Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	37603994	1			T13	11		T16	1		T18	11
all_values[1]	37603994	1			T13	11		T16	1		T18	11
all_values[2]	37603994	1			T13	11		T16	1		T18	11

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134276

1

T13

18

T16

3

T18

18

auto[1]

112677706

1

T13

15

T18

15

T19

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81784507

1

T13

15

T16

3

T18

24

auto[1]

31027475

1

T13

18

T18

9

T19

9

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	46403	1			T13	3		T16	1		T18	4
all_values[0]	auto[0]	auto[1]	1362	1			T13	4		T32	2		T69	2
all_values[0]	auto[1]	auto[0]	37395174	1			T18	7		T19	1		T24	5
all_values[0]	auto[1]	auto[1]	161055	1			T13	4		T19	1		T24	3
all_values[1]	auto[0]	auto[0]	25882	1			T13	2		T16	1		T18	6
all_values[1]	auto[0]	auto[1]	25203	1			T13	3		T18	2		T19	1
all_values[1]	auto[1]	auto[0]	20819606	1			T13	4		T18	1		T19	1
all_values[1]	auto[1]	auto[1]	16733303	1			T13	2		T18	2		T19	3
all_values[2]	auto[0]	auto[0]	26527	1			T13	3		T16	1		T18	4
all_values[2]	auto[0]	auto[1]	8899	1			T13	3		T18	2		T19	1
all_values[2]	auto[1]	auto[0]	23470915	1			T13	3		T18	2		T19	1
all_values[2]	auto[1]	auto[1]	14097653	1			T13	2		T18	3		T19	3