Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.55 98.75 100.00 100.00 98.47 99.49 99.86


Total tests in report: 905
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
47.55 47.55 35.39 35.39 28.45 28.45 51.76 51.76 100.00 100.00 25.87 25.87 79.80 79.80 11.55 11.55 /workspace/coverage/cover_reg_top/30.hmac_intr_test.402304531
83.08 35.54 94.73 59.34 77.36 48.91 56.28 4.52 100.00 0.00 94.78 68.91 94.19 14.39 64.24 52.68 /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.1095652444
95.19 12.10 99.25 4.52 97.20 19.83 89.95 33.67 100.00 0.00 96.74 1.96 95.96 1.77 87.21 22.97 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2862941255
96.69 1.51 99.40 0.15 97.61 0.42 96.73 6.78 100.00 0.00 97.17 0.43 95.96 0.00 89.96 2.75 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1517591306
97.40 0.71 99.40 0.00 97.61 0.00 96.73 0.00 100.00 0.00 97.17 0.00 95.96 0.00 94.91 4.95 /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3276958131
97.95 0.55 99.40 0.00 97.92 0.31 99.50 2.76 100.00 0.00 97.17 0.00 96.72 0.76 94.91 0.00 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3366726491
98.16 0.22 99.40 0.00 97.92 0.00 99.50 0.00 100.00 0.00 97.17 0.00 98.23 1.52 94.91 0.00 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.570931856
98.34 0.18 99.40 0.00 98.13 0.21 100.00 0.50 100.00 0.00 97.17 0.00 98.48 0.25 95.19 0.28 /workspace/coverage/default/4.hmac_sec_cm.3189768867
98.46 0.12 99.40 0.00 98.13 0.00 100.00 0.00 100.00 0.00 97.17 0.00 98.48 0.00 96.01 0.83 /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.3688681946
98.57 0.11 99.40 0.00 98.34 0.21 100.00 0.00 100.00 0.00 97.17 0.00 98.48 0.00 96.56 0.55 /workspace/coverage/default/47.hmac_stress_all.386029267
98.64 0.08 99.40 0.00 98.34 0.00 100.00 0.00 100.00 0.00 97.17 0.00 98.48 0.00 97.11 0.55 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1388064635
98.72 0.08 99.40 0.00 98.34 0.00 100.00 0.00 100.00 0.00 97.17 0.00 98.48 0.00 97.66 0.55 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2168945576
98.80 0.08 99.40 0.00 98.34 0.00 100.00 0.00 100.00 0.00 97.17 0.00 98.48 0.00 98.21 0.55 /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.1651670986
98.86 0.06 99.40 0.00 98.55 0.21 100.00 0.00 100.00 0.00 97.39 0.22 98.48 0.00 98.21 0.00 /workspace/coverage/default/22.hmac_alert_test.3228513275
98.90 0.04 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 98.49 0.28 /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.2140183935
98.94 0.04 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 98.76 0.28 /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.2731561007
98.98 0.04 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.04 0.28 /workspace/coverage/default/3.hmac_burst_wr.4018370545
99.00 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.17 0.14 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1696553463
99.02 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.31 0.14 /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2296038255
99.04 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.45 0.14 /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.4242152273
99.06 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.59 0.14 /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2369508930
99.08 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.72 0.14 /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.4035530367
99.10 0.02 99.40 0.00 98.55 0.00 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.86 0.14 /workspace/coverage/default/15.hmac_back_pressure.692555368
99.11 0.01 99.40 0.00 98.65 0.10 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.86 0.00 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.928453333
99.13 0.01 99.40 0.00 98.75 0.10 100.00 0.00 100.00 0.00 97.39 0.00 98.48 0.00 99.86 0.00 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3737845639

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1647158150
/workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3156508699
/workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2531158381
/workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2065326089
/workspace/coverage/cover_reg_top/0.hmac_csr_rw.3120196137
/workspace/coverage/cover_reg_top/0.hmac_intr_test.1796251211
/workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3540986920
/workspace/coverage/cover_reg_top/0.hmac_tl_errors.1861437699
/workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2905564127
/workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3668842067
/workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1037303630
/workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.140748442
/workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2173498598
/workspace/coverage/cover_reg_top/1.hmac_csr_rw.3271597809
/workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2826322684
/workspace/coverage/cover_reg_top/1.hmac_tl_errors.2137048989
/workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1788499628
/workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.112741435
/workspace/coverage/cover_reg_top/10.hmac_csr_rw.2865726447
/workspace/coverage/cover_reg_top/10.hmac_intr_test.4034795978
/workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1588577144
/workspace/coverage/cover_reg_top/10.hmac_tl_errors.707924913
/workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3166627511
/workspace/coverage/cover_reg_top/11.hmac_csr_rw.4189628135
/workspace/coverage/cover_reg_top/11.hmac_intr_test.2647352362
/workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3090336286
/workspace/coverage/cover_reg_top/11.hmac_tl_errors.1075700763
/workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.907894521
/workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1243012048
/workspace/coverage/cover_reg_top/12.hmac_csr_rw.3559480215
/workspace/coverage/cover_reg_top/12.hmac_intr_test.843131535
/workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1459793280
/workspace/coverage/cover_reg_top/12.hmac_tl_errors.3174006631
/workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2679495005
/workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2964722582
/workspace/coverage/cover_reg_top/13.hmac_csr_rw.4166409840
/workspace/coverage/cover_reg_top/13.hmac_intr_test.1975740360
/workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1096665000
/workspace/coverage/cover_reg_top/13.hmac_tl_errors.2338781024
/workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1386658430
/workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2858123625
/workspace/coverage/cover_reg_top/14.hmac_csr_rw.2839669533
/workspace/coverage/cover_reg_top/14.hmac_intr_test.2606271626
/workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2825805338
/workspace/coverage/cover_reg_top/14.hmac_tl_errors.3338891606
/workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.636781487
/workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1652399096
/workspace/coverage/cover_reg_top/15.hmac_csr_rw.925574552
/workspace/coverage/cover_reg_top/15.hmac_intr_test.292412413
/workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2726161156
/workspace/coverage/cover_reg_top/15.hmac_tl_errors.3855877619
/workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1558789095
/workspace/coverage/cover_reg_top/16.hmac_csr_rw.1964916582
/workspace/coverage/cover_reg_top/16.hmac_intr_test.3199145949
/workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1837846454
/workspace/coverage/cover_reg_top/16.hmac_tl_errors.1240302933
/workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4237457312
/workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2620478492
/workspace/coverage/cover_reg_top/17.hmac_csr_rw.1732402536
/workspace/coverage/cover_reg_top/17.hmac_intr_test.569791823
/workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.947434375
/workspace/coverage/cover_reg_top/17.hmac_tl_errors.3880024777
/workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.786223604
/workspace/coverage/cover_reg_top/18.hmac_csr_rw.2841416496
/workspace/coverage/cover_reg_top/18.hmac_intr_test.2249579197
/workspace/coverage/cover_reg_top/18.hmac_tl_errors.1802614033
/workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1499962457
/workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3863797409
/workspace/coverage/cover_reg_top/19.hmac_csr_rw.1058051319
/workspace/coverage/cover_reg_top/19.hmac_intr_test.1139447441
/workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.432168305
/workspace/coverage/cover_reg_top/19.hmac_tl_errors.371363185
/workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2338317431
/workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2356267928
/workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.634242281
/workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2904151397
/workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3902814349
/workspace/coverage/cover_reg_top/2.hmac_csr_rw.107855421
/workspace/coverage/cover_reg_top/2.hmac_intr_test.4174053026
/workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2130847001
/workspace/coverage/cover_reg_top/2.hmac_tl_errors.1603500796
/workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.170529183
/workspace/coverage/cover_reg_top/20.hmac_intr_test.2724767338
/workspace/coverage/cover_reg_top/21.hmac_intr_test.3142577577
/workspace/coverage/cover_reg_top/22.hmac_intr_test.3193348750
/workspace/coverage/cover_reg_top/23.hmac_intr_test.2213605705
/workspace/coverage/cover_reg_top/24.hmac_intr_test.2426356021
/workspace/coverage/cover_reg_top/25.hmac_intr_test.1874165286
/workspace/coverage/cover_reg_top/26.hmac_intr_test.3429181935
/workspace/coverage/cover_reg_top/27.hmac_intr_test.902529830
/workspace/coverage/cover_reg_top/28.hmac_intr_test.2270375406
/workspace/coverage/cover_reg_top/29.hmac_intr_test.2897626228
/workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.482475516
/workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3011920913
/workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.411554187
/workspace/coverage/cover_reg_top/3.hmac_csr_rw.3574439837
/workspace/coverage/cover_reg_top/3.hmac_intr_test.2111907662
/workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1219830727
/workspace/coverage/cover_reg_top/3.hmac_tl_errors.1881357558
/workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2244226210
/workspace/coverage/cover_reg_top/31.hmac_intr_test.989919075
/workspace/coverage/cover_reg_top/32.hmac_intr_test.1108865815
/workspace/coverage/cover_reg_top/33.hmac_intr_test.1322631466
/workspace/coverage/cover_reg_top/34.hmac_intr_test.483384611
/workspace/coverage/cover_reg_top/35.hmac_intr_test.2967166921
/workspace/coverage/cover_reg_top/36.hmac_intr_test.45988266
/workspace/coverage/cover_reg_top/37.hmac_intr_test.674680640
/workspace/coverage/cover_reg_top/38.hmac_intr_test.979151763
/workspace/coverage/cover_reg_top/39.hmac_intr_test.647825152
/workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2947204540
/workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2237312777
/workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1705779060
/workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.652078262
/workspace/coverage/cover_reg_top/4.hmac_csr_rw.292883597
/workspace/coverage/cover_reg_top/4.hmac_intr_test.3836459849
/workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2518847785
/workspace/coverage/cover_reg_top/4.hmac_tl_errors.2419728391
/workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2845374702
/workspace/coverage/cover_reg_top/40.hmac_intr_test.2842936789
/workspace/coverage/cover_reg_top/41.hmac_intr_test.981008829
/workspace/coverage/cover_reg_top/42.hmac_intr_test.3480052152
/workspace/coverage/cover_reg_top/43.hmac_intr_test.44314867
/workspace/coverage/cover_reg_top/44.hmac_intr_test.518013114
/workspace/coverage/cover_reg_top/45.hmac_intr_test.3066378516
/workspace/coverage/cover_reg_top/46.hmac_intr_test.405895886
/workspace/coverage/cover_reg_top/47.hmac_intr_test.3394281412
/workspace/coverage/cover_reg_top/48.hmac_intr_test.561209012
/workspace/coverage/cover_reg_top/49.hmac_intr_test.2159758974
/workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3497245047
/workspace/coverage/cover_reg_top/5.hmac_csr_rw.1414973445
/workspace/coverage/cover_reg_top/5.hmac_intr_test.900906055
/workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2928096512
/workspace/coverage/cover_reg_top/5.hmac_tl_errors.1996334685
/workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4133334421
/workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.448102940
/workspace/coverage/cover_reg_top/6.hmac_csr_rw.3800387512
/workspace/coverage/cover_reg_top/6.hmac_intr_test.2298614673
/workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1158127596
/workspace/coverage/cover_reg_top/6.hmac_tl_errors.3044035927
/workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4244377121
/workspace/coverage/cover_reg_top/7.hmac_csr_rw.2512532272
/workspace/coverage/cover_reg_top/7.hmac_intr_test.3189631960
/workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.351953927
/workspace/coverage/cover_reg_top/7.hmac_tl_errors.1434084007
/workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.878203440
/workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.915963757
/workspace/coverage/cover_reg_top/8.hmac_csr_rw.141583353
/workspace/coverage/cover_reg_top/8.hmac_intr_test.2017121595
/workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3012242237
/workspace/coverage/cover_reg_top/8.hmac_tl_errors.1659426712
/workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.138305662
/workspace/coverage/cover_reg_top/9.hmac_csr_rw.4158759748
/workspace/coverage/cover_reg_top/9.hmac_intr_test.1954891061
/workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4019892511
/workspace/coverage/cover_reg_top/9.hmac_tl_errors.3040970572
/workspace/coverage/default/0.hmac_alert_test.3344339129
/workspace/coverage/default/0.hmac_back_pressure.638925302
/workspace/coverage/default/0.hmac_burst_wr.4079237619
/workspace/coverage/default/0.hmac_datapath_stress.2413947386
/workspace/coverage/default/0.hmac_error.3879432064
/workspace/coverage/default/0.hmac_long_msg.1055285021
/workspace/coverage/default/0.hmac_sec_cm.889780899
/workspace/coverage/default/0.hmac_smoke.1666900881
/workspace/coverage/default/0.hmac_stress_all.867586578
/workspace/coverage/default/0.hmac_stress_all_with_rand_reset.630413729
/workspace/coverage/default/0.hmac_test_hmac_vectors.1142886047
/workspace/coverage/default/0.hmac_wipe_secret.2956655361
/workspace/coverage/default/1.hmac_alert_test.2515781074
/workspace/coverage/default/1.hmac_back_pressure.4024619596
/workspace/coverage/default/1.hmac_burst_wr.1420944579
/workspace/coverage/default/1.hmac_datapath_stress.1957492146
/workspace/coverage/default/1.hmac_error.4199647635
/workspace/coverage/default/1.hmac_long_msg.2299954131
/workspace/coverage/default/1.hmac_sec_cm.898079019
/workspace/coverage/default/1.hmac_smoke.1424174797
/workspace/coverage/default/1.hmac_stress_all.1608768606
/workspace/coverage/default/1.hmac_stress_all_with_rand_reset.153953201
/workspace/coverage/default/1.hmac_test_hmac_vectors.548900303
/workspace/coverage/default/1.hmac_test_sha_vectors.2359046280
/workspace/coverage/default/1.hmac_wipe_secret.3524474459
/workspace/coverage/default/10.hmac_alert_test.3972997602
/workspace/coverage/default/10.hmac_back_pressure.3516206884
/workspace/coverage/default/10.hmac_burst_wr.1204728332
/workspace/coverage/default/10.hmac_datapath_stress.2076330579
/workspace/coverage/default/10.hmac_error.3102616453
/workspace/coverage/default/10.hmac_long_msg.315490330
/workspace/coverage/default/10.hmac_smoke.2291614090
/workspace/coverage/default/10.hmac_stress_all.520552095
/workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2466917103
/workspace/coverage/default/10.hmac_test_hmac_vectors.2881703940
/workspace/coverage/default/10.hmac_test_sha_vectors.2436578237
/workspace/coverage/default/10.hmac_wipe_secret.1980702220
/workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2574648952
/workspace/coverage/default/101.hmac_stress_all_with_rand_reset.4056727318
/workspace/coverage/default/104.hmac_stress_all_with_rand_reset.288885326
/workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2554311812
/workspace/coverage/default/106.hmac_stress_all_with_rand_reset.230648951
/workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3869788060
/workspace/coverage/default/108.hmac_stress_all_with_rand_reset.3700182026
/workspace/coverage/default/109.hmac_stress_all_with_rand_reset.461432643
/workspace/coverage/default/11.hmac_alert_test.1945467856
/workspace/coverage/default/11.hmac_back_pressure.695220844
/workspace/coverage/default/11.hmac_burst_wr.1174582961
/workspace/coverage/default/11.hmac_datapath_stress.2987595326
/workspace/coverage/default/11.hmac_error.2133692259
/workspace/coverage/default/11.hmac_long_msg.1448422033
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/workspace/coverage/default/79.hmac_stress_all_with_rand_reset.1028785566
/workspace/coverage/default/8.hmac_alert_test.4279349284
/workspace/coverage/default/8.hmac_back_pressure.3624742936
/workspace/coverage/default/8.hmac_burst_wr.28863830
/workspace/coverage/default/8.hmac_datapath_stress.1878338897
/workspace/coverage/default/8.hmac_error.2077183921
/workspace/coverage/default/8.hmac_long_msg.564571331
/workspace/coverage/default/8.hmac_smoke.3947007329
/workspace/coverage/default/8.hmac_stress_all.526581931
/workspace/coverage/default/8.hmac_stress_all_with_rand_reset.643045154
/workspace/coverage/default/8.hmac_test_hmac_vectors.641923080
/workspace/coverage/default/8.hmac_test_sha_vectors.3652057825
/workspace/coverage/default/8.hmac_wipe_secret.1440432975
/workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2659491483
/workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4228664960
/workspace/coverage/default/82.hmac_stress_all_with_rand_reset.222689887
/workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2524225641
/workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3283059783
/workspace/coverage/default/85.hmac_stress_all_with_rand_reset.1150866156
/workspace/coverage/default/86.hmac_stress_all_with_rand_reset.1729234476
/workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1975810143
/workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3055193824
/workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3794509100
/workspace/coverage/default/9.hmac_alert_test.1984604966
/workspace/coverage/default/9.hmac_back_pressure.3730300469
/workspace/coverage/default/9.hmac_burst_wr.332255306
/workspace/coverage/default/9.hmac_datapath_stress.1633660913
/workspace/coverage/default/9.hmac_error.1055995566
/workspace/coverage/default/9.hmac_long_msg.3008300027
/workspace/coverage/default/9.hmac_smoke.1624639707
/workspace/coverage/default/9.hmac_stress_all.2947143397
/workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1975941989
/workspace/coverage/default/9.hmac_test_hmac_vectors.1494265731
/workspace/coverage/default/9.hmac_test_sha_vectors.274116268
/workspace/coverage/default/9.hmac_wipe_secret.3138465888
/workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3281953307
/workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2813009274
/workspace/coverage/default/92.hmac_stress_all_with_rand_reset.2427892179
/workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1194567513
/workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2891911255
/workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3998880882
/workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3376466575
/workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1697738612
/workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2790439220
/workspace/coverage/default/99.hmac_stress_all_with_rand_reset.881779656



Total test records in report: 905
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T13 /workspace/coverage/cover_reg_top/30.hmac_intr_test.402304531 Feb 07 01:46:29 PM PST 24 Feb 07 01:46:31 PM PST 24 19951912 ps
T14 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1414973445 Feb 07 01:46:12 PM PST 24 Feb 07 01:46:14 PM PST 24 19995025 ps
T15 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.292883597 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 42867864 ps
T16 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1881357558 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:10 PM PST 24 327910901 ps
T17 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2237312777 Feb 07 01:46:13 PM PST 24 Feb 07 01:46:17 PM PST 24 927800239 ps
T18 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1388064635 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:02 PM PST 24 35936319 ps
T19 /workspace/coverage/cover_reg_top/41.hmac_intr_test.981008829 Feb 07 01:46:37 PM PST 24 Feb 07 01:46:38 PM PST 24 21381824 ps
T20 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3574439837 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:11 PM PST 24 22899158 ps
T21 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.925574552 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:22 PM PST 24 64273199 ps
T22 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2862941255 Feb 07 01:46:22 PM PST 24 Feb 07 02:00:08 PM PST 24 256693514833 ps
T24 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2298614673 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:12 PM PST 24 14238666 ps
T32 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1108865815 Feb 07 01:46:28 PM PST 24 Feb 07 01:46:30 PM PST 24 11822472 ps
T23 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1603500796 Feb 07 01:45:57 PM PST 24 Feb 07 01:46:00 PM PST 24 494008820 ps
T51 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1517591306 Feb 07 01:46:23 PM PST 24 Feb 07 01:46:27 PM PST 24 74688603 ps
T69 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3836459849 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 37446044 ps
T25 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3338891606 Feb 07 01:46:27 PM PST 24 Feb 07 01:46:29 PM PST 24 48909991 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2249579197 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:23 PM PST 24 41189113 ps
T70 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2159758974 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:31 PM PST 24 13386473 ps
T26 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2338781024 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:25 PM PST 24 292350961 ps
T52 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1788499628 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:03 PM PST 24 142535257 ps
T71 /workspace/coverage/cover_reg_top/5.hmac_intr_test.900906055 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:13 PM PST 24 15621747 ps
T72 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4189628135 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:25 PM PST 24 41675381 ps
T146 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1796251211 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:02 PM PST 24 23275477 ps
T27 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3855877619 Feb 07 01:46:17 PM PST 24 Feb 07 01:46:21 PM PST 24 58537378 ps
T28 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1652399096 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 71840646 ps
T76 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1705779060 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:10 PM PST 24 41996810 ps
T73 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3366726491 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:22 PM PST 24 281431246 ps
T86 /workspace/coverage/cover_reg_top/34.hmac_intr_test.483384611 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:32 PM PST 24 12845499 ps
T87 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4019892511 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 32464814 ps
T66 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.636781487 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:21 PM PST 24 116894294 ps
T74 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2244226210 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:11 PM PST 24 97246975 ps
T88 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2826322684 Feb 07 01:46:04 PM PST 24 Feb 07 01:46:06 PM PST 24 26056188 ps
T29 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.371363185 Feb 07 01:46:23 PM PST 24 Feb 07 01:46:29 PM PST 24 277548232 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2130847001 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 29832572 ps
T77 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3540986920 Feb 07 01:46:02 PM PST 24 Feb 07 01:46:06 PM PST 24 54264968 ps
T30 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3040970572 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:24 PM PST 24 101253657 ps
T78 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2865726447 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:20 PM PST 24 20789182 ps
T145 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2647352362 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:22 PM PST 24 23366571 ps
T155 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2905564127 Feb 07 01:46:01 PM PST 24 Feb 07 01:46:04 PM PST 24 54866418 ps
T31 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.112741435 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 30336687 ps
T156 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1037303630 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:04 PM PST 24 144417355 ps
T157 /workspace/coverage/cover_reg_top/37.hmac_intr_test.674680640 Feb 07 01:46:32 PM PST 24 Feb 07 01:46:34 PM PST 24 31192301 ps
T75 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3044035927 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:11 PM PST 24 488370831 ps
T102 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3012242237 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:25 PM PST 24 321119481 ps
T158 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3902814349 Feb 07 01:46:06 PM PST 24 Feb 07 01:46:09 PM PST 24 24218792 ps
T159 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4244377121 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 18873483 ps
T149 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.878203440 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:11 PM PST 24 641850754 ps
T103 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.947434375 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:24 PM PST 24 81704850 ps
T160 /workspace/coverage/cover_reg_top/28.hmac_intr_test.2270375406 Feb 07 01:46:37 PM PST 24 Feb 07 01:46:39 PM PST 24 69488808 ps
T161 /workspace/coverage/cover_reg_top/15.hmac_intr_test.292412413 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:20 PM PST 24 17729430 ps
T162 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.448102940 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:11 PM PST 24 24271666 ps
T152 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.652078262 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:14 PM PST 24 43375318 ps
T79 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2825805338 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:20 PM PST 24 249341666 ps
T163 /workspace/coverage/cover_reg_top/43.hmac_intr_test.44314867 Feb 07 01:46:37 PM PST 24 Feb 07 01:46:38 PM PST 24 47861525 ps
T148 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1696553463 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:10 PM PST 24 178580829 ps
T164 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2518847785 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:09 PM PST 24 31141194 ps
T165 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2839669533 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:31 PM PST 24 31754417 ps
T166 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2111907662 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 39204762 ps
T167 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2419728391 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 600094132 ps
T80 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3271597809 Feb 07 01:46:03 PM PST 24 Feb 07 01:46:05 PM PST 24 56037274 ps
T81 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2947204540 Feb 07 01:46:13 PM PST 24 Feb 07 01:46:15 PM PST 24 63682605 ps
T67 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.928453333 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:25 PM PST 24 164995068 ps
T147 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1499962457 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:27 PM PST 24 678320901 ps
T168 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2897626228 Feb 07 01:46:32 PM PST 24 Feb 07 01:46:34 PM PST 24 36089191 ps
T82 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.570931856 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:15 PM PST 24 477189244 ps
T169 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2841416496 Feb 07 01:46:25 PM PST 24 Feb 07 01:46:27 PM PST 24 23926933 ps
T170 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1588577144 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:23 PM PST 24 70156881 ps
T171 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4174053026 Feb 07 01:45:59 PM PST 24 Feb 07 01:46:00 PM PST 24 22465643 ps
T172 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3090336286 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 19656713 ps
T173 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1075700763 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:33 PM PST 24 148263599 ps
T174 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2967166921 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:33 PM PST 24 16340241 ps
T175 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2842936789 Feb 07 01:46:28 PM PST 24 Feb 07 01:46:30 PM PST 24 42880600 ps
T176 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2338317431 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:32 PM PST 24 69489461 ps
T83 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1964916582 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:23 PM PST 24 80465955 ps
T177 /workspace/coverage/cover_reg_top/36.hmac_intr_test.45988266 Feb 07 01:46:33 PM PST 24 Feb 07 01:46:35 PM PST 24 19214989 ps
T178 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3166627511 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:23 PM PST 24 126759218 ps
T153 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.411554187 Feb 07 01:46:11 PM PST 24 Feb 07 01:46:15 PM PST 24 25194807 ps
T179 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.707924913 Feb 07 01:46:17 PM PST 24 Feb 07 01:46:20 PM PST 24 109030679 ps
T84 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2356267928 Feb 07 01:46:06 PM PST 24 Feb 07 01:46:09 PM PST 24 106991409 ps
T180 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2213605705 Feb 07 01:46:32 PM PST 24 Feb 07 01:46:34 PM PST 24 18796327 ps
T181 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3066378516 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:33 PM PST 24 11663849 ps
T182 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4034795978 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:25 PM PST 24 32165940 ps
T183 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1647158150 Feb 07 01:45:59 PM PST 24 Feb 07 01:46:01 PM PST 24 260301669 ps
T184 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2964722582 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:23 PM PST 24 50402555 ps
T185 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.107855421 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:09 PM PST 24 20735083 ps
T150 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2168945576 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:21 PM PST 24 659275213 ps
T186 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.432168305 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:26 PM PST 24 157938258 ps
T187 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3429181935 Feb 07 01:46:35 PM PST 24 Feb 07 01:46:37 PM PST 24 21621661 ps
T188 /workspace/coverage/cover_reg_top/7.hmac_intr_test.3189631960 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:12 PM PST 24 41794127 ps
T189 /workspace/coverage/cover_reg_top/44.hmac_intr_test.518013114 Feb 07 01:46:35 PM PST 24 Feb 07 01:46:36 PM PST 24 18019587 ps
T190 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3880024777 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 82259610 ps
T191 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.170529183 Feb 07 01:46:01 PM PST 24 Feb 07 01:46:06 PM PST 24 78425381 ps
T192 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1802614033 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:27 PM PST 24 599874038 ps
T193 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1659426712 Feb 07 01:46:11 PM PST 24 Feb 07 01:46:15 PM PST 24 115133624 ps
T194 /workspace/coverage/cover_reg_top/25.hmac_intr_test.1874165286 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:31 PM PST 24 42854153 ps
T195 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1158127596 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 398429172 ps
T196 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4133334421 Feb 07 01:46:13 PM PST 24 Feb 07 01:46:15 PM PST 24 168688068 ps
T197 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.140748442 Feb 07 01:46:01 PM PST 24 Feb 07 01:46:05 PM PST 24 56565636 ps
T198 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.786223604 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 21316238 ps
T154 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2065326089 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:09 PM PST 24 19105538 ps
T199 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1732402536 Feb 07 01:46:26 PM PST 24 Feb 07 01:46:28 PM PST 24 89509781 ps
T85 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2904151397 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:02 PM PST 24 87616474 ps
T200 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2017121595 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:10 PM PST 24 14127155 ps
T201 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1975740360 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:19 PM PST 24 49471945 ps
T202 /workspace/coverage/cover_reg_top/48.hmac_intr_test.561209012 Feb 07 01:46:29 PM PST 24 Feb 07 01:46:30 PM PST 24 14546126 ps
T1 /workspace/coverage/default/44.hmac_error.1625468184 Feb 07 03:31:30 PM PST 24 Feb 07 03:32:37 PM PST 24 5174667760 ps
T2 /workspace/coverage/default/22.hmac_wipe_secret.3020129999 Feb 07 03:27:39 PM PST 24 Feb 07 03:28:59 PM PST 24 4572374515 ps
T3 /workspace/coverage/default/15.hmac_wipe_secret.683184627 Feb 07 03:26:22 PM PST 24 Feb 07 03:27:16 PM PST 24 11917674979 ps
T4 /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.2613420070 Feb 07 03:35:53 PM PST 24 Feb 07 03:40:52 PM PST 24 11858335007 ps
T7 /workspace/coverage/default/38.hmac_long_msg.967848915 Feb 07 03:30:14 PM PST 24 Feb 07 03:30:36 PM PST 24 1557025885 ps
T9 /workspace/coverage/default/7.hmac_smoke.1590632004 Feb 07 03:24:46 PM PST 24 Feb 07 03:24:49 PM PST 24 837302151 ps
T10 /workspace/coverage/default/12.hmac_smoke.2756219565 Feb 07 03:25:47 PM PST 24 Feb 07 03:25:50 PM PST 24 577705120 ps
T5 /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.1095652444 Feb 07 03:36:32 PM PST 24 Feb 07 04:04:56 PM PST 24 132361289514 ps
T11 /workspace/coverage/default/8.hmac_test_hmac_vectors.641923080 Feb 07 03:25:13 PM PST 24 Feb 07 03:25:15 PM PST 24 34401466 ps
T12 /workspace/coverage/default/47.hmac_stress_all.386029267 Feb 07 03:32:01 PM PST 24 Feb 07 03:34:23 PM PST 24 7864294896 ps
T40 /workspace/coverage/default/42.hmac_test_hmac_vectors.2366259944 Feb 07 03:31:09 PM PST 24 Feb 07 03:31:11 PM PST 24 32735599 ps
T41 /workspace/coverage/default/27.hmac_test_hmac_vectors.1317481009 Feb 07 03:28:33 PM PST 24 Feb 07 03:28:34 PM PST 24 85415376 ps
T42 /workspace/coverage/default/7.hmac_error.2704044088 Feb 07 03:25:01 PM PST 24 Feb 07 03:25:24 PM PST 24 5059506780 ps
T6 /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3276958131 Feb 07 03:32:34 PM PST 24 Feb 07 04:50:36 PM PST 24 142298682971 ps
T43 /workspace/coverage/default/39.hmac_error.162423694 Feb 07 03:30:24 PM PST 24 Feb 07 03:30:42 PM PST 24 2379684076 ps
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