Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18828587

1

T1

1281

T2

6169

T3

3559

auto[1]

9378453

1

T1

2677

T2

5953

T3

4668

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9429703

1

T1

1336

T2

5830

T3

4033

auto[1]

18777337

1

T1

2622

T2

6292

T3

4194

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16487615

1

T1

1214

T2

6406

T3

4675

auto[1]

11719425

1

T1

2744

T2

5716

T3

3552

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	15905761	1			T1	3123		T2	10517		T3	7097
fifo_depth[1]	1421931	1			T1	166		T2	730		T3	491
fifo_depth[2]	1280257	1			T1	158		T2	486		T3	336
fifo_depth[3]	1080047	1			T1	136		T2	242		T3	186
fifo_depth[4]	1050546	1			T1	107		T2	103		T3	91
fifo_depth[5]	886760	1			T1	85		T2	27		T3	19
fifo_depth[6]	920629	1			T1	72		T2	9		T3	6
fifo_depth[7]	778935	1			T1	50		T2	8		T3	1
fifo_depth[8]	932761	1			T1	30		T4	1746		T10	7
fifo_depth[9]	544987	1			T1	15		T4	989		T10	4
fifo_depth[10]	559300	1			T1	7		T4	1442		T10	1
fifo_depth[11]	342775	1			T1	4		T4	913		T10	2
fifo_depth[12]	586982	1			T1	4		T4	2119		T10	1
fifo_depth[13]	264001	1			T1	1		T4	897		T10	1
fifo_depth[14]	427013	1			T4	1625		T5	1742		T6	5962
fifo_depth[15]	243058	1			T4	652		T5	832		T6	3980
fifo_depth[16]	981297	1			T4	3132		T5	5041		T6	14319

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12301279

1

T1

835

T2

1605

T3

1130

auto[1]

15905761

1

T1

3123

T2

10517

T3

7097

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27225743

1

T1

3958

T2

12122

T3

8227

auto[1]

981297

1

T4

3132

T5

5041

T6

14319

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

943203

1

T1

40

T2

173

T3

78

auto[0]

auto[0]

auto[0]

auto[1]

983646

1

T1

97

T2

181

T3

297

auto[0]

auto[0]

auto[1]

auto[0]

3302781

1

T1

38

T2

223

T3

118

auto[0]

auto[0]

auto[1]

auto[1]

973268

1

T2

260

T3

140

T4

1132

auto[0]

auto[1]

auto[0]

auto[0]

1518160

1

T2

220

T3

73

T4

891

auto[0]

auto[1]

auto[0]

auto[1]

1541488

1

T1

51

T2

210

T3

107

auto[0]

auto[1]

auto[1]

auto[0]

1533946

1

T1

163

T2

205

T3

221

auto[0]

auto[1]

auto[1]

auto[1]

1504787

1

T1

446

T2

133

T3

96

auto[1]

auto[0]

auto[0]

auto[0]

810694

1

T1

56

T2

1039

T3

511

auto[1]

auto[0]

auto[0]

auto[1]

825729

1

T1

401

T2

1167

T3

1918

auto[1]

auto[0]

auto[1]

auto[0]

7840021

1

T1

190

T2

1583

T3

795

auto[1]

auto[0]

auto[1]

auto[1]

808273

1

T1

392

T2

1780

T3

818

auto[1]

auto[1]

auto[0]

auto[0]

1426870

1

T1

1

T2

1460

T3

382

auto[1]

auto[1]

auto[0]

auto[1]

1379913

1

T1

690

T2

1380

T3

667

auto[1]

auto[1]

auto[1]

auto[0]

1452912

1

T1

793

T2

1266

T3

1381

auto[1]

auto[1]

auto[1]

auto[1]

1361349

1

T1

600

T2

842

T3

625

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

1641736

1

T1

96

T2

1212

T3

589

auto[0]

auto[0]

auto[0]

auto[1]

1688646

1

T1

498

T2

1348

T3

2215

auto[0]

auto[0]

auto[1]

auto[0]

11023980

1

T1

228

T2

1806

T3

913

auto[0]

auto[0]

auto[1]

auto[1]

1665689

1

T1

392

T2

2040

T3

958

auto[0]

auto[1]

auto[0]

auto[0]

2816822

1

T1

1

T2

1680

T3

455

auto[0]

auto[1]

auto[0]

auto[1]

2786595

1

T1

741

T2

1590

T3

774

auto[0]

auto[1]

auto[1]

auto[0]

2869952

1

T1

956

T2

1471

T3

1602

auto[0]

auto[1]

auto[1]

auto[1]

2732323

1

T1

1046

T2

975

T3

721

auto[1]

auto[0]

auto[0]

auto[0]

112161

1

T4

1493

T5

849

T6

1344

auto[1]

auto[0]

auto[0]

auto[1]

120729

1

T4

376

T5

334

T6

1539

auto[1]

auto[0]

auto[1]

auto[0]

118822

1

T4

213

T5

428

T6

912

auto[1]

auto[0]

auto[1]

auto[1]

115852

1

T4

86

T5

3

T6

2087

auto[1]

auto[1]

auto[0]

auto[0]

128208

1

T4

146

T5

2335

T6

1562

auto[1]

auto[1]

auto[0]

auto[1]

134806

1

T4

347

T5

543

T6

2184

auto[1]

auto[1]

auto[1]

auto[0]

116906

1

T4

337

T5

12

T6

3366

auto[1]

auto[1]

auto[1]

auto[1]

133813

1

T4

134

T5

537

T6

1325

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	810694	1			T1	56		T2	1039		T3	511
fifo_depth[0]	auto[0]	auto[0]	auto[1]	825729	1			T1	401		T2	1167		T3	1918
fifo_depth[0]	auto[0]	auto[1]	auto[0]	7840021	1			T1	190		T2	1583		T3	795
fifo_depth[0]	auto[0]	auto[1]	auto[1]	808273	1			T1	392		T2	1780		T3	818
fifo_depth[0]	auto[1]	auto[0]	auto[0]	1426870	1			T1	1		T2	1460		T3	382
fifo_depth[0]	auto[1]	auto[0]	auto[1]	1379913	1			T1	690		T2	1380		T3	667
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1452912	1			T1	793		T2	1266		T3	1381
fifo_depth[0]	auto[1]	auto[1]	auto[1]	1361349	1			T1	600		T2	842		T3	625
fifo_depth[1]	auto[0]	auto[0]	auto[0]	73300	1			T1	10		T2	76		T3	30
fifo_depth[1]	auto[0]	auto[0]	auto[1]	77158	1			T1	33		T2	86		T3	121
fifo_depth[1]	auto[0]	auto[1]	auto[0]	584478	1			T1	15		T2	99		T3	57
fifo_depth[1]	auto[0]	auto[1]	auto[1]	74285	1			T2	112		T3	63		T4	40
fifo_depth[1]	auto[1]	auto[0]	auto[0]	153316	1			T2	109		T3	35		T4	18
fifo_depth[1]	auto[1]	auto[0]	auto[1]	152272	1			T1	9		T2	93		T3	47
fifo_depth[1]	auto[1]	auto[1]	auto[0]	156908	1			T1	23		T2	96		T3	92
fifo_depth[1]	auto[1]	auto[1]	auto[1]	150214	1			T1	76		T2	59		T3	46
fifo_depth[2]	auto[0]	auto[0]	auto[0]	67351	1			T1	3		T2	48		T3	23
fifo_depth[2]	auto[0]	auto[0]	auto[1]	72446	1			T1	31		T2	56		T3	100
fifo_depth[2]	auto[0]	auto[1]	auto[0]	508809	1			T1	18		T2	69		T3	31
fifo_depth[2]	auto[0]	auto[1]	auto[1]	69104	1			T2	83		T3	44		T4	52
fifo_depth[2]	auto[1]	auto[0]	auto[0]	139832	1			T2	64		T3	15		T4	32
fifo_depth[2]	auto[1]	auto[0]	auto[1]	141305	1			T1	11		T2	68		T3	33
fifo_depth[2]	auto[1]	auto[1]	auto[0]	142794	1			T1	31		T2	64		T3	63
fifo_depth[2]	auto[1]	auto[1]	auto[1]	138616	1			T1	64		T2	34		T3	27
fifo_depth[3]	auto[0]	auto[0]	auto[0]	58437	1			T1	6		T2	26		T3	15
fifo_depth[3]	auto[0]	auto[0]	auto[1]	62563	1			T1	26		T2	23		T3	40
fifo_depth[3]	auto[0]	auto[1]	auto[0]	407441	1			T1	5		T2	36		T3	21
fifo_depth[3]	auto[0]	auto[1]	auto[1]	59643	1			T2	40		T3	16		T4	64
fifo_depth[3]	auto[1]	auto[0]	auto[0]	122499	1			T2	32		T3	13		T4	29
fifo_depth[3]	auto[1]	auto[0]	auto[1]	123664	1			T1	6		T2	28		T3	19
fifo_depth[3]	auto[1]	auto[1]	auto[0]	124791	1			T1	22		T2	29		T3	43
fifo_depth[3]	auto[1]	auto[1]	auto[1]	121009	1			T1	71		T2	28		T3	19
fifo_depth[4]	auto[0]	auto[0]	auto[0]	69514	1			T1	2		T2	15		T3	9
fifo_depth[4]	auto[0]	auto[0]	auto[1]	71277	1			T1	7		T2	13		T3	27
fifo_depth[4]	auto[0]	auto[1]	auto[0]	325216	1			T2	18		T3	7		T4	511
fifo_depth[4]	auto[0]	auto[1]	auto[1]	70062	1			T2	18		T3	12		T4	41
fifo_depth[4]	auto[1]	auto[0]	auto[0]	128183	1			T2	9		T3	9		T4	39
fifo_depth[4]	auto[1]	auto[0]	auto[1]	130919	1			T1	9		T2	16		T3	8
fifo_depth[4]	auto[1]	auto[1]	auto[0]	130392	1			T1	17		T2	8		T3	17
fifo_depth[4]	auto[1]	auto[1]	auto[1]	124983	1			T1	72		T2	6		T3	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	55211	1			T1	6		T2	5		T4	123
fifo_depth[5]	auto[0]	auto[0]	auto[1]	58809	1			T2	2		T3	6		T4	53
fifo_depth[5]	auto[0]	auto[1]	auto[0]	267464	1			T3	1		T4	324		T7	2
fifo_depth[5]	auto[0]	auto[1]	auto[1]	57004	1			T2	5		T3	3		T4	59
fifo_depth[5]	auto[1]	auto[0]	auto[0]	111564	1			T2	1		T3	1		T4	23
fifo_depth[5]	auto[1]	auto[0]	auto[1]	112938	1			T1	4		T2	4		T4	75
fifo_depth[5]	auto[1]	auto[1]	auto[0]	113055	1			T1	12		T2	4		T3	6
fifo_depth[5]	auto[1]	auto[1]	auto[1]	110715	1			T1	63		T2	6		T3	2
fifo_depth[6]	auto[0]	auto[0]	auto[0]	65603	1			T1	6		T3	1		T4	459
fifo_depth[6]	auto[0]	auto[0]	auto[1]	66332	1			T2	1		T3	2		T4	43
fifo_depth[6]	auto[0]	auto[1]	auto[0]	245355	1			T3	1		T4	398		T5	2306
fifo_depth[6]	auto[0]	auto[1]	auto[1]	65035	1			T2	1		T3	2		T4	64
fifo_depth[6]	auto[1]	auto[0]	auto[0]	119298	1			T2	4		T4	34		T10	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	121255	1			T1	7		T4	203		T10	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	121005	1			T1	11		T2	3		T4	260
fifo_depth[6]	auto[1]	auto[1]	auto[1]	116746	1			T1	48		T4	23		T10	2
fifo_depth[7]	auto[0]	auto[0]	auto[0]	54036	1			T1	5		T2	3		T4	485
fifo_depth[7]	auto[0]	auto[0]	auto[1]	57133	1			T3	1		T4	41		T5	259
fifo_depth[7]	auto[0]	auto[1]	auto[0]	195492	1			T2	1		T4	244		T5	1853
fifo_depth[7]	auto[0]	auto[1]	auto[1]	55133	1			T2	1		T4	75		T5	211
fifo_depth[7]	auto[1]	auto[0]	auto[0]	104257	1			T2	1		T4	21		T10	3
fifo_depth[7]	auto[1]	auto[0]	auto[1]	105313	1			T1	3		T2	1		T4	150
fifo_depth[7]	auto[1]	auto[1]	auto[0]	104807	1			T1	12		T2	1		T4	171
fifo_depth[7]	auto[1]	auto[1]	auto[1]	102764	1			T1	30		T4	26		T10	1
fifo_depth[8]	auto[0]	auto[0]	auto[0]	84762	1			T1	1		T4	637		T5	195
fifo_depth[8]	auto[0]	auto[0]	auto[1]	85655	1			T4	34		T5	415		T12	25
fifo_depth[8]	auto[0]	auto[1]	auto[0]	181067	1			T4	286		T5	1399		T12	3
fifo_depth[8]	auto[0]	auto[1]	auto[1]	79702	1			T4	189		T5	166		T6	1248
fifo_depth[8]	auto[1]	auto[0]	auto[0]	125927	1			T4	27		T10	2		T5	484
fifo_depth[8]	auto[1]	auto[0]	auto[1]	124782	1			T1	2		T4	164		T5	175
fifo_depth[8]	auto[1]	auto[1]	auto[0]	126019	1			T1	12		T4	226		T10	5
fifo_depth[8]	auto[1]	auto[1]	auto[1]	124847	1			T1	15		T4	183		T5	204
fifo_depth[9]	auto[0]	auto[0]	auto[0]	42993	1			T1	1		T4	437		T5	115
fifo_depth[9]	auto[0]	auto[0]	auto[1]	45087	1			T4	26		T5	205		T6	653
fifo_depth[9]	auto[0]	auto[1]	auto[0]	113018	1			T4	153		T5	917		T6	1601
fifo_depth[9]	auto[0]	auto[1]	auto[1]	44524	1			T4	41		T5	119		T6	691
fifo_depth[9]	auto[1]	auto[0]	auto[0]	73611	1			T4	21		T10	1		T5	121
fifo_depth[9]	auto[1]	auto[0]	auto[1]	75526	1			T4	135		T5	113		T6	2084
fifo_depth[9]	auto[1]	auto[1]	auto[0]	75620	1			T1	7		T4	134		T10	3
fifo_depth[9]	auto[1]	auto[1]	auto[1]	74608	1			T1	7		T4	42		T5	164
fifo_depth[10]	auto[0]	auto[0]	auto[0]	52668	1			T4	374		T5	95		T6	880
fifo_depth[10]	auto[0]	auto[0]	auto[1]	55164	1			T4	20		T5	338		T12	2
fifo_depth[10]	auto[0]	auto[1]	auto[0]	95230	1			T4	247		T5	580		T12	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	56224	1			T4	163		T5	107		T6	949
fifo_depth[10]	auto[1]	auto[0]	auto[0]	75173	1			T4	27		T5	261		T12	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	74265	1			T4	158		T10	1		T5	79
fifo_depth[10]	auto[1]	auto[1]	auto[0]	76594	1			T1	7		T4	188		T5	108
fifo_depth[10]	auto[1]	auto[1]	auto[1]	73982	1			T4	265		T5	145		T12	2
fifo_depth[11]	auto[0]	auto[0]	auto[0]	32808	1			T4	406		T5	64		T6	611
fifo_depth[11]	auto[0]	auto[0]	auto[1]	34107	1			T4	18		T5	145		T12	2
fifo_depth[11]	auto[0]	auto[1]	auto[0]	58159	1			T4	111		T5	282		T6	792
fifo_depth[11]	auto[0]	auto[1]	auto[1]	36520	1			T4	22		T5	43		T6	676
fifo_depth[11]	auto[1]	auto[0]	auto[0]	43942	1			T4	16		T10	2		T5	141
fifo_depth[11]	auto[1]	auto[0]	auto[1]	46795	1			T4	112		T5	57		T6	1428
fifo_depth[11]	auto[1]	auto[1]	auto[0]	46121	1			T1	4		T4	71		T5	75
fifo_depth[11]	auto[1]	auto[1]	auto[1]	44323	1			T4	157		T5	126		T6	916
fifo_depth[12]	auto[0]	auto[0]	auto[0]	69789	1			T4	443		T5	274		T6	1742
fifo_depth[12]	auto[0]	auto[0]	auto[1]	68781	1			T4	15		T5	481		T6	1079
fifo_depth[12]	auto[0]	auto[1]	auto[0]	77826	1			T4	404		T5	169		T6	1110
fifo_depth[12]	auto[0]	auto[1]	auto[1]	67853	1			T4	114		T5	25		T6	1033
fifo_depth[12]	auto[1]	auto[0]	auto[0]	75247	1			T4	259		T10	1		T5	395
fifo_depth[12]	auto[1]	auto[0]	auto[1]	75454	1			T4	114		T5	70		T12	2
fifo_depth[12]	auto[1]	auto[1]	auto[0]	78563	1			T1	4		T4	533		T5	51
fifo_depth[12]	auto[1]	auto[1]	auto[1]	73469	1			T4	237		T5	447		T6	1293
fifo_depth[13]	auto[0]	auto[0]	auto[0]	30236	1			T4	310		T5	39		T6	568
fifo_depth[13]	auto[0]	auto[0]	auto[1]	30371	1			T4	13		T5	74		T6	571
fifo_depth[13]	auto[0]	auto[1]	auto[0]	38244	1			T4	294		T5	83		T6	440
fifo_depth[13]	auto[0]	auto[1]	auto[1]	35129	1			T4	14		T5	7		T6	617
fifo_depth[13]	auto[1]	auto[0]	auto[0]	31474	1			T4	12		T10	1		T5	96
fifo_depth[13]	auto[1]	auto[0]	auto[1]	33568	1			T4	90		T5	41		T6	1044
fifo_depth[13]	auto[1]	auto[1]	auto[0]	33435	1			T1	1		T4	31		T5	27
fifo_depth[13]	auto[1]	auto[1]	auto[1]	31544	1			T4	133		T5	163		T6	531
fifo_depth[14]	auto[0]	auto[0]	auto[0]	47681	1			T4	258		T5	196		T6	763
fifo_depth[14]	auto[0]	auto[0]	auto[1]	50320	1			T4	12		T5	410		T6	814
fifo_depth[14]	auto[0]	auto[1]	auto[0]	54209	1			T4	304		T5	42		T6	629
fifo_depth[14]	auto[0]	auto[1]	auto[1]	55015	1			T4	102		T5	7		T6	964
fifo_depth[14]	auto[1]	auto[0]	auto[0]	54876	1			T4	182		T5	187		T6	551
fifo_depth[14]	auto[1]	auto[0]	auto[1]	55433	1			T4	122		T5	96		T6	1131
fifo_depth[14]	auto[1]	auto[1]	auto[0]	56441	1			T4	403		T5	22		T6	477
fifo_depth[14]	auto[1]	auto[1]	auto[1]	53038	1			T4	242		T5	782		T6	633
fifo_depth[15]	auto[0]	auto[0]	auto[0]	26653	1			T4	251		T5	26		T6	454
fifo_depth[15]	auto[0]	auto[0]	auto[1]	27714	1			T4	13		T5	47		T6	422
fifo_depth[15]	auto[0]	auto[1]	auto[0]	31951	1			T4	213		T5	24		T6	484
fifo_depth[15]	auto[0]	auto[1]	auto[1]	32183	1			T4	6		T5	3		T6	575
fifo_depth[15]	auto[1]	auto[0]	auto[0]	30753	1			T4	5		T5	81		T6	466
fifo_depth[15]	auto[1]	auto[0]	auto[1]	33193	1			T4	76		T5	110		T6	884
fifo_depth[15]	auto[1]	auto[1]	auto[0]	30495	1			T4	12		T5	36		T6	337
fifo_depth[15]	auto[1]	auto[1]	auto[1]	30116	1			T4	76		T5	505		T6	358
fifo_depth[16]	auto[0]	auto[0]	auto[0]	112161	1			T4	1493		T5	849		T6	1344
fifo_depth[16]	auto[0]	auto[0]	auto[1]	120729	1			T4	376		T5	334		T6	1539
fifo_depth[16]	auto[0]	auto[1]	auto[0]	118822	1			T4	213		T5	428		T6	912
fifo_depth[16]	auto[0]	auto[1]	auto[1]	115852	1			T4	86		T5	3		T6	2087
fifo_depth[16]	auto[1]	auto[0]	auto[0]	128208	1			T4	146		T5	2335		T6	1562
fifo_depth[16]	auto[1]	auto[0]	auto[1]	134806	1			T4	347		T5	543		T6	2184
fifo_depth[16]	auto[1]	auto[1]	auto[0]	116906	1			T4	337		T5	12		T6	3366
fifo_depth[16]	auto[1]	auto[1]	auto[1]	133813	1			T4	134		T5	537		T6	1325