Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	37603994	1			T13	11		T16	1		T18	11
all_pins[1]	37603994	1			T13	11		T16	1		T18	11
all_pins[2]	37603994	1			T13	11		T16	1		T18	11

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	81606218	1			T13	25		T16	3		T18	28
values[0x1]	31205764	1			T13	8		T18	5		T19	7
transitions[0x0=>0x1]	27515462	1			T13	6		T18	4		T19	3
transitions[0x1=>0x0]	27515483	1			T13	6		T18	4		T19	4

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	37439250	1			T13	7		T16	1		T18	11
all_pins[0]	values[0x1]	164744	1			T13	4		T19	1		T24	3
all_pins[0]	transitions[0x0=>0x1]	164513	1			T13	4		T24	3		T32	1
all_pins[0]	transitions[0x1=>0x0]	14097443	1			T13	2		T18	3		T19	3
all_pins[1]	values[0x0]	20660627	1			T13	9		T16	1		T18	9
all_pins[1]	values[0x1]	16943367	1			T13	2		T18	2		T19	3
all_pins[1]	transitions[0x0=>0x1]	16815047	1			T18	2		T19	3		T24	2
all_pins[1]	transitions[0x1=>0x0]	36424	1			T13	2		T19	1		T24	2
all_pins[2]	values[0x0]	23506341	1			T13	9		T16	1		T18	8
all_pins[2]	values[0x1]	14097653	1			T13	2		T18	3		T19	3
all_pins[2]	transitions[0x0=>0x1]	10535902	1			T13	2		T18	2		T32	4
all_pins[2]	transitions[0x1=>0x0]	13381616	1			T13	2		T18	1		T24	3