Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 4088 1 T13 10 T18 10 T19 4
all_values[1] 4088 1 T13 10 T18 10 T19 4
all_values[2] 4088 1 T13 10 T18 10 T19 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5808 1 T13 14 T18 16 T19 5
auto[1] 6456 1 T13 16 T18 14 T19 7


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4530 1 T13 6 T18 17 T19 2
auto[1] 7734 1 T13 24 T18 13 T19 10


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7001 1 T13 14 T18 19 T19 6
auto[1] 5263 1 T13 16 T18 11 T19 6


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 645 1 T13 1 T18 4 T19 1
all_values[0] auto[0] auto[0] auto[1] 417 1 T13 1 T69 1 T104 1
all_values[0] auto[0] auto[1] auto[0] 807 1 T18 6 T19 1 T24 4
all_values[0] auto[0] auto[1] auto[1] 429 1 T13 3 T19 1 T24 1
all_values[0] auto[1] auto[0] auto[1] 853 1 T13 1 T32 2 T69 1
all_values[0] auto[1] auto[1] auto[1] 937 1 T13 4 T19 1 T24 2
all_values[1] auto[0] auto[0] auto[0] 705 1 T13 1 T18 3 T32 5
all_values[1] auto[0] auto[0] auto[1] 422 1 T13 1 T86 1 T145 1
all_values[1] auto[0] auto[1] auto[0] 823 1 T13 1 T18 1 T24 1
all_values[1] auto[0] auto[1] auto[1] 407 1 T13 2 T18 1 T19 1
all_values[1] auto[1] auto[0] auto[1] 851 1 T13 3 T18 3 T19 2
all_values[1] auto[1] auto[1] auto[1] 880 1 T13 2 T18 2 T19 1
all_values[2] auto[0] auto[0] auto[0] 749 1 T13 1 T18 2 T32 1
all_values[2] auto[0] auto[0] auto[1] 371 1 T18 1 T19 1 T146 1
all_values[2] auto[0] auto[1] auto[0] 801 1 T13 2 T18 1 T24 1
all_values[2] auto[0] auto[1] auto[1] 425 1 T13 1 T19 1 T32 2
all_values[2] auto[1] auto[0] auto[1] 795 1 T13 5 T18 3 T19 1
all_values[2] auto[1] auto[1] auto[1] 947 1 T13 1 T18 3 T19 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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