Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.45 99.55 98.75 100.00 100.00 98.47 99.49 99.86


Total test records in report: 905
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T761 /workspace/coverage/default/19.hmac_test_hmac_vectors.1113364075 Feb 07 03:27:12 PM PST 24 Feb 07 03:27:14 PM PST 24 96767388 ps
T762 /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.4157409526 Feb 07 03:36:01 PM PST 24 Feb 07 03:38:35 PM PST 24 58383986517 ps
T763 /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1553564800 Feb 07 03:35:57 PM PST 24 Feb 07 04:24:26 PM PST 24 589881505714 ps
T764 /workspace/coverage/default/31.hmac_alert_test.3062713378 Feb 07 03:29:09 PM PST 24 Feb 07 03:29:11 PM PST 24 18279364 ps
T765 /workspace/coverage/default/30.hmac_stress_all.2075468266 Feb 07 03:28:53 PM PST 24 Feb 07 03:53:51 PM PST 24 117870429147 ps
T766 /workspace/coverage/default/20.hmac_wipe_secret.2821141806 Feb 07 03:27:21 PM PST 24 Feb 07 03:27:45 PM PST 24 3210570661 ps
T767 /workspace/coverage/default/25.hmac_error.101212910 Feb 07 03:28:10 PM PST 24 Feb 07 03:30:29 PM PST 24 11195980032 ps
T768 /workspace/coverage/default/33.hmac_wipe_secret.1750449274 Feb 07 03:29:30 PM PST 24 Feb 07 03:29:58 PM PST 24 2821970758 ps
T769 /workspace/coverage/default/38.hmac_smoke.3453482485 Feb 07 03:30:14 PM PST 24 Feb 07 03:30:15 PM PST 24 26937718 ps
T770 /workspace/coverage/default/20.hmac_test_hmac_vectors.3211791695 Feb 07 03:27:22 PM PST 24 Feb 07 03:27:26 PM PST 24 241640535 ps
T771 /workspace/coverage/default/35.hmac_long_msg.2491823836 Feb 07 03:29:41 PM PST 24 Feb 07 03:31:01 PM PST 24 9935973090 ps
T772 /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.2003545114 Feb 07 03:32:45 PM PST 24 Feb 07 04:33:04 PM PST 24 71376261340 ps
T773 /workspace/coverage/default/8.hmac_wipe_secret.1440432975 Feb 07 03:25:18 PM PST 24 Feb 07 03:25:35 PM PST 24 1162953935 ps
T774 /workspace/coverage/default/47.hmac_datapath_stress.807276903 Feb 07 03:31:56 PM PST 24 Feb 07 03:32:56 PM PST 24 3932295656 ps
T775 /workspace/coverage/default/3.hmac_alert_test.1336189511 Feb 07 03:24:36 PM PST 24 Feb 07 03:24:37 PM PST 24 14096014 ps
T776 /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.706852319 Feb 07 03:35:59 PM PST 24 Feb 07 03:40:43 PM PST 24 69871150193 ps
T777 /workspace/coverage/default/11.hmac_test_hmac_vectors.4166487077 Feb 07 03:25:43 PM PST 24 Feb 07 03:25:46 PM PST 24 84960130 ps
T778 /workspace/coverage/default/34.hmac_back_pressure.2746429796 Feb 07 03:29:29 PM PST 24 Feb 07 03:29:32 PM PST 24 57207146 ps
T779 /workspace/coverage/default/26.hmac_alert_test.3212857299 Feb 07 03:28:21 PM PST 24 Feb 07 03:28:22 PM PST 24 148477803 ps
T780 /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2695290407 Feb 07 03:24:48 PM PST 24 Feb 07 03:42:56 PM PST 24 25537024994 ps
T137 /workspace/coverage/default/31.hmac_error.205745594 Feb 07 03:29:03 PM PST 24 Feb 07 03:32:32 PM PST 24 34598251351 ps
T781 /workspace/coverage/default/6.hmac_error.780497683 Feb 07 03:24:42 PM PST 24 Feb 07 03:26:16 PM PST 24 22161370818 ps
T782 /workspace/coverage/default/44.hmac_smoke.4104287543 Feb 07 03:31:13 PM PST 24 Feb 07 03:31:14 PM PST 24 62982669 ps
T783 /workspace/coverage/default/24.hmac_test_hmac_vectors.3067254364 Feb 07 03:28:04 PM PST 24 Feb 07 03:28:06 PM PST 24 68162653 ps
T784 /workspace/coverage/default/7.hmac_long_msg.23433854 Feb 07 03:24:43 PM PST 24 Feb 07 03:24:55 PM PST 24 205690875 ps
T785 /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1368823898 Feb 07 03:35:53 PM PST 24 Feb 07 03:37:49 PM PST 24 15234567166 ps
T786 /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1749583459 Feb 07 03:26:49 PM PST 24 Feb 07 03:28:28 PM PST 24 6190421999 ps
T787 /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2644990640 Feb 07 03:35:59 PM PST 24 Feb 07 03:48:29 PM PST 24 71893360953 ps
T788 /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3173089725 Feb 07 03:31:32 PM PST 24 Feb 07 04:13:52 PM PST 24 988514797396 ps
T789 /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.302147318 Feb 07 03:25:16 PM PST 24 Feb 07 04:10:07 PM PST 24 560351007662 ps
T790 /workspace/coverage/default/17.hmac_error.1377502861 Feb 07 03:26:46 PM PST 24 Feb 07 03:29:04 PM PST 24 13496230809 ps
T791 /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.270041620 Feb 07 03:32:39 PM PST 24 Feb 07 03:55:42 PM PST 24 116396836518 ps
T792 /workspace/coverage/default/10.hmac_alert_test.3972997602 Feb 07 03:25:30 PM PST 24 Feb 07 03:25:31 PM PST 24 14347658 ps
T793 /workspace/coverage/default/28.hmac_long_msg.1626849481 Feb 07 03:28:41 PM PST 24 Feb 07 03:30:23 PM PST 24 21310850468 ps
T794 /workspace/coverage/default/43.hmac_back_pressure.3658181117 Feb 07 03:31:05 PM PST 24 Feb 07 03:32:06 PM PST 24 3177391649 ps
T795 /workspace/coverage/default/43.hmac_test_sha_vectors.3502069922 Feb 07 03:31:16 PM PST 24 Feb 07 03:38:55 PM PST 24 196501487262 ps
T796 /workspace/coverage/default/23.hmac_burst_wr.1394955761 Feb 07 03:27:51 PM PST 24 Feb 07 03:28:34 PM PST 24 8415617137 ps
T797 /workspace/coverage/default/47.hmac_error.2176939625 Feb 07 03:31:56 PM PST 24 Feb 07 03:33:29 PM PST 24 11365759441 ps
T798 /workspace/coverage/default/40.hmac_smoke.3403616145 Feb 07 03:30:29 PM PST 24 Feb 07 03:30:32 PM PST 24 848096179 ps
T799 /workspace/coverage/default/0.hmac_alert_test.3344339129 Feb 07 03:24:21 PM PST 24 Feb 07 03:24:23 PM PST 24 77076640 ps
T800 /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2625325576 Feb 07 03:30:53 PM PST 24 Feb 07 03:38:07 PM PST 24 30975943907 ps
T801 /workspace/coverage/default/30.hmac_error.3395190769 Feb 07 03:28:53 PM PST 24 Feb 07 03:30:23 PM PST 24 10752512257 ps
T802 /workspace/coverage/default/46.hmac_test_hmac_vectors.3414123468 Feb 07 03:31:43 PM PST 24 Feb 07 03:31:44 PM PST 24 242230331 ps
T803 /workspace/coverage/default/29.hmac_smoke.2790103879 Feb 07 03:28:48 PM PST 24 Feb 07 03:28:52 PM PST 24 341590703 ps
T804 /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3440464278 Feb 07 03:32:40 PM PST 24 Feb 07 03:47:38 PM PST 24 852521793979 ps
T805 /workspace/coverage/default/11.hmac_error.2133692259 Feb 07 03:25:39 PM PST 24 Feb 07 03:27:33 PM PST 24 6116938863 ps
T806 /workspace/coverage/default/1.hmac_stress_all.1608768606 Feb 07 03:24:32 PM PST 24 Feb 07 03:28:43 PM PST 24 10176891464 ps
T807 /workspace/coverage/default/34.hmac_datapath_stress.250939571 Feb 07 03:29:29 PM PST 24 Feb 07 03:30:08 PM PST 24 1533509224 ps
T808 /workspace/coverage/default/18.hmac_error.915789923 Feb 07 03:26:57 PM PST 24 Feb 07 03:27:41 PM PST 24 3484046222 ps
T809 /workspace/coverage/default/6.hmac_datapath_stress.124472953 Feb 07 03:24:46 PM PST 24 Feb 07 03:25:55 PM PST 24 1318024859 ps
T810 /workspace/coverage/default/49.hmac_test_hmac_vectors.765363487 Feb 07 03:32:21 PM PST 24 Feb 07 03:32:23 PM PST 24 113522175 ps
T121 /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.3600041845 Feb 07 03:31:39 PM PST 24 Feb 07 04:14:49 PM PST 24 67938268341 ps
T811 /workspace/coverage/default/47.hmac_wipe_secret.181997407 Feb 07 03:32:00 PM PST 24 Feb 07 03:32:08 PM PST 24 895250992 ps
T812 /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.2423007650 Feb 07 03:35:57 PM PST 24 Feb 07 03:42:30 PM PST 24 90798334744 ps
T813 /workspace/coverage/default/35.hmac_stress_all.4260635449 Feb 07 03:29:45 PM PST 24 Feb 07 03:36:16 PM PST 24 57276245428 ps
T814 /workspace/coverage/default/29.hmac_alert_test.2348345502 Feb 07 03:28:50 PM PST 24 Feb 07 03:28:51 PM PST 24 11987035 ps
T815 /workspace/coverage/default/35.hmac_wipe_secret.3524353991 Feb 07 03:29:37 PM PST 24 Feb 07 03:30:57 PM PST 24 2134513427 ps
T816 /workspace/coverage/default/28.hmac_burst_wr.528939884 Feb 07 03:28:43 PM PST 24 Feb 07 03:28:50 PM PST 24 2146234737 ps
T817 /workspace/coverage/default/7.hmac_stress_all.249910160 Feb 07 03:25:13 PM PST 24 Feb 07 03:55:29 PM PST 24 214171839211 ps
T818 /workspace/coverage/default/17.hmac_stress_all.3622884822 Feb 07 03:26:54 PM PST 24 Feb 07 03:38:05 PM PST 24 13312964323 ps
T819 /workspace/coverage/default/9.hmac_stress_all.2947143397 Feb 07 03:25:17 PM PST 24 Feb 07 03:27:51 PM PST 24 29470019412 ps
T820 /workspace/coverage/default/16.hmac_error.3260161984 Feb 07 03:26:33 PM PST 24 Feb 07 03:28:38 PM PST 24 14097461008 ps
T821 /workspace/coverage/default/12.hmac_datapath_stress.1388909250 Feb 07 03:25:52 PM PST 24 Feb 07 03:27:49 PM PST 24 14575993733 ps
T822 /workspace/coverage/default/14.hmac_test_hmac_vectors.4294860275 Feb 07 03:26:13 PM PST 24 Feb 07 03:26:16 PM PST 24 193659857 ps
T823 /workspace/coverage/default/39.hmac_long_msg.2420767219 Feb 07 03:30:17 PM PST 24 Feb 07 03:31:34 PM PST 24 17311815851 ps
T824 /workspace/coverage/default/42.hmac_long_msg.1778198648 Feb 07 03:30:57 PM PST 24 Feb 07 03:32:45 PM PST 24 23604914013 ps
T825 /workspace/coverage/default/40.hmac_back_pressure.2154554179 Feb 07 03:30:29 PM PST 24 Feb 07 03:31:02 PM PST 24 1977733081 ps
T826 /workspace/coverage/default/5.hmac_error.340883705 Feb 07 03:24:33 PM PST 24 Feb 07 03:25:20 PM PST 24 3477783716 ps
T827 /workspace/coverage/default/21.hmac_wipe_secret.1810188371 Feb 07 03:27:26 PM PST 24 Feb 07 03:28:18 PM PST 24 11446031379 ps
T828 /workspace/coverage/default/42.hmac_datapath_stress.321171742 Feb 07 03:30:58 PM PST 24 Feb 07 03:32:06 PM PST 24 4231616122 ps
T829 /workspace/coverage/default/21.hmac_stress_all.2583951121 Feb 07 03:27:33 PM PST 24 Feb 07 03:46:48 PM PST 24 66265438923 ps
T830 /workspace/coverage/default/23.hmac_test_sha_vectors.3196284120 Feb 07 03:27:54 PM PST 24 Feb 07 03:34:46 PM PST 24 7869990957 ps
T831 /workspace/coverage/default/4.hmac_datapath_stress.1662131194 Feb 07 03:24:26 PM PST 24 Feb 07 03:26:26 PM PST 24 4326065760 ps
T136 /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2296038255 Feb 07 03:33:24 PM PST 24 Feb 07 04:31:22 PM PST 24 443879938568 ps
T832 /workspace/coverage/default/1.hmac_wipe_secret.3524474459 Feb 07 03:24:27 PM PST 24 Feb 07 03:25:19 PM PST 24 14434022255 ps
T833 /workspace/coverage/default/9.hmac_test_sha_vectors.274116268 Feb 07 03:25:18 PM PST 24 Feb 07 03:33:12 PM PST 24 37306467890 ps
T834 /workspace/coverage/default/20.hmac_alert_test.301179193 Feb 07 03:27:21 PM PST 24 Feb 07 03:27:25 PM PST 24 24964597 ps
T835 /workspace/coverage/default/47.hmac_alert_test.2743858223 Feb 07 03:32:13 PM PST 24 Feb 07 03:32:14 PM PST 24 13201954 ps
T836 /workspace/coverage/default/49.hmac_back_pressure.1739982787 Feb 07 03:32:17 PM PST 24 Feb 07 03:33:08 PM PST 24 1617882883 ps
T837 /workspace/coverage/default/44.hmac_test_hmac_vectors.3821822200 Feb 07 03:31:33 PM PST 24 Feb 07 03:31:35 PM PST 24 33853250 ps
T838 /workspace/coverage/default/43.hmac_wipe_secret.4186879964 Feb 07 03:31:18 PM PST 24 Feb 07 03:31:36 PM PST 24 423716973 ps
T839 /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.1118259538 Feb 07 03:35:59 PM PST 24 Feb 07 04:13:25 PM PST 24 54946420616 ps
T840 /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.214627326 Feb 07 03:32:26 PM PST 24 Feb 07 03:37:27 PM PST 24 70889662788 ps
T841 /workspace/coverage/default/42.hmac_stress_all.1445223747 Feb 07 03:31:06 PM PST 24 Feb 07 03:43:02 PM PST 24 69646717838 ps
T842 /workspace/coverage/default/35.hmac_error.4054629171 Feb 07 03:29:37 PM PST 24 Feb 07 03:32:36 PM PST 24 11115549031 ps
T843 /workspace/coverage/default/8.hmac_long_msg.564571331 Feb 07 03:25:15 PM PST 24 Feb 07 03:25:49 PM PST 24 1761712670 ps
T844 /workspace/coverage/default/33.hmac_test_sha_vectors.1324364717 Feb 07 03:29:27 PM PST 24 Feb 07 03:37:17 PM PST 24 28303784416 ps
T845 /workspace/coverage/default/25.hmac_smoke.2028867562 Feb 07 03:28:03 PM PST 24 Feb 07 03:28:06 PM PST 24 534637272 ps
T846 /workspace/coverage/default/47.hmac_long_msg.2711189880 Feb 07 03:31:46 PM PST 24 Feb 07 03:32:50 PM PST 24 20569576055 ps
T847 /workspace/coverage/default/34.hmac_wipe_secret.463208160 Feb 07 03:29:34 PM PST 24 Feb 07 03:29:54 PM PST 24 6161775148 ps
T848 /workspace/coverage/default/13.hmac_test_hmac_vectors.3600455639 Feb 07 03:26:04 PM PST 24 Feb 07 03:26:06 PM PST 24 43250681 ps
T849 /workspace/coverage/default/22.hmac_datapath_stress.2593795884 Feb 07 03:27:43 PM PST 24 Feb 07 03:28:42 PM PST 24 2693323869 ps
T850 /workspace/coverage/default/39.hmac_alert_test.1366975607 Feb 07 03:30:31 PM PST 24 Feb 07 03:30:32 PM PST 24 36296268 ps
T851 /workspace/coverage/default/32.hmac_error.910775315 Feb 07 03:29:29 PM PST 24 Feb 07 03:31:59 PM PST 24 3369794684 ps
T852 /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.4035530367 Feb 07 03:26:04 PM PST 24 Feb 07 03:37:44 PM PST 24 90710392149 ps
T853 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3174006631 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:33 PM PST 24 39054832 ps
T854 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2173498598 Feb 07 01:45:59 PM PST 24 Feb 07 01:46:01 PM PST 24 20007048 ps
T855 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1434084007 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:15 PM PST 24 776668843 ps
T151 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.907894521 Feb 07 01:46:17 PM PST 24 Feb 07 01:46:19 PM PST 24 120419136 ps
T856 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3193348750 Feb 07 01:46:35 PM PST 24 Feb 07 01:46:37 PM PST 24 203628368 ps
T857 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1243012048 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:24 PM PST 24 50008289 ps
T858 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1837846454 Feb 07 01:46:17 PM PST 24 Feb 07 01:46:19 PM PST 24 18325113 ps
T859 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1240302933 Feb 07 01:46:23 PM PST 24 Feb 07 01:46:28 PM PST 24 41931505 ps
T860 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1219830727 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 27417772 ps
T861 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2620478492 Feb 07 01:46:25 PM PST 24 Feb 07 01:51:04 PM PST 24 22391330702 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3156508699 Feb 07 01:46:00 PM PST 24 Feb 07 01:46:08 PM PST 24 1832256377 ps
T862 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1322631466 Feb 07 01:46:28 PM PST 24 Feb 07 01:46:29 PM PST 24 54610979 ps
T863 /workspace/coverage/cover_reg_top/39.hmac_intr_test.647825152 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:33 PM PST 24 12248727 ps
T864 /workspace/coverage/cover_reg_top/19.hmac_intr_test.1139447441 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 43947789 ps
T865 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3142577577 Feb 07 01:46:37 PM PST 24 Feb 07 01:46:39 PM PST 24 58792172 ps
T866 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1459793280 Feb 07 01:46:17 PM PST 24 Feb 07 01:46:20 PM PST 24 98492393 ps
T867 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2928096512 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:11 PM PST 24 94080306 ps
T868 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3668842067 Feb 07 01:45:59 PM PST 24 Feb 07 01:46:02 PM PST 24 197075796 ps
T869 /workspace/coverage/cover_reg_top/27.hmac_intr_test.902529830 Feb 07 01:46:30 PM PST 24 Feb 07 01:46:31 PM PST 24 14367183 ps
T870 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3199145949 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:24 PM PST 24 11306763 ps
T871 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3394281412 Feb 07 01:46:37 PM PST 24 Feb 07 01:46:38 PM PST 24 16187799 ps
T872 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2606271626 Feb 07 01:46:18 PM PST 24 Feb 07 01:46:19 PM PST 24 37164240 ps
T873 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4166409840 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 25845070 ps
T874 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3863797409 Feb 07 01:46:29 PM PST 24 Feb 07 01:46:31 PM PST 24 27286178 ps
T91 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.482475516 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:11 PM PST 24 2202932252 ps
T875 /workspace/coverage/cover_reg_top/17.hmac_intr_test.569791823 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 45732915 ps
T876 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2726161156 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:20 PM PST 24 88544073 ps
T877 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1861437699 Feb 07 01:45:58 PM PST 24 Feb 07 01:46:01 PM PST 24 364623682 ps
T878 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2137048989 Feb 07 01:46:01 PM PST 24 Feb 07 01:46:05 PM PST 24 833445040 ps
T879 /workspace/coverage/cover_reg_top/12.hmac_intr_test.843131535 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 21396414 ps
T880 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2531158381 Feb 07 01:46:01 PM PST 24 Feb 07 01:46:03 PM PST 24 56204765 ps
T881 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3497245047 Feb 07 01:46:10 PM PST 24 Feb 07 01:46:14 PM PST 24 20072050 ps
T882 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.138305662 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:26 PM PST 24 22223888 ps
T883 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1096665000 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:24 PM PST 24 239956487 ps
T884 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.915963757 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:25 PM PST 24 145997433 ps
T92 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3800387512 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:11 PM PST 24 56537357 ps
T885 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2724767338 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:23 PM PST 24 13709454 ps
T93 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1058051319 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:25 PM PST 24 14699044 ps
T886 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.351953927 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:12 PM PST 24 54787663 ps
T887 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3480052152 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:33 PM PST 24 14123383 ps
T888 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.141583353 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:11 PM PST 24 34948926 ps
T889 /workspace/coverage/cover_reg_top/9.hmac_intr_test.1954891061 Feb 07 01:46:23 PM PST 24 Feb 07 01:46:26 PM PST 24 47985987 ps
T890 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1386658430 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:21 PM PST 24 210176503 ps
T891 /workspace/coverage/cover_reg_top/31.hmac_intr_test.989919075 Feb 07 01:46:35 PM PST 24 Feb 07 01:46:37 PM PST 24 23942849 ps
T892 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2679495005 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:26 PM PST 24 204974616 ps
T893 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1996334685 Feb 07 01:46:13 PM PST 24 Feb 07 01:46:15 PM PST 24 32976535 ps
T894 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2858123625 Feb 07 01:46:21 PM PST 24 Feb 07 01:46:23 PM PST 24 391218828 ps
T895 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3120196137 Feb 07 01:46:08 PM PST 24 Feb 07 01:46:10 PM PST 24 50582323 ps
T896 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2845374702 Feb 07 01:46:13 PM PST 24 Feb 07 01:46:16 PM PST 24 181933242 ps
T897 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.634242281 Feb 07 01:46:06 PM PST 24 Feb 07 01:46:11 PM PST 24 1013123459 ps
T898 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2512532272 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:11 PM PST 24 13340922 ps
T899 /workspace/coverage/cover_reg_top/38.hmac_intr_test.979151763 Feb 07 01:46:31 PM PST 24 Feb 07 01:46:33 PM PST 24 13533247 ps
T900 /workspace/coverage/cover_reg_top/46.hmac_intr_test.405895886 Feb 07 01:46:33 PM PST 24 Feb 07 01:46:35 PM PST 24 13723556 ps
T901 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1558789095 Feb 07 01:46:22 PM PST 24 Feb 07 01:46:24 PM PST 24 21952498 ps
T902 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4237457312 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:24 PM PST 24 192286304 ps
T68 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3737845639 Feb 07 01:46:07 PM PST 24 Feb 07 01:46:10 PM PST 24 65738712 ps
T94 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3011920913 Feb 07 01:46:09 PM PST 24 Feb 07 01:46:11 PM PST 24 19281739 ps
T903 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3559480215 Feb 07 01:46:19 PM PST 24 Feb 07 01:46:20 PM PST 24 13076106 ps
T904 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4158759748 Feb 07 01:46:20 PM PST 24 Feb 07 01:46:22 PM PST 24 25680296 ps
T905 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2426356021 Feb 07 01:46:29 PM PST 24 Feb 07 01:46:30 PM PST 24 37246540 ps

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.402304531
Short name T13
Test name
Test status
Simulation time 19951912 ps
CPU time 0.62 seconds
Started Feb 07 01:46:29 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 183988 kb
Host smart-029d395b-7ce9-4ff0-afa8-f30e227ff23b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402304531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.402304531
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/default/192.hmac_stress_all_with_rand_reset.1095652444
Short name T5
Test name
Test status
Simulation time 132361289514 ps
CPU time 1702.58 seconds
Started Feb 07 03:36:32 PM PST 24
Finished Feb 07 04:04:56 PM PST 24
Peak memory 247288 kb
Host smart-1566107a-0c03-4cb8-8b31-f13312e5d535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095652444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.hmac_stress_all_with_rand_reset.1095652444
Directory /workspace/192.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2862941255
Short name T22
Test name
Test status
Simulation time 256693514833 ps
CPU time 823.01 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 02:00:08 PM PST 24
Peak memory 210380 kb
Host smart-9c4b3a8e-6aca-4eeb-966c-8f91f256b9f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862941255 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2862941255
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1517591306
Short name T51
Test name
Test status
Simulation time 74688603 ps
CPU time 1.78 seconds
Started Feb 07 01:46:23 PM PST 24
Finished Feb 07 01:46:27 PM PST 24
Peak memory 198244 kb
Host smart-b551f206-5c7f-406d-95e6-71cd2653a31c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517591306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1517591306
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/63.hmac_stress_all_with_rand_reset.3276958131
Short name T6
Test name
Test status
Simulation time 142298682971 ps
CPU time 4679.77 seconds
Started Feb 07 03:32:34 PM PST 24
Finished Feb 07 04:50:36 PM PST 24
Peak memory 275936 kb
Host smart-4b4ae8b1-ed70-4fc0-a8dd-70fdd1fc7107
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276958131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.hmac_stress_all_with_rand_reset.3276958131
Directory /workspace/63.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3366726491
Short name T73
Test name
Test status
Simulation time 281431246 ps
CPU time 0.82 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:22 PM PST 24
Peak memory 192200 kb
Host smart-92bf196c-5000-4810-ab19-8922bbd48e3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366726491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3366726491
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.570931856
Short name T82
Test name
Test status
Simulation time 477189244 ps
CPU time 3.06 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 192400 kb
Host smart-707efb0b-cdd3-49d8-a12b-4639f72d2b6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570931856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.570931856
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3189768867
Short name T53
Test name
Test status
Simulation time 714715344 ps
CPU time 0.97 seconds
Started Feb 07 03:24:48 PM PST 24
Finished Feb 07 03:24:50 PM PST 24
Peak memory 217260 kb
Host smart-1ae14161-710e-4542-b051-a5a20330b79d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189768867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3189768867
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/120.hmac_stress_all_with_rand_reset.3688681946
Short name T308
Test name
Test status
Simulation time 421757917615 ps
CPU time 1921.31 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 04:07:56 PM PST 24
Peak memory 225104 kb
Host smart-959a4129-4806-424f-8723-0163de701b6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3688681946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.hmac_stress_all_with_rand_reset.3688681946
Directory /workspace/120.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_stress_all.386029267
Short name T12
Test name
Test status
Simulation time 7864294896 ps
CPU time 140.99 seconds
Started Feb 07 03:32:01 PM PST 24
Finished Feb 07 03:34:23 PM PST 24
Peak memory 199128 kb
Host smart-1aa47854-2e15-4391-9717-5e4269d8945c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386029267 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.386029267
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1388064635
Short name T18
Test name
Test status
Simulation time 35936319 ps
CPU time 0.61 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 183964 kb
Host smart-9fb4addd-8fe1-4b75-860f-18586359423a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388064635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1388064635
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2168945576
Short name T150
Test name
Test status
Simulation time 659275213 ps
CPU time 2.54 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 198552 kb
Host smart-fca00aaa-d96d-471c-b67e-61d209f9fcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168945576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2168945576
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.1651670986
Short name T127
Test name
Test status
Simulation time 101838105468 ps
CPU time 2442.24 seconds
Started Feb 07 03:36:00 PM PST 24
Finished Feb 07 04:16:43 PM PST 24
Peak memory 248320 kb
Host smart-1176ba6f-7608-4829-a114-83980aab3dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651670986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.1651670986
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3228513275
Short name T47
Test name
Test status
Simulation time 13552128 ps
CPU time 0.55 seconds
Started Feb 07 03:27:39 PM PST 24
Finished Feb 07 03:27:40 PM PST 24
Peak memory 193396 kb
Host smart-03b3b394-ef38-4bc3-ab51-d3cae152a935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228513275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3228513275
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/102.hmac_stress_all_with_rand_reset.2140183935
Short name T38
Test name
Test status
Simulation time 103015419788 ps
CPU time 1224.4 seconds
Started Feb 07 03:33:12 PM PST 24
Finished Feb 07 03:53:37 PM PST 24
Peak memory 243280 kb
Host smart-f0416b1b-dc42-4b16-874a-89aa8f38fd31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140183935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.hmac_stress_all_with_rand_reset.2140183935
Directory /workspace/102.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.2731561007
Short name T632
Test name
Test status
Simulation time 171199561110 ps
CPU time 1833.36 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 04:06:32 PM PST 24
Peak memory 224940 kb
Host smart-486f824d-cfe5-495f-823c-a6ae3464c2e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731561007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.2731561007
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.4018370545
Short name T326
Test name
Test status
Simulation time 2871315634 ps
CPU time 34.75 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 03:25:07 PM PST 24
Peak memory 198924 kb
Host smart-78c36d20-728e-4110-a4ad-faeaeb52c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018370545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.4018370545
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1696553463
Short name T148
Test name
Test status
Simulation time 178580829 ps
CPU time 1.18 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 198316 kb
Host smart-9ee4abd2-1362-4c16-b636-26748bcc5ac6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696553463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1696553463
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/115.hmac_stress_all_with_rand_reset.2296038255
Short name T136
Test name
Test status
Simulation time 443879938568 ps
CPU time 3476.75 seconds
Started Feb 07 03:33:24 PM PST 24
Finished Feb 07 04:31:22 PM PST 24
Peak memory 270560 kb
Host smart-5daee25d-e915-4b80-9cc8-aa1a980c222e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296038255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.hmac_stress_all_with_rand_reset.2296038255
Directory /workspace/115.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/117.hmac_stress_all_with_rand_reset.4242152273
Short name T111
Test name
Test status
Simulation time 141141086860 ps
CPU time 1325 seconds
Started Feb 07 03:35:52 PM PST 24
Finished Feb 07 03:57:58 PM PST 24
Peak memory 243268 kb
Host smart-76c0eb02-ae5e-4b65-aa1e-afb3728d7b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4242152273 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.hmac_stress_all_with_rand_reset.4242152273
Directory /workspace/117.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_stress_all_with_rand_reset.2369508930
Short name T138
Test name
Test status
Simulation time 303637658701 ps
CPU time 2818.28 seconds
Started Feb 07 03:25:57 PM PST 24
Finished Feb 07 04:12:59 PM PST 24
Peak memory 259936 kb
Host smart-af7161bc-99a8-4e7c-9abc-8d4a5ba1ef44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2369508930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all_with_rand_reset.2369508930
Directory /workspace/12.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.4035530367
Short name T852
Test name
Test status
Simulation time 90710392149 ps
CPU time 699.04 seconds
Started Feb 07 03:26:04 PM PST 24
Finished Feb 07 03:37:44 PM PST 24
Peak memory 231240 kb
Host smart-b3f42627-7935-424a-bc5f-ab7d0b68c893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4035530367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.4035530367
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.692555368
Short name T64
Test name
Test status
Simulation time 14402020207 ps
CPU time 36.23 seconds
Started Feb 07 03:26:27 PM PST 24
Finished Feb 07 03:27:04 PM PST 24
Peak memory 199144 kb
Host smart-61a9577b-cedc-46f4-be17-60d9d25f46bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692555368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.692555368
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.928453333
Short name T67
Test name
Test status
Simulation time 164995068 ps
CPU time 2.47 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 198560 kb
Host smart-95696e38-a15d-4b9a-93aa-7300f86588f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928453333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.928453333
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3737845639
Short name T68
Test name
Test status
Simulation time 65738712 ps
CPU time 1.21 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 198100 kb
Host smart-b5e2edc9-bee9-41a1-a47d-d34dba818d5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737845639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3737845639
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1647158150
Short name T183
Test name
Test status
Simulation time 260301669 ps
CPU time 1.25 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 184216 kb
Host smart-23152f3a-8928-4c6c-bf6e-aa25f7d0e994
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647158150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1647158150
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3156508699
Short name T90
Test name
Test status
Simulation time 1832256377 ps
CPU time 6.63 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:08 PM PST 24
Peak memory 192376 kb
Host smart-b14f3eef-5a04-4453-91ae-64fd3047836a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156508699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3156508699
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.2531158381
Short name T880
Test name
Test status
Simulation time 56204765 ps
CPU time 0.63 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:03 PM PST 24
Peak memory 193824 kb
Host smart-bd1fb45d-5276-4186-9264-924d389d1cd4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531158381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.2531158381
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2065326089
Short name T154
Test name
Test status
Simulation time 19105538 ps
CPU time 1.51 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 198848 kb
Host smart-85fe097d-28e7-46b3-b86f-b5c177d54706
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065326089 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2065326089
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3120196137
Short name T895
Test name
Test status
Simulation time 50582323 ps
CPU time 0.69 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 194716 kb
Host smart-56efc9c8-5820-4274-9b2e-28d1fb2c47cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120196137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3120196137
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1796251211
Short name T146
Test name
Test status
Simulation time 23275477 ps
CPU time 0.57 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 184012 kb
Host smart-07501ab5-10f8-43cf-b241-e0e582ebbe3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796251211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1796251211
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3540986920
Short name T77
Test name
Test status
Simulation time 54264968 ps
CPU time 1.02 seconds
Started Feb 07 01:46:02 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 197020 kb
Host smart-86f9de0b-47be-4bbf-8b38-d32f24ecab72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540986920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3540986920
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1861437699
Short name T877
Test name
Test status
Simulation time 364623682 ps
CPU time 2.07 seconds
Started Feb 07 01:45:58 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 198780 kb
Host smart-35089a26-cd17-40df-b64e-b649eb38432a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861437699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1861437699
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2905564127
Short name T155
Test name
Test status
Simulation time 54866418 ps
CPU time 1.21 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:04 PM PST 24
Peak memory 198008 kb
Host smart-dd741940-0aed-40d2-9393-209a25e395c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905564127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2905564127
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3668842067
Short name T868
Test name
Test status
Simulation time 197075796 ps
CPU time 1.79 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 184220 kb
Host smart-f72108a7-f3f5-43f7-bb4c-e964d88d57f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668842067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3668842067
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1037303630
Short name T156
Test name
Test status
Simulation time 144417355 ps
CPU time 3.28 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:04 PM PST 24
Peak memory 192432 kb
Host smart-704fbaab-941d-4cd9-9899-403e1510ee2b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037303630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1037303630
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.140748442
Short name T197
Test name
Test status
Simulation time 56565636 ps
CPU time 0.66 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 194140 kb
Host smart-5bc8ab81-2559-42d8-951a-6c71466fae16
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140748442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.140748442
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2173498598
Short name T854
Test name
Test status
Simulation time 20007048 ps
CPU time 1.05 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:46:01 PM PST 24
Peak memory 198612 kb
Host smart-c640839d-3d9a-41f9-bcbc-4713b7a3f8f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173498598 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2173498598
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.3271597809
Short name T80
Test name
Test status
Simulation time 56037274 ps
CPU time 0.72 seconds
Started Feb 07 01:46:03 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 194272 kb
Host smart-d9cd70b7-8fec-44a7-8dc6-74576db0bbc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271597809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.3271597809
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2826322684
Short name T88
Test name
Test status
Simulation time 26056188 ps
CPU time 1.05 seconds
Started Feb 07 01:46:04 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 197232 kb
Host smart-e336b9e1-946d-4629-9380-8e0068f9dddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826322684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2826322684
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.2137048989
Short name T878
Test name
Test status
Simulation time 833445040 ps
CPU time 1.73 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:05 PM PST 24
Peak memory 198844 kb
Host smart-56c158c0-4da8-4c73-9149-aefe9c5ba1a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137048989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.2137048989
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1788499628
Short name T52
Test name
Test status
Simulation time 142535257 ps
CPU time 1.74 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:03 PM PST 24
Peak memory 198292 kb
Host smart-22d1e373-64cd-4b63-ae03-c24fa97e3a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788499628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1788499628
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.112741435
Short name T31
Test name
Test status
Simulation time 30336687 ps
CPU time 0.98 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 198704 kb
Host smart-daa09cef-e891-4238-b11e-0565b2955329
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112741435 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.112741435
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2865726447
Short name T78
Test name
Test status
Simulation time 20789182 ps
CPU time 0.73 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 194480 kb
Host smart-e9f1bcd6-b705-4e3d-96c9-1346aec8580b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865726447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2865726447
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4034795978
Short name T182
Test name
Test status
Simulation time 32165940 ps
CPU time 0.59 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 183932 kb
Host smart-b208c595-2cbb-4eca-87ad-b25e7e877dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034795978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4034795978
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1588577144
Short name T170
Test name
Test status
Simulation time 70156881 ps
CPU time 1.4 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 192460 kb
Host smart-ad5ff378-f9ee-4511-a69d-06b6e5bbc0cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588577144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1588577144
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.707924913
Short name T179
Test name
Test status
Simulation time 109030679 ps
CPU time 2.16 seconds
Started Feb 07 01:46:17 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 198884 kb
Host smart-f2aae193-3174-4ad8-9b6c-a1c2a62e8ee6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707924913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.707924913
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3166627511
Short name T178
Test name
Test status
Simulation time 126759218 ps
CPU time 1.29 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 198316 kb
Host smart-248d3015-5614-48d4-9a52-27eaaa6a45b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166627511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3166627511
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.4189628135
Short name T72
Test name
Test status
Simulation time 41675381 ps
CPU time 0.63 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 193964 kb
Host smart-8334a9ff-7c31-4de7-a052-b24a68dc0b96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189628135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.4189628135
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2647352362
Short name T145
Test name
Test status
Simulation time 23366571 ps
CPU time 0.6 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:22 PM PST 24
Peak memory 183952 kb
Host smart-620f1148-6672-4ba2-b6cf-ac8bf7ee901f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647352362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2647352362
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3090336286
Short name T172
Test name
Test status
Simulation time 19656713 ps
CPU time 0.79 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 195516 kb
Host smart-346356a3-148b-4cc6-84bd-6a95f7e24dd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090336286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3090336286
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1075700763
Short name T173
Test name
Test status
Simulation time 148263599 ps
CPU time 2.45 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 198680 kb
Host smart-43cf2096-0a06-4d73-8db3-b37c113eb075
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075700763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1075700763
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.907894521
Short name T151
Test name
Test status
Simulation time 120419136 ps
CPU time 1.21 seconds
Started Feb 07 01:46:17 PM PST 24
Finished Feb 07 01:46:19 PM PST 24
Peak memory 198824 kb
Host smart-ec9b9511-5503-4521-b23d-d9ed71686765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907894521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.907894521
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1243012048
Short name T857
Test name
Test status
Simulation time 50008289 ps
CPU time 2.04 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198904 kb
Host smart-d720f893-8a22-476a-b275-2a5985b44720
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243012048 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1243012048
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.3559480215
Short name T903
Test name
Test status
Simulation time 13076106 ps
CPU time 0.68 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 194788 kb
Host smart-1147697d-99ed-4011-ad22-50f024b1f477
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559480215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.3559480215
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.843131535
Short name T879
Test name
Test status
Simulation time 21396414 ps
CPU time 0.6 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 183960 kb
Host smart-caab57ec-2da6-4125-bc4e-b84a49f8f77b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843131535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.843131535
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1459793280
Short name T866
Test name
Test status
Simulation time 98492393 ps
CPU time 1.45 seconds
Started Feb 07 01:46:17 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 192520 kb
Host smart-567d22cd-f46b-4c25-976a-6b0ef0cc93c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459793280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1459793280
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3174006631
Short name T853
Test name
Test status
Simulation time 39054832 ps
CPU time 1.95 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 198844 kb
Host smart-a314ab83-ffb5-4d7c-b342-af1b0577ba68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174006631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3174006631
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2679495005
Short name T892
Test name
Test status
Simulation time 204974616 ps
CPU time 1.79 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:26 PM PST 24
Peak memory 198468 kb
Host smart-97c46bcd-19d3-484f-ae54-6b3ca43084d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679495005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2679495005
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2964722582
Short name T184
Test name
Test status
Simulation time 50402555 ps
CPU time 1.33 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 198868 kb
Host smart-7aae960f-08e0-4a28-936f-13dfff8a123d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964722582 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2964722582
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.4166409840
Short name T873
Test name
Test status
Simulation time 25845070 ps
CPU time 0.72 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 194524 kb
Host smart-e2eb4a56-17fa-4167-b477-78e438c4a88e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166409840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.4166409840
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1975740360
Short name T201
Test name
Test status
Simulation time 49471945 ps
CPU time 0.59 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:19 PM PST 24
Peak memory 183952 kb
Host smart-ab490656-e2df-48de-b3d6-92e5c987a9e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975740360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1975740360
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1096665000
Short name T883
Test name
Test status
Simulation time 239956487 ps
CPU time 1.27 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 192440 kb
Host smart-93d70cc6-1407-4b67-93e1-0eb161d823ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096665000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1096665000
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2338781024
Short name T26
Test name
Test status
Simulation time 292350961 ps
CPU time 3.26 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 198852 kb
Host smart-7dbfa159-725a-4044-adf9-acff23f563eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338781024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2338781024
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1386658430
Short name T890
Test name
Test status
Simulation time 210176503 ps
CPU time 1.85 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 198500 kb
Host smart-16274eb0-7a40-4d28-acee-d9bf528f7576
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386658430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1386658430
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2858123625
Short name T894
Test name
Test status
Simulation time 391218828 ps
CPU time 1.14 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 198644 kb
Host smart-c8dc674f-2b68-4ad6-ba72-142c0894c9fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858123625 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2858123625
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2839669533
Short name T165
Test name
Test status
Simulation time 31754417 ps
CPU time 0.62 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 194044 kb
Host smart-fe23120f-0cef-4fe9-835e-727c69611adb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839669533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2839669533
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2606271626
Short name T872
Test name
Test status
Simulation time 37164240 ps
CPU time 0.58 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:19 PM PST 24
Peak memory 183936 kb
Host smart-fa52a943-1eb4-4ca3-afa5-4498a0cac3e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606271626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2606271626
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2825805338
Short name T79
Test name
Test status
Simulation time 249341666 ps
CPU time 1.21 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 192484 kb
Host smart-0b8689a4-af4a-4153-81d5-7413d45ccdeb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825805338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2825805338
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.3338891606
Short name T25
Test name
Test status
Simulation time 48909991 ps
CPU time 1.36 seconds
Started Feb 07 01:46:27 PM PST 24
Finished Feb 07 01:46:29 PM PST 24
Peak memory 198920 kb
Host smart-6c79cbc7-31bb-464b-8043-db1cd0dfed6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338891606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.3338891606
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.636781487
Short name T66
Test name
Test status
Simulation time 116894294 ps
CPU time 1.89 seconds
Started Feb 07 01:46:18 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 198336 kb
Host smart-ba75782e-39d2-456a-b8a1-a09a3feb5bf3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636781487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.636781487
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1652399096
Short name T28
Test name
Test status
Simulation time 71840646 ps
CPU time 1.72 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198888 kb
Host smart-8fc46a61-0177-480a-9cd5-2b34f8acb1ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652399096 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1652399096
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.925574552
Short name T21
Test name
Test status
Simulation time 64273199 ps
CPU time 0.68 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:22 PM PST 24
Peak memory 194632 kb
Host smart-40a74657-2ddb-49be-94eb-75e92bdef3d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925574552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.925574552
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.292412413
Short name T161
Test name
Test status
Simulation time 17729430 ps
CPU time 0.6 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 183960 kb
Host smart-5443aafe-1290-4d65-88de-917f810ae7d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292412413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.292412413
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2726161156
Short name T876
Test name
Test status
Simulation time 88544073 ps
CPU time 0.79 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:20 PM PST 24
Peak memory 195884 kb
Host smart-7b38fc57-8172-4dfa-ade6-2e40586d983b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726161156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2726161156
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3855877619
Short name T27
Test name
Test status
Simulation time 58537378 ps
CPU time 3.25 seconds
Started Feb 07 01:46:17 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 198884 kb
Host smart-e43a2c52-f3ab-47e0-a392-12e6c56a5249
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855877619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3855877619
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.1558789095
Short name T901
Test name
Test status
Simulation time 21952498 ps
CPU time 0.82 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198660 kb
Host smart-b53d0b80-503b-4e4e-98de-9ada7878a956
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558789095 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.1558789095
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1964916582
Short name T83
Test name
Test status
Simulation time 80465955 ps
CPU time 0.71 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 194964 kb
Host smart-ea2889dc-afb0-42b6-afb8-61acf192d235
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964916582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1964916582
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3199145949
Short name T870
Test name
Test status
Simulation time 11306763 ps
CPU time 0.58 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 183940 kb
Host smart-df418b43-0ec8-4783-b33b-ac91440d6df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199145949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3199145949
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.1837846454
Short name T858
Test name
Test status
Simulation time 18325113 ps
CPU time 0.84 seconds
Started Feb 07 01:46:17 PM PST 24
Finished Feb 07 01:46:19 PM PST 24
Peak memory 192256 kb
Host smart-321b2b89-086f-45a2-b0c0-3e3a13c62d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837846454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.1837846454
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1240302933
Short name T859
Test name
Test status
Simulation time 41931505 ps
CPU time 2.13 seconds
Started Feb 07 01:46:23 PM PST 24
Finished Feb 07 01:46:28 PM PST 24
Peak memory 198768 kb
Host smart-869e9d31-e8f6-44f7-bcc5-603edc5e371e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240302933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1240302933
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.4237457312
Short name T902
Test name
Test status
Simulation time 192286304 ps
CPU time 2.34 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198576 kb
Host smart-f3a28317-6f36-432e-bc25-c0e3e253ab6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237457312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.4237457312
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2620478492
Short name T861
Test name
Test status
Simulation time 22391330702 ps
CPU time 277.86 seconds
Started Feb 07 01:46:25 PM PST 24
Finished Feb 07 01:51:04 PM PST 24
Peak memory 198864 kb
Host smart-f919d018-3ef8-4331-820e-03f927294d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620478492 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2620478492
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1732402536
Short name T199
Test name
Test status
Simulation time 89509781 ps
CPU time 0.65 seconds
Started Feb 07 01:46:26 PM PST 24
Finished Feb 07 01:46:28 PM PST 24
Peak memory 194800 kb
Host smart-e6ebc01f-8ebb-45c3-93ce-cfa0b0b18a41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732402536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1732402536
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.569791823
Short name T875
Test name
Test status
Simulation time 45732915 ps
CPU time 0.56 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 183972 kb
Host smart-b21d4bb3-2b37-4e90-bc6c-f7b1ef0b9dc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569791823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.569791823
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.947434375
Short name T103
Test name
Test status
Simulation time 81704850 ps
CPU time 1.35 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 192456 kb
Host smart-9310adc9-c719-43e1-917a-52f46f3a7beb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947434375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.947434375
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.3880024777
Short name T190
Test name
Test status
Simulation time 82259610 ps
CPU time 2.24 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198696 kb
Host smart-4a04b5f8-b86b-4e8b-af1e-9a9c7247f441
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880024777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.3880024777
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.786223604
Short name T198
Test name
Test status
Simulation time 21316238 ps
CPU time 1.51 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198804 kb
Host smart-b1e1ee39-edb2-4a19-8233-e820e4a02a9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786223604 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.786223604
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2841416496
Short name T169
Test name
Test status
Simulation time 23926933 ps
CPU time 0.65 seconds
Started Feb 07 01:46:25 PM PST 24
Finished Feb 07 01:46:27 PM PST 24
Peak memory 194580 kb
Host smart-e7ca8af9-dce1-4021-b98f-ebe35b4ae5a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841416496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2841416496
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2249579197
Short name T104
Test name
Test status
Simulation time 41189113 ps
CPU time 0.56 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 183896 kb
Host smart-2ff1b8c6-da4f-4ff9-a134-44c7c1087600
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249579197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2249579197
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1802614033
Short name T192
Test name
Test status
Simulation time 599874038 ps
CPU time 3.23 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:27 PM PST 24
Peak memory 198912 kb
Host smart-1dbef968-6979-4ff0-ae4e-77626dac565b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802614033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1802614033
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1499962457
Short name T147
Test name
Test status
Simulation time 678320901 ps
CPU time 2.46 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:27 PM PST 24
Peak memory 198440 kb
Host smart-7176278a-e967-43e1-97d8-07dbe2f21c0d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499962457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1499962457
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3863797409
Short name T874
Test name
Test status
Simulation time 27286178 ps
CPU time 1.42 seconds
Started Feb 07 01:46:29 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 198856 kb
Host smart-e8a257d7-dbdc-4006-afaa-f74ecc647643
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863797409 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3863797409
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1058051319
Short name T93
Test name
Test status
Simulation time 14699044 ps
CPU time 0.61 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 194384 kb
Host smart-dc8ac346-6803-4af8-8796-caba076a0875
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058051319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1058051319
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.1139447441
Short name T864
Test name
Test status
Simulation time 43947789 ps
CPU time 0.59 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 183948 kb
Host smart-0b5a6a12-4556-48bd-ad7b-3c7d12ed9dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139447441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.1139447441
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.432168305
Short name T186
Test name
Test status
Simulation time 157938258 ps
CPU time 1.29 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:26 PM PST 24
Peak memory 196916 kb
Host smart-308008da-623e-4e0f-b566-705864b47000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432168305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.432168305
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.371363185
Short name T29
Test name
Test status
Simulation time 277548232 ps
CPU time 3.35 seconds
Started Feb 07 01:46:23 PM PST 24
Finished Feb 07 01:46:29 PM PST 24
Peak memory 198608 kb
Host smart-a39761e6-3c77-4235-8898-17647cb99324
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371363185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.371363185
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2338317431
Short name T176
Test name
Test status
Simulation time 69489461 ps
CPU time 1.15 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:32 PM PST 24
Peak memory 198012 kb
Host smart-98a88d38-fd3c-49c6-a907-80425b5a4d54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338317431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2338317431
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.2356267928
Short name T84
Test name
Test status
Simulation time 106991409 ps
CPU time 2 seconds
Started Feb 07 01:46:06 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 195964 kb
Host smart-3f3eb0d8-3934-4531-9503-6b3061f4799a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356267928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.2356267928
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.634242281
Short name T897
Test name
Test status
Simulation time 1013123459 ps
CPU time 3.49 seconds
Started Feb 07 01:46:06 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 184208 kb
Host smart-8f56bb34-4f78-429e-8f6b-14a6ce865324
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634242281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.634242281
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2904151397
Short name T85
Test name
Test status
Simulation time 87616474 ps
CPU time 0.73 seconds
Started Feb 07 01:46:00 PM PST 24
Finished Feb 07 01:46:02 PM PST 24
Peak memory 194132 kb
Host smart-0dca11b5-6da9-4229-82d0-17a98ba8f7ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904151397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2904151397
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3902814349
Short name T158
Test name
Test status
Simulation time 24218792 ps
CPU time 1.51 seconds
Started Feb 07 01:46:06 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 198860 kb
Host smart-5080f15c-ccb7-4b2d-bb13-158c222207a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902814349 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3902814349
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.107855421
Short name T185
Test name
Test status
Simulation time 20735083 ps
CPU time 0.75 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 194832 kb
Host smart-f78b7aa8-f6ee-47f9-a9cf-21664386a4f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107855421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.107855421
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4174053026
Short name T171
Test name
Test status
Simulation time 22465643 ps
CPU time 0.56 seconds
Started Feb 07 01:45:59 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 183944 kb
Host smart-60558f33-bd30-4eb2-a4cf-168d40d9f031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174053026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4174053026
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2130847001
Short name T89
Test name
Test status
Simulation time 29832572 ps
CPU time 1.28 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 197016 kb
Host smart-d86f8d04-e49f-4c07-82af-5ff7919f0f0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130847001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2130847001
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1603500796
Short name T23
Test name
Test status
Simulation time 494008820 ps
CPU time 2.76 seconds
Started Feb 07 01:45:57 PM PST 24
Finished Feb 07 01:46:00 PM PST 24
Peak memory 198824 kb
Host smart-4cc0f187-c4e8-4842-86b8-489079b392f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603500796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1603500796
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.170529183
Short name T191
Test name
Test status
Simulation time 78425381 ps
CPU time 1.82 seconds
Started Feb 07 01:46:01 PM PST 24
Finished Feb 07 01:46:06 PM PST 24
Peak memory 198520 kb
Host smart-456f88c4-c3e6-4d25-b223-cea030bf9773
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170529183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.170529183
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2724767338
Short name T885
Test name
Test status
Simulation time 13709454 ps
CPU time 0.58 seconds
Started Feb 07 01:46:21 PM PST 24
Finished Feb 07 01:46:23 PM PST 24
Peak memory 183900 kb
Host smart-e0c547bd-2a98-4afd-9b41-563e3a144b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724767338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2724767338
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3142577577
Short name T865
Test name
Test status
Simulation time 58792172 ps
CPU time 0.58 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 183684 kb
Host smart-6383c0f3-a306-4505-a9ae-add3e15034da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142577577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3142577577
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3193348750
Short name T856
Test name
Test status
Simulation time 203628368 ps
CPU time 0.6 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 183916 kb
Host smart-1ea9fd05-5743-48d3-80d0-8ceaf0770be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193348750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3193348750
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2213605705
Short name T180
Test name
Test status
Simulation time 18796327 ps
CPU time 0.61 seconds
Started Feb 07 01:46:32 PM PST 24
Finished Feb 07 01:46:34 PM PST 24
Peak memory 183960 kb
Host smart-1fff3278-bde3-4d78-b5c7-1745753d35c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213605705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2213605705
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2426356021
Short name T905
Test name
Test status
Simulation time 37246540 ps
CPU time 0.63 seconds
Started Feb 07 01:46:29 PM PST 24
Finished Feb 07 01:46:30 PM PST 24
Peak memory 183948 kb
Host smart-27cb9208-b6ea-435f-a52f-e86ff02e11ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426356021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2426356021
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1874165286
Short name T194
Test name
Test status
Simulation time 42854153 ps
CPU time 0.6 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 183988 kb
Host smart-72534a68-4ab7-4ac5-a515-e58bce4b2767
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874165286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1874165286
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3429181935
Short name T187
Test name
Test status
Simulation time 21621661 ps
CPU time 0.56 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 183916 kb
Host smart-4f04626a-9192-4fc6-b6b9-d0809c2de87f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429181935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3429181935
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.902529830
Short name T869
Test name
Test status
Simulation time 14367183 ps
CPU time 0.63 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 184016 kb
Host smart-22fe733b-2aed-4dd1-8147-bb71d8a6b016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902529830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.902529830
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.2270375406
Short name T160
Test name
Test status
Simulation time 69488808 ps
CPU time 0.61 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:39 PM PST 24
Peak memory 183384 kb
Host smart-be2f0870-3f88-400b-a685-04ca64008992
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270375406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.2270375406
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2897626228
Short name T168
Test name
Test status
Simulation time 36089191 ps
CPU time 0.54 seconds
Started Feb 07 01:46:32 PM PST 24
Finished Feb 07 01:46:34 PM PST 24
Peak memory 183924 kb
Host smart-fc710cc5-e0c9-495f-ba07-4d5b4800847e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897626228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2897626228
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.482475516
Short name T91
Test name
Test status
Simulation time 2202932252 ps
CPU time 1.99 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 192484 kb
Host smart-d55050ef-8310-4344-a712-f2d9480ce747
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482475516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.482475516
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3011920913
Short name T94
Test name
Test status
Simulation time 19281739 ps
CPU time 0.72 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 194424 kb
Host smart-c5603f95-49c7-4938-b8a1-a1476f87d7af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011920913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3011920913
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.411554187
Short name T153
Test name
Test status
Simulation time 25194807 ps
CPU time 2.22 seconds
Started Feb 07 01:46:11 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 198892 kb
Host smart-ad31fdbb-f069-43cc-bf14-9fdc4ae1ab56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411554187 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.411554187
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3574439837
Short name T20
Test name
Test status
Simulation time 22899158 ps
CPU time 0.59 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 194028 kb
Host smart-af2f5e2a-6b7c-421f-97df-2444cc6980a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574439837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3574439837
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2111907662
Short name T166
Test name
Test status
Simulation time 39204762 ps
CPU time 0.56 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 183928 kb
Host smart-0603afbb-3dae-4936-8c14-70df425a778f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111907662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2111907662
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1219830727
Short name T860
Test name
Test status
Simulation time 27417772 ps
CPU time 1.21 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 197040 kb
Host smart-88875b43-5234-4393-ae4a-5fc456ad219e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219830727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1219830727
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1881357558
Short name T16
Test name
Test status
Simulation time 327910901 ps
CPU time 1.82 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 198884 kb
Host smart-7fc3536d-628e-4efd-840c-ee57045c20e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881357558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1881357558
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2244226210
Short name T74
Test name
Test status
Simulation time 97246975 ps
CPU time 1.71 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 198420 kb
Host smart-84819d32-0ff1-4bd7-82b2-52006a8f77b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244226210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2244226210
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.989919075
Short name T891
Test name
Test status
Simulation time 23942849 ps
CPU time 0.56 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:37 PM PST 24
Peak memory 183936 kb
Host smart-285e7f3f-6684-4d42-9742-2332258d1ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989919075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.989919075
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1108865815
Short name T32
Test name
Test status
Simulation time 11822472 ps
CPU time 0.63 seconds
Started Feb 07 01:46:28 PM PST 24
Finished Feb 07 01:46:30 PM PST 24
Peak memory 183988 kb
Host smart-69b8c2ef-752b-4b29-9d90-eedef13e63e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108865815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1108865815
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1322631466
Short name T862
Test name
Test status
Simulation time 54610979 ps
CPU time 0.57 seconds
Started Feb 07 01:46:28 PM PST 24
Finished Feb 07 01:46:29 PM PST 24
Peak memory 183956 kb
Host smart-ac9377f8-fde3-43f7-964b-12b3824abe8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322631466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1322631466
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.483384611
Short name T86
Test name
Test status
Simulation time 12845499 ps
CPU time 0.59 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:32 PM PST 24
Peak memory 183968 kb
Host smart-9bb2e805-4ebd-47ba-bd12-4f818d2ee078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483384611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.483384611
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2967166921
Short name T174
Test name
Test status
Simulation time 16340241 ps
CPU time 0.58 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 183924 kb
Host smart-f16ea1bb-42dd-4a42-b16e-ae3a84d162f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967166921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2967166921
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.45988266
Short name T177
Test name
Test status
Simulation time 19214989 ps
CPU time 0.64 seconds
Started Feb 07 01:46:33 PM PST 24
Finished Feb 07 01:46:35 PM PST 24
Peak memory 183952 kb
Host smart-7ad713ed-e2e6-4dc1-b5dc-87d3092f3a7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45988266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.45988266
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.674680640
Short name T157
Test name
Test status
Simulation time 31192301 ps
CPU time 0.62 seconds
Started Feb 07 01:46:32 PM PST 24
Finished Feb 07 01:46:34 PM PST 24
Peak memory 183960 kb
Host smart-69630375-ca7d-4cf0-b095-e3dbc31a567e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674680640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.674680640
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.979151763
Short name T899
Test name
Test status
Simulation time 13533247 ps
CPU time 0.6 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 183880 kb
Host smart-53be1d45-0b35-473f-a0fa-47d539f2fce2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979151763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.979151763
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.647825152
Short name T863
Test name
Test status
Simulation time 12248727 ps
CPU time 0.64 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 183940 kb
Host smart-cdf94011-3fb4-4368-88a1-5f1c39958cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647825152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.647825152
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2947204540
Short name T81
Test name
Test status
Simulation time 63682605 ps
CPU time 1.26 seconds
Started Feb 07 01:46:13 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 184140 kb
Host smart-b804f59f-863b-4273-ab5e-a15114a51052
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947204540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2947204540
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2237312777
Short name T17
Test name
Test status
Simulation time 927800239 ps
CPU time 3.47 seconds
Started Feb 07 01:46:13 PM PST 24
Finished Feb 07 01:46:17 PM PST 24
Peak memory 192428 kb
Host smart-9e105a78-6cb0-4d88-81dc-a4a55abb5352
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237312777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2237312777
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1705779060
Short name T76
Test name
Test status
Simulation time 41996810 ps
CPU time 0.61 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 193736 kb
Host smart-4d0d9e2d-b440-432b-900c-34728fea5e3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705779060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1705779060
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.652078262
Short name T152
Test name
Test status
Simulation time 43375318 ps
CPU time 1.25 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:14 PM PST 24
Peak memory 198864 kb
Host smart-c44dd840-a7ff-4ef8-a0f7-84906a488820
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652078262 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.652078262
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.292883597
Short name T15
Test name
Test status
Simulation time 42867864 ps
CPU time 0.62 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 194412 kb
Host smart-93fdb416-a088-4cbf-a45c-084c9f02c584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292883597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.292883597
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3836459849
Short name T69
Test name
Test status
Simulation time 37446044 ps
CPU time 0.54 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 184000 kb
Host smart-e8331c6b-88cc-4daa-8ab1-8901af4889ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836459849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3836459849
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2518847785
Short name T164
Test name
Test status
Simulation time 31141194 ps
CPU time 0.88 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:09 PM PST 24
Peak memory 195744 kb
Host smart-5a6f1720-9cff-418f-b43e-6d939b82005f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518847785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2518847785
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2419728391
Short name T167
Test name
Test status
Simulation time 600094132 ps
CPU time 1.56 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 198864 kb
Host smart-a97f510c-7951-46a3-b382-538f83294796
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419728391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2419728391
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2845374702
Short name T896
Test name
Test status
Simulation time 181933242 ps
CPU time 2.49 seconds
Started Feb 07 01:46:13 PM PST 24
Finished Feb 07 01:46:16 PM PST 24
Peak memory 198588 kb
Host smart-ca0b55bd-c40d-4ff3-b9c9-28a2ba3ec8c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845374702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2845374702
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2842936789
Short name T175
Test name
Test status
Simulation time 42880600 ps
CPU time 0.55 seconds
Started Feb 07 01:46:28 PM PST 24
Finished Feb 07 01:46:30 PM PST 24
Peak memory 183940 kb
Host smart-4381bf8c-8b08-48dd-a236-5648388fe86f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842936789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2842936789
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.981008829
Short name T19
Test name
Test status
Simulation time 21381824 ps
CPU time 0.59 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 183940 kb
Host smart-301e5186-1f77-4ae4-976c-d5b09b0468ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981008829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.981008829
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3480052152
Short name T887
Test name
Test status
Simulation time 14123383 ps
CPU time 0.62 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 183936 kb
Host smart-b2197712-de97-475b-8683-4f9909d2f78c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480052152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3480052152
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.44314867
Short name T163
Test name
Test status
Simulation time 47861525 ps
CPU time 0.61 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 183936 kb
Host smart-58984d5b-3bf8-4244-b611-1d36299ed6bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44314867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.44314867
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.518013114
Short name T189
Test name
Test status
Simulation time 18019587 ps
CPU time 0.6 seconds
Started Feb 07 01:46:35 PM PST 24
Finished Feb 07 01:46:36 PM PST 24
Peak memory 183916 kb
Host smart-b83cf644-f495-441e-874f-d728191a8ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518013114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.518013114
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3066378516
Short name T181
Test name
Test status
Simulation time 11663849 ps
CPU time 0.59 seconds
Started Feb 07 01:46:31 PM PST 24
Finished Feb 07 01:46:33 PM PST 24
Peak memory 183948 kb
Host smart-e1e515c6-a9c0-4a30-a13b-a4bce14599d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066378516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3066378516
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.405895886
Short name T900
Test name
Test status
Simulation time 13723556 ps
CPU time 0.6 seconds
Started Feb 07 01:46:33 PM PST 24
Finished Feb 07 01:46:35 PM PST 24
Peak memory 183952 kb
Host smart-9df34035-9819-42e1-a878-b94b56fccd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405895886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.405895886
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3394281412
Short name T871
Test name
Test status
Simulation time 16187799 ps
CPU time 0.57 seconds
Started Feb 07 01:46:37 PM PST 24
Finished Feb 07 01:46:38 PM PST 24
Peak memory 183656 kb
Host smart-3ec1d84f-d3da-4abf-bde6-ae20ff20ec3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394281412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3394281412
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.561209012
Short name T202
Test name
Test status
Simulation time 14546126 ps
CPU time 0.7 seconds
Started Feb 07 01:46:29 PM PST 24
Finished Feb 07 01:46:30 PM PST 24
Peak memory 183952 kb
Host smart-10996e4e-0039-43a2-9501-4f705fe68c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561209012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.561209012
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2159758974
Short name T70
Test name
Test status
Simulation time 13386473 ps
CPU time 0.57 seconds
Started Feb 07 01:46:30 PM PST 24
Finished Feb 07 01:46:31 PM PST 24
Peak memory 183984 kb
Host smart-72f20d51-be7c-4cbd-a6a7-f89a6776b2fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159758974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2159758974
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3497245047
Short name T881
Test name
Test status
Simulation time 20072050 ps
CPU time 1.57 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:14 PM PST 24
Peak memory 198860 kb
Host smart-a99e60b9-cb2c-4360-aa69-37aef5be74bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497245047 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3497245047
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1414973445
Short name T14
Test name
Test status
Simulation time 19995025 ps
CPU time 0.68 seconds
Started Feb 07 01:46:12 PM PST 24
Finished Feb 07 01:46:14 PM PST 24
Peak memory 194728 kb
Host smart-7643a8e2-808d-462a-894a-3a2eb65c24b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414973445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1414973445
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.900906055
Short name T71
Test name
Test status
Simulation time 15621747 ps
CPU time 0.56 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:13 PM PST 24
Peak memory 183928 kb
Host smart-dfb7b1a9-5cd7-461f-8c44-cc86545f6530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900906055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.900906055
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2928096512
Short name T867
Test name
Test status
Simulation time 94080306 ps
CPU time 1.04 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 196368 kb
Host smart-cc405274-7851-44ab-b45d-8906903e0852
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928096512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2928096512
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1996334685
Short name T893
Test name
Test status
Simulation time 32976535 ps
CPU time 1.16 seconds
Started Feb 07 01:46:13 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 198804 kb
Host smart-04a7a4b3-ba62-440a-a672-e6caea8a931c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996334685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1996334685
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.4133334421
Short name T196
Test name
Test status
Simulation time 168688068 ps
CPU time 1.16 seconds
Started Feb 07 01:46:13 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 198140 kb
Host smart-5bb5691e-a88f-4fae-aeb7-db76a53eadaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133334421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.4133334421
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.448102940
Short name T162
Test name
Test status
Simulation time 24271666 ps
CPU time 1.68 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 198868 kb
Host smart-c24d12c6-3e59-493b-b7f3-a7b79d9fbe8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448102940 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.448102940
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3800387512
Short name T92
Test name
Test status
Simulation time 56537357 ps
CPU time 0.68 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 194716 kb
Host smart-c57bb44a-1c10-4594-b7d4-b9b8beda09aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800387512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3800387512
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2298614673
Short name T24
Test name
Test status
Simulation time 14238666 ps
CPU time 0.62 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 183988 kb
Host smart-e166f9e1-94e3-4311-9a15-a3ea05b47cc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298614673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2298614673
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1158127596
Short name T195
Test name
Test status
Simulation time 398429172 ps
CPU time 1.1 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 192468 kb
Host smart-6cbcc2e3-3ef0-4948-bf78-ae0005b1e68d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158127596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1158127596
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3044035927
Short name T75
Test name
Test status
Simulation time 488370831 ps
CPU time 2.52 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 198832 kb
Host smart-2142d6db-503f-4e7a-86ee-e9730fcc8058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044035927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3044035927
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4244377121
Short name T159
Test name
Test status
Simulation time 18873483 ps
CPU time 1.22 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 198572 kb
Host smart-e9c5a0d0-a41a-4d30-a3c8-13e409914f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244377121 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4244377121
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2512532272
Short name T898
Test name
Test status
Simulation time 13340922 ps
CPU time 0.6 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 194148 kb
Host smart-0699cd73-cd13-4fbf-b4bd-4c1ba702e6ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512532272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2512532272
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.3189631960
Short name T188
Test name
Test status
Simulation time 41794127 ps
CPU time 0.58 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 183928 kb
Host smart-4215bc2e-c07a-4fad-9ab0-0016d6041a33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189631960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.3189631960
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.351953927
Short name T886
Test name
Test status
Simulation time 54787663 ps
CPU time 1.05 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:12 PM PST 24
Peak memory 192444 kb
Host smart-474b1246-5ca6-4729-8f5a-3d6980e32366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351953927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.351953927
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1434084007
Short name T855
Test name
Test status
Simulation time 776668843 ps
CPU time 2.55 seconds
Started Feb 07 01:46:10 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 198848 kb
Host smart-6604ca30-3e76-49f1-bfea-469a691a3f53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434084007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1434084007
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.878203440
Short name T149
Test name
Test status
Simulation time 641850754 ps
CPU time 2.55 seconds
Started Feb 07 01:46:07 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 198636 kb
Host smart-bfb2ebb5-15bf-403a-a423-b93705356015
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878203440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.878203440
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.915963757
Short name T884
Test name
Test status
Simulation time 145997433 ps
CPU time 2.87 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 198852 kb
Host smart-97d43be0-43e5-454f-b41e-93ccaf53a526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915963757 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.915963757
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.141583353
Short name T888
Test name
Test status
Simulation time 34948926 ps
CPU time 0.61 seconds
Started Feb 07 01:46:09 PM PST 24
Finished Feb 07 01:46:11 PM PST 24
Peak memory 193932 kb
Host smart-af2e2cd1-8dc2-4011-9ac3-6249c85a814f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141583353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.141583353
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2017121595
Short name T200
Test name
Test status
Simulation time 14127155 ps
CPU time 0.58 seconds
Started Feb 07 01:46:08 PM PST 24
Finished Feb 07 01:46:10 PM PST 24
Peak memory 183980 kb
Host smart-1be73fad-1dce-47c3-a25b-2454d3288b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017121595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2017121595
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3012242237
Short name T102
Test name
Test status
Simulation time 321119481 ps
CPU time 0.81 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:25 PM PST 24
Peak memory 192248 kb
Host smart-9e1ad4a9-f070-477c-a3f0-423bfb90e339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012242237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3012242237
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1659426712
Short name T193
Test name
Test status
Simulation time 115133624 ps
CPU time 2.52 seconds
Started Feb 07 01:46:11 PM PST 24
Finished Feb 07 01:46:15 PM PST 24
Peak memory 198936 kb
Host smart-f954f12b-12c4-4294-9339-c57505169abc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659426712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1659426712
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.138305662
Short name T882
Test name
Test status
Simulation time 22223888 ps
CPU time 1.02 seconds
Started Feb 07 01:46:22 PM PST 24
Finished Feb 07 01:46:26 PM PST 24
Peak memory 198672 kb
Host smart-5a956d5f-0df1-46ae-932a-0610025402ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138305662 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.138305662
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4158759748
Short name T904
Test name
Test status
Simulation time 25680296 ps
CPU time 0.76 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:22 PM PST 24
Peak memory 195184 kb
Host smart-3a22767b-823a-4eea-8b87-c26113253b6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158759748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4158759748
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.1954891061
Short name T889
Test name
Test status
Simulation time 47985987 ps
CPU time 0.58 seconds
Started Feb 07 01:46:23 PM PST 24
Finished Feb 07 01:46:26 PM PST 24
Peak memory 183728 kb
Host smart-07c54e53-f859-417f-93ff-8cbf2790568e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954891061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.1954891061
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4019892511
Short name T87
Test name
Test status
Simulation time 32464814 ps
CPU time 0.8 seconds
Started Feb 07 01:46:19 PM PST 24
Finished Feb 07 01:46:21 PM PST 24
Peak memory 192324 kb
Host smart-16265c36-035b-44d9-90e8-fda6d26d4b23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019892511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4019892511
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3040970572
Short name T30
Test name
Test status
Simulation time 101253657 ps
CPU time 2.43 seconds
Started Feb 07 01:46:20 PM PST 24
Finished Feb 07 01:46:24 PM PST 24
Peak memory 198852 kb
Host smart-a6ef2365-4c23-4df9-839f-f90596f96f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040970572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3040970572
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3344339129
Short name T799
Test name
Test status
Simulation time 77076640 ps
CPU time 0.59 seconds
Started Feb 07 03:24:21 PM PST 24
Finished Feb 07 03:24:23 PM PST 24
Peak memory 194468 kb
Host smart-b2fb6cd6-94c0-436e-b4b3-436e14fae2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344339129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3344339129
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.638925302
Short name T378
Test name
Test status
Simulation time 8487215771 ps
CPU time 39.13 seconds
Started Feb 07 03:21:41 PM PST 24
Finished Feb 07 03:22:20 PM PST 24
Peak memory 215460 kb
Host smart-a0661375-c2ed-418e-bf14-4623f49884f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638925302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.638925302
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.4079237619
Short name T618
Test name
Test status
Simulation time 3706940632 ps
CPU time 16.69 seconds
Started Feb 07 03:21:43 PM PST 24
Finished Feb 07 03:22:00 PM PST 24
Peak memory 199112 kb
Host smart-f23fd526-c670-461b-acaa-7e3015655bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079237619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.4079237619
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2413947386
Short name T760
Test name
Test status
Simulation time 7212089455 ps
CPU time 88.93 seconds
Started Feb 07 03:21:42 PM PST 24
Finished Feb 07 03:23:11 PM PST 24
Peak memory 199076 kb
Host smart-86185c2b-a277-49a2-85c3-27e68bd4085f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413947386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2413947386
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3879432064
Short name T427
Test name
Test status
Simulation time 1347118822 ps
CPU time 11.43 seconds
Started Feb 07 03:21:43 PM PST 24
Finished Feb 07 03:21:55 PM PST 24
Peak memory 199032 kb
Host smart-2498974c-a13c-4af5-a74e-b83fbe4230ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879432064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3879432064
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1055285021
Short name T443
Test name
Test status
Simulation time 3440066474 ps
CPU time 31.06 seconds
Started Feb 07 03:21:36 PM PST 24
Finished Feb 07 03:22:08 PM PST 24
Peak memory 199144 kb
Host smart-ed271013-23f5-4dcd-ac9c-187d80c632e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055285021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1055285021
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.889780899
Short name T56
Test name
Test status
Simulation time 58512129 ps
CPU time 0.88 seconds
Started Feb 07 03:24:23 PM PST 24
Finished Feb 07 03:24:25 PM PST 24
Peak memory 216104 kb
Host smart-259c09f1-1789-4dd6-bbd6-198a4b5d52b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889780899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.889780899
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1666900881
Short name T630
Test name
Test status
Simulation time 260403811 ps
CPU time 2.51 seconds
Started Feb 07 03:21:37 PM PST 24
Finished Feb 07 03:21:40 PM PST 24
Peak memory 198776 kb
Host smart-754df878-e8b0-45be-af8c-cdfb00e77fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666900881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1666900881
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.867586578
Short name T115
Test name
Test status
Simulation time 113504137541 ps
CPU time 932.03 seconds
Started Feb 07 03:24:21 PM PST 24
Finished Feb 07 03:39:55 PM PST 24
Peak memory 215492 kb
Host smart-449cd945-f0cb-4bb9-8303-0ad2b82bcbcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867586578 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.867586578
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_stress_all_with_rand_reset.630413729
Short name T294
Test name
Test status
Simulation time 88101146184 ps
CPU time 1279.98 seconds
Started Feb 07 03:24:22 PM PST 24
Finished Feb 07 03:45:44 PM PST 24
Peak memory 231980 kb
Host smart-794ab62e-fa27-42a4-9db5-765b1ca6f250
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=630413729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all_with_rand_reset.630413729
Directory /workspace/0.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1142886047
Short name T316
Test name
Test status
Simulation time 132282708 ps
CPU time 0.93 seconds
Started Feb 07 03:21:41 PM PST 24
Finished Feb 07 03:21:42 PM PST 24
Peak memory 196204 kb
Host smart-24709aab-0892-4365-9d4a-bec9d5d1d5d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142886047 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1142886047
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2956655361
Short name T563
Test name
Test status
Simulation time 2157423203 ps
CPU time 7.8 seconds
Started Feb 07 03:21:43 PM PST 24
Finished Feb 07 03:21:51 PM PST 24
Peak memory 199128 kb
Host smart-88b84eef-d6da-4da1-b303-ee3245153901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956655361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2956655361
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2515781074
Short name T275
Test name
Test status
Simulation time 14684574 ps
CPU time 0.58 seconds
Started Feb 07 03:24:42 PM PST 24
Finished Feb 07 03:24:43 PM PST 24
Peak memory 193456 kb
Host smart-8901581d-021a-44a0-9c5c-a23b41605973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515781074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2515781074
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4024619596
Short name T487
Test name
Test status
Simulation time 878004255 ps
CPU time 28.78 seconds
Started Feb 07 03:24:20 PM PST 24
Finished Feb 07 03:24:50 PM PST 24
Peak memory 207176 kb
Host smart-249ffeb9-beb8-4147-b751-c5b1c8dad7e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4024619596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4024619596
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1420944579
Short name T590
Test name
Test status
Simulation time 32179149318 ps
CPU time 49.71 seconds
Started Feb 07 03:24:22 PM PST 24
Finished Feb 07 03:25:13 PM PST 24
Peak memory 199108 kb
Host smart-a48e0dc6-00ba-4ff3-80c2-e25a46bd81bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420944579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1420944579
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1957492146
Short name T553
Test name
Test status
Simulation time 144890767 ps
CPU time 7.9 seconds
Started Feb 07 03:24:41 PM PST 24
Finished Feb 07 03:24:50 PM PST 24
Peak memory 199092 kb
Host smart-ba897691-4bd5-47da-8bd4-b731c2cdef99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957492146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1957492146
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4199647635
Short name T322
Test name
Test status
Simulation time 2127391476 ps
CPU time 8.45 seconds
Started Feb 07 03:24:22 PM PST 24
Finished Feb 07 03:24:32 PM PST 24
Peak memory 198760 kb
Host smart-d0415acd-da46-41fb-b5d4-ddf7d18692de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199647635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4199647635
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2299954131
Short name T694
Test name
Test status
Simulation time 2785886114 ps
CPU time 8.27 seconds
Started Feb 07 03:24:21 PM PST 24
Finished Feb 07 03:24:31 PM PST 24
Peak memory 199068 kb
Host smart-97b20f24-351d-4946-b614-913993a9d08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299954131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2299954131
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.898079019
Short name T57
Test name
Test status
Simulation time 60959719 ps
CPU time 0.88 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:24:34 PM PST 24
Peak memory 216188 kb
Host smart-8e4d692c-9da3-4c76-901d-0f837d2f4774
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898079019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.898079019
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1424174797
Short name T594
Test name
Test status
Simulation time 1139268762 ps
CPU time 3.18 seconds
Started Feb 07 03:24:21 PM PST 24
Finished Feb 07 03:24:26 PM PST 24
Peak memory 199004 kb
Host smart-70c491af-0f13-4114-b2de-021000ba8729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424174797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1424174797
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.1608768606
Short name T806
Test name
Test status
Simulation time 10176891464 ps
CPU time 250.09 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:28:43 PM PST 24
Peak memory 199136 kb
Host smart-3a20da56-637c-4b37-9e13-4dffc9f8e3a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608768606 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.1608768606
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.153953201
Short name T710
Test name
Test status
Simulation time 352517433661 ps
CPU time 343.92 seconds
Started Feb 07 03:24:23 PM PST 24
Finished Feb 07 03:30:08 PM PST 24
Peak memory 211024 kb
Host smart-7ec93cab-8140-431d-be52-2dced6cb31d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153953201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.153953201
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.548900303
Short name T529
Test name
Test status
Simulation time 30776790 ps
CPU time 1.09 seconds
Started Feb 07 03:24:22 PM PST 24
Finished Feb 07 03:24:25 PM PST 24
Peak memory 197508 kb
Host smart-e268db8c-5e96-458c-b2ca-1275ac7c7931
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548900303 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.548900303
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2359046280
Short name T463
Test name
Test status
Simulation time 66146077877 ps
CPU time 427.14 seconds
Started Feb 07 03:24:25 PM PST 24
Finished Feb 07 03:31:33 PM PST 24
Peak memory 199064 kb
Host smart-d66206f6-2d7b-4f69-a1ac-68d58d8d063e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359046280 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.2359046280
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3524474459
Short name T832
Test name
Test status
Simulation time 14434022255 ps
CPU time 51.74 seconds
Started Feb 07 03:24:27 PM PST 24
Finished Feb 07 03:25:19 PM PST 24
Peak memory 199092 kb
Host smart-1c536c94-1d90-41bc-9b72-59b87a4fac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524474459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3524474459
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3972997602
Short name T792
Test name
Test status
Simulation time 14347658 ps
CPU time 0.54 seconds
Started Feb 07 03:25:30 PM PST 24
Finished Feb 07 03:25:31 PM PST 24
Peak memory 193472 kb
Host smart-1ae52ed4-7a68-4077-a259-8b14078f0261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972997602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3972997602
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3516206884
Short name T696
Test name
Test status
Simulation time 576801880 ps
CPU time 19.45 seconds
Started Feb 07 03:25:27 PM PST 24
Finished Feb 07 03:25:46 PM PST 24
Peak memory 217368 kb
Host smart-8097add7-694f-47e1-9477-49aca5f52af5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3516206884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3516206884
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1204728332
Short name T229
Test name
Test status
Simulation time 12323192104 ps
CPU time 40.96 seconds
Started Feb 07 03:25:31 PM PST 24
Finished Feb 07 03:26:13 PM PST 24
Peak memory 199048 kb
Host smart-137f7713-7a50-421d-af28-c0683c337784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204728332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1204728332
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2076330579
Short name T473
Test name
Test status
Simulation time 2353241778 ps
CPU time 107.25 seconds
Started Feb 07 03:25:23 PM PST 24
Finished Feb 07 03:27:10 PM PST 24
Peak memory 198904 kb
Host smart-7e4b076b-6270-4bcb-af99-82361fb455bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2076330579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2076330579
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.3102616453
Short name T531
Test name
Test status
Simulation time 11365293713 ps
CPU time 35.21 seconds
Started Feb 07 03:25:37 PM PST 24
Finished Feb 07 03:26:15 PM PST 24
Peak memory 199140 kb
Host smart-084ca14f-2c42-4d9b-8566-265d1c98828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102616453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.3102616453
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.315490330
Short name T603
Test name
Test status
Simulation time 405772759 ps
CPU time 10.52 seconds
Started Feb 07 03:25:25 PM PST 24
Finished Feb 07 03:25:36 PM PST 24
Peak memory 198976 kb
Host smart-36ef9c93-3866-442f-8f16-bb17d7135993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315490330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.315490330
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.2291614090
Short name T704
Test name
Test status
Simulation time 176482375 ps
CPU time 2.26 seconds
Started Feb 07 03:25:24 PM PST 24
Finished Feb 07 03:25:27 PM PST 24
Peak memory 198940 kb
Host smart-fcc58205-ebf4-4b25-8f55-3047360c3575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291614090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.2291614090
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.520552095
Short name T391
Test name
Test status
Simulation time 232625109251 ps
CPU time 714.6 seconds
Started Feb 07 03:25:38 PM PST 24
Finished Feb 07 03:37:35 PM PST 24
Peak memory 240068 kb
Host smart-01f501e1-7f35-4467-a116-e5aa98786732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520552095 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.520552095
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_stress_all_with_rand_reset.2466917103
Short name T437
Test name
Test status
Simulation time 152736509173 ps
CPU time 1629.36 seconds
Started Feb 07 03:25:29 PM PST 24
Finished Feb 07 03:52:39 PM PST 24
Peak memory 261596 kb
Host smart-64514784-abf4-4faa-a590-474b48fe054c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2466917103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all_with_rand_reset.2466917103
Directory /workspace/10.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2881703940
Short name T459
Test name
Test status
Simulation time 69685688 ps
CPU time 1.23 seconds
Started Feb 07 03:25:36 PM PST 24
Finished Feb 07 03:25:41 PM PST 24
Peak memory 197156 kb
Host smart-82cf2477-d718-4dbe-828c-c812ea8844f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881703940 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2881703940
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.2436578237
Short name T593
Test name
Test status
Simulation time 103116165244 ps
CPU time 425.02 seconds
Started Feb 07 03:25:34 PM PST 24
Finished Feb 07 03:32:45 PM PST 24
Peak memory 199016 kb
Host smart-c160d273-30cf-406b-93e5-1a0ec5f3535c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436578237 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.2436578237
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1980702220
Short name T225
Test name
Test status
Simulation time 1228465358 ps
CPU time 15.88 seconds
Started Feb 07 03:25:36 PM PST 24
Finished Feb 07 03:25:56 PM PST 24
Peak memory 199036 kb
Host smart-24855326-ffb3-46b6-9070-5b70bc4afc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980702220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1980702220
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/100.hmac_stress_all_with_rand_reset.2574648952
Short name T699
Test name
Test status
Simulation time 137244274377 ps
CPU time 1825.62 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 04:03:31 PM PST 24
Peak memory 257600 kb
Host smart-2c84e058-e289-4f90-a184-a9a11415da1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574648952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.hmac_stress_all_with_rand_reset.2574648952
Directory /workspace/100.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.4056727318
Short name T430
Test name
Test status
Simulation time 54475140852 ps
CPU time 391.85 seconds
Started Feb 07 03:33:08 PM PST 24
Finished Feb 07 03:39:40 PM PST 24
Peak memory 223768 kb
Host smart-f97d99ee-dbb0-40fb-812d-5e813f25213f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4056727318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.4056727318
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.288885326
Short name T494
Test name
Test status
Simulation time 151511014311 ps
CPU time 732.44 seconds
Started Feb 07 03:33:15 PM PST 24
Finished Feb 07 03:45:28 PM PST 24
Peak memory 230104 kb
Host smart-cd636806-50f9-48a4-916e-441df69501af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=288885326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.288885326
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/105.hmac_stress_all_with_rand_reset.2554311812
Short name T248
Test name
Test status
Simulation time 4485194552 ps
CPU time 88.92 seconds
Started Feb 07 03:33:16 PM PST 24
Finished Feb 07 03:34:46 PM PST 24
Peak memory 199216 kb
Host smart-f4a224eb-359f-4b22-8d30-2a3dfea58840
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2554311812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.hmac_stress_all_with_rand_reset.2554311812
Directory /workspace/105.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/106.hmac_stress_all_with_rand_reset.230648951
Short name T564
Test name
Test status
Simulation time 470314333514 ps
CPU time 2178.83 seconds
Started Feb 07 03:33:16 PM PST 24
Finished Feb 07 04:09:35 PM PST 24
Peak memory 248400 kb
Host smart-ac7152bc-548c-46e2-97c3-3d3b7d573463
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230648951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.hmac_stress_all_with_rand_reset.230648951
Directory /workspace/106.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/107.hmac_stress_all_with_rand_reset.3869788060
Short name T230
Test name
Test status
Simulation time 109192235645 ps
CPU time 348.74 seconds
Started Feb 07 03:33:19 PM PST 24
Finished Feb 07 03:39:08 PM PST 24
Peak memory 215600 kb
Host smart-dabffbbe-f8aa-43e0-992a-4b1c8e79cbf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869788060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.hmac_stress_all_with_rand_reset.3869788060
Directory /workspace/107.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.3700182026
Short name T416
Test name
Test status
Simulation time 108953366405 ps
CPU time 1580.79 seconds
Started Feb 07 03:33:16 PM PST 24
Finished Feb 07 03:59:37 PM PST 24
Peak memory 234072 kb
Host smart-e48cc1e0-848d-4b72-b0b9-ac88b553fe1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700182026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.3700182026
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/109.hmac_stress_all_with_rand_reset.461432643
Short name T744
Test name
Test status
Simulation time 91684196570 ps
CPU time 632.7 seconds
Started Feb 07 03:33:16 PM PST 24
Finished Feb 07 03:43:49 PM PST 24
Peak memory 231960 kb
Host smart-9bfb4bc9-4d17-42ae-9a79-efc3c03efec4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461432643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.hmac_stress_all_with_rand_reset.461432643
Directory /workspace/109.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1945467856
Short name T49
Test name
Test status
Simulation time 42554270 ps
CPU time 0.56 seconds
Started Feb 07 03:25:56 PM PST 24
Finished Feb 07 03:25:58 PM PST 24
Peak memory 193488 kb
Host smart-cb054781-ab03-430e-807f-f8f64438dafc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945467856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1945467856
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.695220844
Short name T318
Test name
Test status
Simulation time 2081346111 ps
CPU time 16.01 seconds
Started Feb 07 03:25:43 PM PST 24
Finished Feb 07 03:26:01 PM PST 24
Peak memory 207224 kb
Host smart-6d5117ab-f4a1-48db-891f-9f860e3197b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=695220844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.695220844
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1174582961
Short name T278
Test name
Test status
Simulation time 5891455751 ps
CPU time 24.39 seconds
Started Feb 07 03:25:41 PM PST 24
Finished Feb 07 03:26:06 PM PST 24
Peak memory 199124 kb
Host smart-9ec6b5fc-d2c3-4282-b766-7fe09b085ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174582961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1174582961
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2987595326
Short name T116
Test name
Test status
Simulation time 4709993075 ps
CPU time 127.22 seconds
Started Feb 07 03:25:41 PM PST 24
Finished Feb 07 03:27:51 PM PST 24
Peak memory 199072 kb
Host smart-4e916971-3d02-4e3f-877a-343bdb4066d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2987595326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2987595326
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2133692259
Short name T805
Test name
Test status
Simulation time 6116938863 ps
CPU time 113.19 seconds
Started Feb 07 03:25:39 PM PST 24
Finished Feb 07 03:27:33 PM PST 24
Peak memory 199088 kb
Host smart-f0c57067-3f7d-44fc-8510-f3d791324931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133692259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2133692259
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1448422033
Short name T725
Test name
Test status
Simulation time 5901922713 ps
CPU time 27.72 seconds
Started Feb 07 03:25:28 PM PST 24
Finished Feb 07 03:25:56 PM PST 24
Peak memory 199068 kb
Host smart-b57a2486-4b1e-48b7-b316-a30aeed57652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448422033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1448422033
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3998600613
Short name T449
Test name
Test status
Simulation time 18442522 ps
CPU time 0.67 seconds
Started Feb 07 03:25:37 PM PST 24
Finished Feb 07 03:25:41 PM PST 24
Peak memory 194228 kb
Host smart-298e314d-1527-4eaf-b160-e129c570ac88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998600613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3998600613
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3565944275
Short name T214
Test name
Test status
Simulation time 272010304743 ps
CPU time 1764.67 seconds
Started Feb 07 03:25:52 PM PST 24
Finished Feb 07 03:55:17 PM PST 24
Peak memory 234200 kb
Host smart-aaa8eb27-8c11-43db-89a1-a9dacece283c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565944275 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3565944275
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_stress_all_with_rand_reset.930418210
Short name T734
Test name
Test status
Simulation time 101038765313 ps
CPU time 387.94 seconds
Started Feb 07 03:25:49 PM PST 24
Finished Feb 07 03:32:18 PM PST 24
Peak memory 231956 kb
Host smart-db2c76af-7bb0-4a7d-885e-9e6fb4aaa93f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930418210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all_with_rand_reset.930418210
Directory /workspace/11.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.4166487077
Short name T777
Test name
Test status
Simulation time 84960130 ps
CPU time 0.9 seconds
Started Feb 07 03:25:43 PM PST 24
Finished Feb 07 03:25:46 PM PST 24
Peak memory 195816 kb
Host smart-9c3ca8c4-8e73-4d03-ac42-61c97b0d6780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166487077 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.4166487077
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.3182948686
Short name T61
Test name
Test status
Simulation time 37841726838 ps
CPU time 476.43 seconds
Started Feb 07 03:25:54 PM PST 24
Finished Feb 07 03:33:50 PM PST 24
Peak memory 199104 kb
Host smart-d1aa93f9-e205-414e-afc3-44b442801cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182948686 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.3182948686
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.1128453636
Short name T289
Test name
Test status
Simulation time 3236824624 ps
CPU time 46.36 seconds
Started Feb 07 03:25:56 PM PST 24
Finished Feb 07 03:26:43 PM PST 24
Peak memory 199124 kb
Host smart-1f49bd01-61aa-40fe-be4a-1fd4c08a085a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128453636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.1128453636
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/111.hmac_stress_all_with_rand_reset.1039390692
Short name T130
Test name
Test status
Simulation time 207627342914 ps
CPU time 954.18 seconds
Started Feb 07 03:33:24 PM PST 24
Finished Feb 07 03:49:19 PM PST 24
Peak memory 239924 kb
Host smart-e5dee270-630f-485a-aa35-f8ecf277a581
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1039390692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.hmac_stress_all_with_rand_reset.1039390692
Directory /workspace/111.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.hmac_stress_all_with_rand_reset.3821802024
Short name T629
Test name
Test status
Simulation time 92221558944 ps
CPU time 4092.44 seconds
Started Feb 07 03:33:29 PM PST 24
Finished Feb 07 04:41:42 PM PST 24
Peak memory 260808 kb
Host smart-cdfc662c-287a-4da5-8e5f-fd7273ab6daf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3821802024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.hmac_stress_all_with_rand_reset.3821802024
Directory /workspace/112.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.hmac_stress_all_with_rand_reset.3412534879
Short name T587
Test name
Test status
Simulation time 230201016715 ps
CPU time 2256.42 seconds
Started Feb 07 03:33:27 PM PST 24
Finished Feb 07 04:11:04 PM PST 24
Peak memory 231160 kb
Host smart-d6d43b74-bd57-47a6-a690-7d8b6fd44d48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412534879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.hmac_stress_all_with_rand_reset.3412534879
Directory /workspace/113.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/114.hmac_stress_all_with_rand_reset.3819111820
Short name T382
Test name
Test status
Simulation time 19012987355 ps
CPU time 360.75 seconds
Started Feb 07 03:33:25 PM PST 24
Finished Feb 07 03:39:26 PM PST 24
Peak memory 215596 kb
Host smart-bd9afc41-c3ba-420d-9a44-f20be676a747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3819111820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.hmac_stress_all_with_rand_reset.3819111820
Directory /workspace/114.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/116.hmac_stress_all_with_rand_reset.2613420070
Short name T4
Test name
Test status
Simulation time 11858335007 ps
CPU time 298.77 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:40:52 PM PST 24
Peak memory 214820 kb
Host smart-141f89ba-1431-4b61-8c82-d6aab99d26eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2613420070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.hmac_stress_all_with_rand_reset.2613420070
Directory /workspace/116.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/118.hmac_stress_all_with_rand_reset.154644239
Short name T412
Test name
Test status
Simulation time 58443215286 ps
CPU time 1122.89 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 03:54:37 PM PST 24
Peak memory 223844 kb
Host smart-ada14bb3-6d9a-452b-a0eb-77eb5fe186fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=154644239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.hmac_stress_all_with_rand_reset.154644239
Directory /workspace/118.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/119.hmac_stress_all_with_rand_reset.2639396560
Short name T643
Test name
Test status
Simulation time 24369254521 ps
CPU time 503.6 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 03:44:26 PM PST 24
Peak memory 237048 kb
Host smart-cbd122e1-424f-4ade-83aa-34cef255cde2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2639396560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.hmac_stress_all_with_rand_reset.2639396560
Directory /workspace/119.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.hmac_alert_test.919513161
Short name T280
Test name
Test status
Simulation time 11394181 ps
CPU time 0.58 seconds
Started Feb 07 03:25:56 PM PST 24
Finished Feb 07 03:25:58 PM PST 24
Peak memory 193416 kb
Host smart-4b0d0996-ca04-44b2-8753-d6f2398f7469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919513161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.919513161
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.642988224
Short name T646
Test name
Test status
Simulation time 997471266 ps
CPU time 8.87 seconds
Started Feb 07 03:25:53 PM PST 24
Finished Feb 07 03:26:02 PM PST 24
Peak memory 211264 kb
Host smart-30bd7961-2e2d-49d3-91a5-ee2db8b28637
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642988224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.642988224
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3952622466
Short name T616
Test name
Test status
Simulation time 4393118116 ps
CPU time 20.03 seconds
Started Feb 07 03:25:58 PM PST 24
Finished Feb 07 03:26:21 PM PST 24
Peak memory 199104 kb
Host smart-36b2f04e-8a08-42ba-b49c-4ce8d2736bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952622466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3952622466
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1388909250
Short name T821
Test name
Test status
Simulation time 14575993733 ps
CPU time 116.42 seconds
Started Feb 07 03:25:52 PM PST 24
Finished Feb 07 03:27:49 PM PST 24
Peak memory 199124 kb
Host smart-c2da10ff-d8b1-4001-a8e3-e639ecead4a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1388909250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1388909250
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.2025272397
Short name T337
Test name
Test status
Simulation time 42608259035 ps
CPU time 176.07 seconds
Started Feb 07 03:25:53 PM PST 24
Finished Feb 07 03:28:49 PM PST 24
Peak memory 199048 kb
Host smart-2714161e-ccbd-4417-8583-15634be8ac42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025272397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.2025272397
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.386294287
Short name T690
Test name
Test status
Simulation time 3441442789 ps
CPU time 24.12 seconds
Started Feb 07 03:25:47 PM PST 24
Finished Feb 07 03:26:11 PM PST 24
Peak memory 199072 kb
Host smart-53c15d81-608c-4009-b101-c529e5906150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386294287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.386294287
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2756219565
Short name T10
Test name
Test status
Simulation time 577705120 ps
CPU time 3.15 seconds
Started Feb 07 03:25:47 PM PST 24
Finished Feb 07 03:25:50 PM PST 24
Peak memory 198800 kb
Host smart-4f5adfde-0763-4f1c-9f60-4ebb14095d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756219565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2756219565
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3381346571
Short name T296
Test name
Test status
Simulation time 14846152827 ps
CPU time 107.78 seconds
Started Feb 07 03:25:57 PM PST 24
Finished Feb 07 03:27:49 PM PST 24
Peak memory 215524 kb
Host smart-d2aceb7f-cc81-4563-861a-63843ef3e33d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381346571 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3381346571
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2417624755
Short name T705
Test name
Test status
Simulation time 87887699 ps
CPU time 0.98 seconds
Started Feb 07 03:25:55 PM PST 24
Finished Feb 07 03:25:57 PM PST 24
Peak memory 196964 kb
Host smart-9b507a03-84be-413e-9077-f615700acebd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417624755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2417624755
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1328906599
Short name T562
Test name
Test status
Simulation time 8159780479 ps
CPU time 415.32 seconds
Started Feb 07 03:25:53 PM PST 24
Finished Feb 07 03:32:49 PM PST 24
Peak memory 199136 kb
Host smart-7f009332-17ef-4235-9d42-03c4066b49ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328906599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.1328906599
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1378675812
Short name T560
Test name
Test status
Simulation time 15610034381 ps
CPU time 73.84 seconds
Started Feb 07 03:25:51 PM PST 24
Finished Feb 07 03:27:05 PM PST 24
Peak memory 199172 kb
Host smart-89981cb2-debd-4dda-ab02-5adacdc4c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378675812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1378675812
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/121.hmac_stress_all_with_rand_reset.1088184313
Short name T331
Test name
Test status
Simulation time 37623108699 ps
CPU time 1568.71 seconds
Started Feb 07 03:35:55 PM PST 24
Finished Feb 07 04:02:04 PM PST 24
Peak memory 231988 kb
Host smart-00632ce9-e9af-483b-8334-c5f983aa7f58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088184313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.hmac_stress_all_with_rand_reset.1088184313
Directory /workspace/121.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/122.hmac_stress_all_with_rand_reset.2112811929
Short name T425
Test name
Test status
Simulation time 85566301385 ps
CPU time 2797.31 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 04:22:31 PM PST 24
Peak memory 256556 kb
Host smart-6c75425f-3f77-409f-a021-8c8cbfa1648a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112811929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.hmac_stress_all_with_rand_reset.2112811929
Directory /workspace/122.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/123.hmac_stress_all_with_rand_reset.3236220580
Short name T620
Test name
Test status
Simulation time 81713571407 ps
CPU time 1465.35 seconds
Started Feb 07 03:35:52 PM PST 24
Finished Feb 07 04:00:18 PM PST 24
Peak memory 239548 kb
Host smart-b625e82a-eac0-452f-9d57-2280b331faf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3236220580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.hmac_stress_all_with_rand_reset.3236220580
Directory /workspace/123.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.1493603480
Short name T666
Test name
Test status
Simulation time 117140674316 ps
CPU time 1679.97 seconds
Started Feb 07 03:35:52 PM PST 24
Finished Feb 07 04:03:53 PM PST 24
Peak memory 245872 kb
Host smart-38fb2b34-8e7c-4f85-8df9-a0e4730e0b0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1493603480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.1493603480
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/125.hmac_stress_all_with_rand_reset.372469912
Short name T105
Test name
Test status
Simulation time 62754835091 ps
CPU time 951.72 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:51:46 PM PST 24
Peak memory 240172 kb
Host smart-16ee860b-dc69-48b9-8467-06f16a7b2458
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=372469912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.hmac_stress_all_with_rand_reset.372469912
Directory /workspace/125.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.4206955355
Short name T219
Test name
Test status
Simulation time 22071191317 ps
CPU time 208.79 seconds
Started Feb 07 03:36:01 PM PST 24
Finished Feb 07 03:39:30 PM PST 24
Peak memory 207416 kb
Host smart-8c106da5-e290-4d17-81b9-cd501a035cfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206955355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.4206955355
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/127.hmac_stress_all_with_rand_reset.2740642115
Short name T301
Test name
Test status
Simulation time 362506897159 ps
CPU time 884.7 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:50:39 PM PST 24
Peak memory 248012 kb
Host smart-08a414c1-696c-48da-907d-587db9af5325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2740642115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.hmac_stress_all_with_rand_reset.2740642115
Directory /workspace/127.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.hmac_stress_all_with_rand_reset.2309793593
Short name T142
Test name
Test status
Simulation time 39548714444 ps
CPU time 728.18 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:48:01 PM PST 24
Peak memory 215604 kb
Host smart-4a969aa2-7bea-4d8b-a77e-8f8a80f92cd3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309793593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.hmac_stress_all_with_rand_reset.2309793593
Directory /workspace/128.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/129.hmac_stress_all_with_rand_reset.268454786
Short name T470
Test name
Test status
Simulation time 70045248457 ps
CPU time 1079.98 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 03:53:55 PM PST 24
Peak memory 240112 kb
Host smart-da3fe9ef-d377-4fd9-9b23-f94cdd9f3434
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268454786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.hmac_stress_all_with_rand_reset.268454786
Directory /workspace/129.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_alert_test.356165080
Short name T253
Test name
Test status
Simulation time 31068833 ps
CPU time 0.58 seconds
Started Feb 07 03:26:03 PM PST 24
Finished Feb 07 03:26:06 PM PST 24
Peak memory 193484 kb
Host smart-83ddf9c3-262f-43e3-8c07-ece87ba7e58a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356165080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.356165080
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2964370970
Short name T642
Test name
Test status
Simulation time 6901046115 ps
CPU time 50.83 seconds
Started Feb 07 03:25:57 PM PST 24
Finished Feb 07 03:26:48 PM PST 24
Peak memory 223648 kb
Host smart-880bab31-ff8a-4046-a4c5-90327c121788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964370970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2964370970
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4145676657
Short name T251
Test name
Test status
Simulation time 313848447 ps
CPU time 14.84 seconds
Started Feb 07 03:26:04 PM PST 24
Finished Feb 07 03:26:20 PM PST 24
Peak memory 199040 kb
Host smart-68be5e78-6e7f-43ba-aabd-5da0fa67985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145676657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4145676657
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1386728522
Short name T238
Test name
Test status
Simulation time 2012646616 ps
CPU time 102.51 seconds
Started Feb 07 03:25:57 PM PST 24
Finished Feb 07 03:27:43 PM PST 24
Peak memory 199092 kb
Host smart-03ca09fc-e5ec-4282-ad73-a6ebd2dea489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386728522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1386728522
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.63987781
Short name T261
Test name
Test status
Simulation time 4429826542 ps
CPU time 20.08 seconds
Started Feb 07 03:26:03 PM PST 24
Finished Feb 07 03:26:25 PM PST 24
Peak memory 199104 kb
Host smart-0b002904-252b-40ff-90d8-71755dd3a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63987781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.63987781
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.3001487
Short name T298
Test name
Test status
Simulation time 3466765927 ps
CPU time 94.64 seconds
Started Feb 07 03:25:56 PM PST 24
Finished Feb 07 03:27:32 PM PST 24
Peak memory 199092 kb
Host smart-b496cd75-0e7b-4d64-8fe9-8b5645098e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.3001487
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1093424663
Short name T212
Test name
Test status
Simulation time 1314267324 ps
CPU time 3.62 seconds
Started Feb 07 03:25:57 PM PST 24
Finished Feb 07 03:26:04 PM PST 24
Peak memory 199044 kb
Host smart-cc910dd5-b75f-47a6-8105-8d8cdda99e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093424663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1093424663
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2179650705
Short name T610
Test name
Test status
Simulation time 111858955036 ps
CPU time 1011.45 seconds
Started Feb 07 03:26:03 PM PST 24
Finished Feb 07 03:42:57 PM PST 24
Peak memory 225560 kb
Host smart-1908870b-53a5-47b2-a969-70e24052ed71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179650705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2179650705
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3600455639
Short name T848
Test name
Test status
Simulation time 43250681 ps
CPU time 0.99 seconds
Started Feb 07 03:26:04 PM PST 24
Finished Feb 07 03:26:06 PM PST 24
Peak memory 197728 kb
Host smart-4e81d6f7-bc9a-441e-9106-0f1927daf047
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600455639 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3600455639
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2605053755
Short name T481
Test name
Test status
Simulation time 29081823614 ps
CPU time 355.38 seconds
Started Feb 07 03:26:02 PM PST 24
Finished Feb 07 03:31:58 PM PST 24
Peak memory 199168 kb
Host smart-52220155-5cc0-4703-8b29-d3f720e78abc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605053755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.2605053755
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2038247505
Short name T595
Test name
Test status
Simulation time 3458050934 ps
CPU time 62.28 seconds
Started Feb 07 03:26:04 PM PST 24
Finished Feb 07 03:27:07 PM PST 24
Peak memory 199108 kb
Host smart-774a7ac3-059b-41ca-acf4-6b1a01eb8c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038247505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2038247505
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/130.hmac_stress_all_with_rand_reset.4157409526
Short name T762
Test name
Test status
Simulation time 58383986517 ps
CPU time 153.45 seconds
Started Feb 07 03:36:01 PM PST 24
Finished Feb 07 03:38:35 PM PST 24
Peak memory 215024 kb
Host smart-1bd4cf3b-2181-4e6d-b83b-531745ae7272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4157409526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.hmac_stress_all_with_rand_reset.4157409526
Directory /workspace/130.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.hmac_stress_all_with_rand_reset.4187573223
Short name T507
Test name
Test status
Simulation time 510516136977 ps
CPU time 2233.73 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 04:13:16 PM PST 24
Peak memory 251312 kb
Host smart-e7644e78-932c-4a1a-814a-40d4a5f1ba3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4187573223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.hmac_stress_all_with_rand_reset.4187573223
Directory /workspace/131.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/132.hmac_stress_all_with_rand_reset.440648395
Short name T415
Test name
Test status
Simulation time 878268525239 ps
CPU time 2350.47 seconds
Started Feb 07 03:35:55 PM PST 24
Finished Feb 07 04:15:06 PM PST 24
Peak memory 248336 kb
Host smart-dd4c4e23-7acb-46a1-a2ff-af9738d510a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440648395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.hmac_stress_all_with_rand_reset.440648395
Directory /workspace/132.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/133.hmac_stress_all_with_rand_reset.1308025745
Short name T402
Test name
Test status
Simulation time 51992307451 ps
CPU time 636.56 seconds
Started Feb 07 03:35:55 PM PST 24
Finished Feb 07 03:46:32 PM PST 24
Peak memory 236260 kb
Host smart-dee9cb42-82ad-4768-9045-25073c22aa31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1308025745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.hmac_stress_all_with_rand_reset.1308025745
Directory /workspace/133.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.662652822
Short name T62
Test name
Test status
Simulation time 189020927330 ps
CPU time 1444.3 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 03:59:59 PM PST 24
Peak memory 230480 kb
Host smart-d96a9e06-e5ef-4d77-a1cb-a7d5d61af13f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662652822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.662652822
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/135.hmac_stress_all_with_rand_reset.1368823898
Short name T785
Test name
Test status
Simulation time 15234567166 ps
CPU time 115.06 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:37:49 PM PST 24
Peak memory 199156 kb
Host smart-6ed34bb8-bb2e-46f8-adc6-054be12c2ae6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1368823898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.hmac_stress_all_with_rand_reset.1368823898
Directory /workspace/135.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.2444765957
Short name T739
Test name
Test status
Simulation time 517065662105 ps
CPU time 5608.81 seconds
Started Feb 07 03:36:01 PM PST 24
Finished Feb 07 05:09:31 PM PST 24
Peak memory 274800 kb
Host smart-057b413e-f2a4-4925-a95f-dbab020572ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444765957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.2444765957
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/137.hmac_stress_all_with_rand_reset.240792147
Short name T611
Test name
Test status
Simulation time 40077536014 ps
CPU time 767.46 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 03:48:42 PM PST 24
Peak memory 227468 kb
Host smart-adec464e-21de-4e75-a9dd-19edf17e1c52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=240792147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.hmac_stress_all_with_rand_reset.240792147
Directory /workspace/137.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/138.hmac_stress_all_with_rand_reset.2042039867
Short name T96
Test name
Test status
Simulation time 68227826140 ps
CPU time 1057.55 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 03:53:32 PM PST 24
Peak memory 242216 kb
Host smart-fa3110e0-2c22-49c4-a182-fbb24d9505ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2042039867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.hmac_stress_all_with_rand_reset.2042039867
Directory /workspace/138.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/139.hmac_stress_all_with_rand_reset.757745376
Short name T264
Test name
Test status
Simulation time 96645606065 ps
CPU time 1625.55 seconds
Started Feb 07 03:35:55 PM PST 24
Finished Feb 07 04:03:01 PM PST 24
Peak memory 215576 kb
Host smart-f75ca50a-52f3-44d5-ab56-ff051cbc4564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757745376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.hmac_stress_all_with_rand_reset.757745376
Directory /workspace/139.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1531516236
Short name T730
Test name
Test status
Simulation time 12269351 ps
CPU time 0.58 seconds
Started Feb 07 03:26:15 PM PST 24
Finished Feb 07 03:26:16 PM PST 24
Peak memory 193460 kb
Host smart-ee4fc082-ebac-4ca3-9965-c50e81fd0e70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531516236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1531516236
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2616372405
Short name T548
Test name
Test status
Simulation time 939168540 ps
CPU time 15.69 seconds
Started Feb 07 03:26:03 PM PST 24
Finished Feb 07 03:26:21 PM PST 24
Peak memory 207204 kb
Host smart-8b926db2-464d-4fec-9563-f20c17f32bae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2616372405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2616372405
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2166193256
Short name T633
Test name
Test status
Simulation time 4361961099 ps
CPU time 31.27 seconds
Started Feb 07 03:26:10 PM PST 24
Finished Feb 07 03:26:42 PM PST 24
Peak memory 199060 kb
Host smart-bdda73d0-e77a-4711-88f6-11ab42d7b518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166193256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2166193256
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.4293650789
Short name T239
Test name
Test status
Simulation time 720804354 ps
CPU time 34.77 seconds
Started Feb 07 03:26:10 PM PST 24
Finished Feb 07 03:26:46 PM PST 24
Peak memory 199052 kb
Host smart-94889b9f-1c95-40c3-9594-273418e36c33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4293650789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.4293650789
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1366864474
Short name T524
Test name
Test status
Simulation time 8092301423 ps
CPU time 95.18 seconds
Started Feb 07 03:26:09 PM PST 24
Finished Feb 07 03:27:45 PM PST 24
Peak memory 199076 kb
Host smart-4579c984-fb1d-4f95-a232-a47e70ba85d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366864474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1366864474
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.461535948
Short name T511
Test name
Test status
Simulation time 1100926808 ps
CPU time 13.54 seconds
Started Feb 07 03:26:04 PM PST 24
Finished Feb 07 03:26:19 PM PST 24
Peak memory 198824 kb
Host smart-01f060e4-a8c0-49cf-baa4-fe0026ded019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461535948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.461535948
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.4234130818
Short name T330
Test name
Test status
Simulation time 842659293 ps
CPU time 2.75 seconds
Started Feb 07 03:26:03 PM PST 24
Finished Feb 07 03:26:06 PM PST 24
Peak memory 198868 kb
Host smart-a74bf654-79eb-4d36-a548-9eb701410970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234130818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.4234130818
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.122349340
Short name T617
Test name
Test status
Simulation time 516106978 ps
CPU time 1.75 seconds
Started Feb 07 03:26:14 PM PST 24
Finished Feb 07 03:26:16 PM PST 24
Peak memory 198540 kb
Host smart-42cdbdb4-e1e2-45d5-9731-9b8530d6e901
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122349340 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.122349340
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_stress_all_with_rand_reset.993232955
Short name T647
Test name
Test status
Simulation time 1173542641698 ps
CPU time 3456 seconds
Started Feb 07 03:26:14 PM PST 24
Finished Feb 07 04:23:51 PM PST 24
Peak memory 224868 kb
Host smart-74bca956-8bd7-493e-8f3f-be142808d5c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993232955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all_with_rand_reset.993232955
Directory /workspace/14.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.4294860275
Short name T822
Test name
Test status
Simulation time 193659857 ps
CPU time 1.19 seconds
Started Feb 07 03:26:13 PM PST 24
Finished Feb 07 03:26:16 PM PST 24
Peak memory 197340 kb
Host smart-7d61e189-e4c0-41fe-b730-11bcb6690381
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294860275 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.4294860275
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.878899064
Short name T558
Test name
Test status
Simulation time 119294546337 ps
CPU time 487.9 seconds
Started Feb 07 03:26:12 PM PST 24
Finished Feb 07 03:34:20 PM PST 24
Peak memory 199136 kb
Host smart-d08aeabe-6fb0-431d-a663-b5af0c437554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878899064 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.hmac_test_sha_vectors.878899064
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1703172587
Short name T313
Test name
Test status
Simulation time 2555029268 ps
CPU time 48.99 seconds
Started Feb 07 03:26:09 PM PST 24
Finished Feb 07 03:26:59 PM PST 24
Peak memory 199124 kb
Host smart-555893c6-5b14-4e8d-a2a1-2da163f7626b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703172587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1703172587
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/140.hmac_stress_all_with_rand_reset.255612654
Short name T555
Test name
Test status
Simulation time 178591222015 ps
CPU time 1638.93 seconds
Started Feb 07 03:35:54 PM PST 24
Finished Feb 07 04:03:14 PM PST 24
Peak memory 246628 kb
Host smart-ec7679b7-ab08-4f26-b019-4f24dc2a43c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=255612654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.hmac_stress_all_with_rand_reset.255612654
Directory /workspace/140.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.hmac_stress_all_with_rand_reset.559387727
Short name T737
Test name
Test status
Simulation time 133578679631 ps
CPU time 1689.71 seconds
Started Feb 07 03:35:52 PM PST 24
Finished Feb 07 04:04:02 PM PST 24
Peak memory 248320 kb
Host smart-e5083414-13ed-4ea4-a051-293a95f64a94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559387727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.hmac_stress_all_with_rand_reset.559387727
Directory /workspace/141.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.3134261406
Short name T354
Test name
Test status
Simulation time 117753176810 ps
CPU time 1267.22 seconds
Started Feb 07 03:35:53 PM PST 24
Finished Feb 07 03:57:01 PM PST 24
Peak memory 247372 kb
Host smart-f6fb4dc4-22d5-45a5-8b20-b0a58839ab40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3134261406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.3134261406
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/143.hmac_stress_all_with_rand_reset.1831486880
Short name T106
Test name
Test status
Simulation time 152964058411 ps
CPU time 1184.79 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 03:55:47 PM PST 24
Peak memory 225248 kb
Host smart-606fe3c2-9d34-443d-93ca-7668b6c7f26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1831486880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.hmac_stress_all_with_rand_reset.1831486880
Directory /workspace/143.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/144.hmac_stress_all_with_rand_reset.2974417909
Short name T63
Test name
Test status
Simulation time 248295988949 ps
CPU time 937.47 seconds
Started Feb 07 03:35:55 PM PST 24
Finished Feb 07 03:51:33 PM PST 24
Peak memory 240168 kb
Host smart-1f7be155-eb73-4bd7-b6fb-1a9a92e54192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2974417909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.hmac_stress_all_with_rand_reset.2974417909
Directory /workspace/144.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/145.hmac_stress_all_with_rand_reset.515713404
Short name T141
Test name
Test status
Simulation time 240641844447 ps
CPU time 879.37 seconds
Started Feb 07 03:36:04 PM PST 24
Finished Feb 07 03:50:44 PM PST 24
Peak memory 240156 kb
Host smart-eb3d6394-1669-4b4d-a596-05163a07ae61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515713404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.hmac_stress_all_with_rand_reset.515713404
Directory /workspace/145.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/146.hmac_stress_all_with_rand_reset.733503108
Short name T95
Test name
Test status
Simulation time 68411775563 ps
CPU time 885.57 seconds
Started Feb 07 03:35:52 PM PST 24
Finished Feb 07 03:50:39 PM PST 24
Peak memory 232964 kb
Host smart-dc5ef640-df8b-4f28-80b3-3da6a6485447
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=733503108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.hmac_stress_all_with_rand_reset.733503108
Directory /workspace/146.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.449066131
Short name T232
Test name
Test status
Simulation time 12386631664 ps
CPU time 177.47 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:38:56 PM PST 24
Peak memory 199268 kb
Host smart-571fde42-c472-4dea-b746-a0c8a02618a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=449066131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.449066131
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.929272103
Short name T669
Test name
Test status
Simulation time 17328804289 ps
CPU time 249.76 seconds
Started Feb 07 03:36:05 PM PST 24
Finished Feb 07 03:40:15 PM PST 24
Peak memory 231940 kb
Host smart-c9b1f0c8-8d8c-4e02-82d4-a9da66dddb2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929272103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.929272103
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.1947779346
Short name T509
Test name
Test status
Simulation time 30457883092 ps
CPU time 1476.72 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 04:00:35 PM PST 24
Peak memory 207396 kb
Host smart-10c7930d-bc77-4e3a-b40f-ccf84bf36149
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1947779346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.1947779346
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.907234432
Short name T252
Test name
Test status
Simulation time 14413857 ps
CPU time 0.58 seconds
Started Feb 07 03:26:33 PM PST 24
Finished Feb 07 03:26:35 PM PST 24
Peak memory 193560 kb
Host smart-f7022d65-7f1a-4fd6-a625-cff6255e099c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907234432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.907234432
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.875236288
Short name T282
Test name
Test status
Simulation time 5152720056 ps
CPU time 60.86 seconds
Started Feb 07 03:26:23 PM PST 24
Finished Feb 07 03:27:24 PM PST 24
Peak memory 199040 kb
Host smart-0be5c740-6093-40d8-84b3-a781cae76561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875236288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.875236288
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.4006790262
Short name T224
Test name
Test status
Simulation time 2651383757 ps
CPU time 36.5 seconds
Started Feb 07 03:26:26 PM PST 24
Finished Feb 07 03:27:03 PM PST 24
Peak memory 199164 kb
Host smart-c8f09dc1-7e6c-4faa-88d7-95c27d8ef1b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006790262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.4006790262
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.1602958922
Short name T342
Test name
Test status
Simulation time 3695040782 ps
CPU time 93.37 seconds
Started Feb 07 03:26:31 PM PST 24
Finished Feb 07 03:28:05 PM PST 24
Peak memory 199080 kb
Host smart-4f630c57-0147-482e-ba49-1e6cbad55350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602958922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.1602958922
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.631585264
Short name T438
Test name
Test status
Simulation time 9195669901 ps
CPU time 33.92 seconds
Started Feb 07 03:26:26 PM PST 24
Finished Feb 07 03:27:00 PM PST 24
Peak memory 199128 kb
Host smart-d7948d0b-9a93-42cd-8bdc-faf4f6405913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631585264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.631585264
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1246434592
Short name T210
Test name
Test status
Simulation time 4964326389 ps
CPU time 4.35 seconds
Started Feb 07 03:26:14 PM PST 24
Finished Feb 07 03:26:19 PM PST 24
Peak memory 199112 kb
Host smart-63d7c1d9-0d2e-4b89-bb65-6a32d01cc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246434592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1246434592
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.2060426760
Short name T612
Test name
Test status
Simulation time 75291674572 ps
CPU time 479.91 seconds
Started Feb 07 03:26:22 PM PST 24
Finished Feb 07 03:34:23 PM PST 24
Peak memory 199072 kb
Host smart-9688c82b-2242-4c88-a8d6-2b00f6e9ae9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060426760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.2060426760
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_stress_all_with_rand_reset.2382786436
Short name T371
Test name
Test status
Simulation time 809677114595 ps
CPU time 642.08 seconds
Started Feb 07 03:26:40 PM PST 24
Finished Feb 07 03:37:23 PM PST 24
Peak memory 246872 kb
Host smart-9a7b44f3-72ac-4aab-93f1-939792ba240a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2382786436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all_with_rand_reset.2382786436
Directory /workspace/15.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.4035338584
Short name T673
Test name
Test status
Simulation time 109552687 ps
CPU time 1.09 seconds
Started Feb 07 03:26:32 PM PST 24
Finished Feb 07 03:26:33 PM PST 24
Peak memory 197180 kb
Host smart-fa47fb87-e5be-4807-a110-6ee97fe17ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035338584 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.4035338584
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2004090031
Short name T404
Test name
Test status
Simulation time 16083196442 ps
CPU time 396.93 seconds
Started Feb 07 03:26:27 PM PST 24
Finished Feb 07 03:33:04 PM PST 24
Peak memory 199120 kb
Host smart-7c1bc468-d4ca-43a3-b875-018d5a4b464b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004090031 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.2004090031
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.683184627
Short name T3
Test name
Test status
Simulation time 11917674979 ps
CPU time 53.37 seconds
Started Feb 07 03:26:22 PM PST 24
Finished Feb 07 03:27:16 PM PST 24
Peak memory 199072 kb
Host smart-e3a4a910-280c-42bf-9243-a32101dda4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683184627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.683184627
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/151.hmac_stress_all_with_rand_reset.3395937731
Short name T674
Test name
Test status
Simulation time 217758284723 ps
CPU time 1988.12 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 04:09:08 PM PST 24
Peak memory 240140 kb
Host smart-1707b119-4136-4a4d-8e2f-72e2434e6837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3395937731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.hmac_stress_all_with_rand_reset.3395937731
Directory /workspace/151.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/153.hmac_stress_all_with_rand_reset.2559149009
Short name T602
Test name
Test status
Simulation time 61770504156 ps
CPU time 852.98 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:50:11 PM PST 24
Peak memory 232004 kb
Host smart-fe5e1885-bc2b-4f4c-8de5-0e3ab0964a51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559149009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.hmac_stress_all_with_rand_reset.2559149009
Directory /workspace/153.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/154.hmac_stress_all_with_rand_reset.1366364467
Short name T58
Test name
Test status
Simulation time 60925447102 ps
CPU time 1669.77 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 04:03:47 PM PST 24
Peak memory 256588 kb
Host smart-154e9514-4e6e-452b-ab76-cacd0e875be2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1366364467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.hmac_stress_all_with_rand_reset.1366364467
Directory /workspace/154.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/155.hmac_stress_all_with_rand_reset.706852319
Short name T776
Test name
Test status
Simulation time 69871150193 ps
CPU time 283.31 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 03:40:43 PM PST 24
Peak memory 214624 kb
Host smart-8a201126-eb7a-4100-a24b-f5332b6d3edf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=706852319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.hmac_stress_all_with_rand_reset.706852319
Directory /workspace/155.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/156.hmac_stress_all_with_rand_reset.1507182109
Short name T98
Test name
Test status
Simulation time 56659517766 ps
CPU time 2229.82 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 04:13:08 PM PST 24
Peak memory 253056 kb
Host smart-fdefa0b9-2629-4188-ac0d-bcefb17cc77d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1507182109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.hmac_stress_all_with_rand_reset.1507182109
Directory /workspace/156.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/157.hmac_stress_all_with_rand_reset.241093667
Short name T671
Test name
Test status
Simulation time 22859639451 ps
CPU time 417.75 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:42:56 PM PST 24
Peak memory 215552 kb
Host smart-69bb5147-4832-4e34-b836-6ebea519228b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=241093667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.hmac_stress_all_with_rand_reset.241093667
Directory /workspace/157.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/158.hmac_stress_all_with_rand_reset.611731933
Short name T312
Test name
Test status
Simulation time 42630986916 ps
CPU time 173.96 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 03:38:51 PM PST 24
Peak memory 207400 kb
Host smart-b505e951-a4af-483b-895b-d76e41f3c442
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=611731933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.hmac_stress_all_with_rand_reset.611731933
Directory /workspace/158.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/159.hmac_stress_all_with_rand_reset.2423007650
Short name T812
Test name
Test status
Simulation time 90798334744 ps
CPU time 392.58 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 03:42:30 PM PST 24
Peak memory 229436 kb
Host smart-9a7f20c3-a329-47f3-b70f-76defaf6e214
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423007650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.hmac_stress_all_with_rand_reset.2423007650
Directory /workspace/159.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3943808970
Short name T649
Test name
Test status
Simulation time 59994760 ps
CPU time 0.57 seconds
Started Feb 07 03:26:46 PM PST 24
Finished Feb 07 03:26:47 PM PST 24
Peak memory 193444 kb
Host smart-029fbe32-7aa7-4b00-abf1-1b5d4f002fc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943808970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3943808970
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1878785027
Short name T259
Test name
Test status
Simulation time 1419990377 ps
CPU time 4.6 seconds
Started Feb 07 03:26:34 PM PST 24
Finished Feb 07 03:26:39 PM PST 24
Peak memory 207292 kb
Host smart-1f97c8bd-f489-45bc-9940-a7228c3c5f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878785027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1878785027
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.866280743
Short name T398
Test name
Test status
Simulation time 9605942970 ps
CPU time 30.65 seconds
Started Feb 07 03:26:42 PM PST 24
Finished Feb 07 03:27:13 PM PST 24
Peak memory 199060 kb
Host smart-61c003c7-2aba-450b-b77c-e0b1cbc71492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866280743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.866280743
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4055008609
Short name T600
Test name
Test status
Simulation time 2598119872 ps
CPU time 53.59 seconds
Started Feb 07 03:26:36 PM PST 24
Finished Feb 07 03:27:30 PM PST 24
Peak memory 199068 kb
Host smart-c583994b-a5e0-4598-89d1-2d6de47368de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4055008609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4055008609
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.3260161984
Short name T820
Test name
Test status
Simulation time 14097461008 ps
CPU time 124.71 seconds
Started Feb 07 03:26:33 PM PST 24
Finished Feb 07 03:28:38 PM PST 24
Peak memory 199104 kb
Host smart-abdf44f9-5b52-4af1-979f-c248e6c74fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260161984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.3260161984
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.2457700709
Short name T681
Test name
Test status
Simulation time 1838077177 ps
CPU time 33.76 seconds
Started Feb 07 03:26:36 PM PST 24
Finished Feb 07 03:27:11 PM PST 24
Peak memory 198980 kb
Host smart-cbcce2c1-91b0-4d1a-9061-021c998921d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457700709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.2457700709
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2459621737
Short name T285
Test name
Test status
Simulation time 214680151 ps
CPU time 3.67 seconds
Started Feb 07 03:26:33 PM PST 24
Finished Feb 07 03:26:37 PM PST 24
Peak memory 198768 kb
Host smart-c13ad5f7-2119-4afb-aae4-57d9a86ac673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459621737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2459621737
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.682369152
Short name T569
Test name
Test status
Simulation time 427354851830 ps
CPU time 1466.2 seconds
Started Feb 07 03:26:40 PM PST 24
Finished Feb 07 03:51:07 PM PST 24
Peak memory 232744 kb
Host smart-6a1a15aa-af32-439b-9101-8ffbc87b83ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682369152 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.682369152
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_stress_all_with_rand_reset.710312431
Short name T324
Test name
Test status
Simulation time 28888922691 ps
CPU time 473.12 seconds
Started Feb 07 03:26:42 PM PST 24
Finished Feb 07 03:34:36 PM PST 24
Peak memory 215412 kb
Host smart-b40eda2d-f5d1-4c0f-a3b0-0843b33b2da5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=710312431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all_with_rand_reset.710312431
Directory /workspace/16.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.620891325
Short name T722
Test name
Test status
Simulation time 106059954 ps
CPU time 1.07 seconds
Started Feb 07 03:26:40 PM PST 24
Finished Feb 07 03:26:41 PM PST 24
Peak memory 197368 kb
Host smart-9ab90e0a-d999-4745-b4cd-aed5eb8cb898
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620891325 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_hmac_vectors.620891325
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.400504402
Short name T203
Test name
Test status
Simulation time 96426720587 ps
CPU time 418.91 seconds
Started Feb 07 03:26:36 PM PST 24
Finished Feb 07 03:33:36 PM PST 24
Peak memory 199156 kb
Host smart-3de829d8-5b7c-44d4-850d-6606d9187ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400504402 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.hmac_test_sha_vectors.400504402
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3619605228
Short name T245
Test name
Test status
Simulation time 589740149 ps
CPU time 8.24 seconds
Started Feb 07 03:26:38 PM PST 24
Finished Feb 07 03:26:47 PM PST 24
Peak memory 199020 kb
Host smart-0c7f1296-2820-4edc-9dbf-cdc05ac8c6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619605228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3619605228
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/161.hmac_stress_all_with_rand_reset.3708856361
Short name T120
Test name
Test status
Simulation time 137291914502 ps
CPU time 5310.43 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 05:04:31 PM PST 24
Peak memory 266564 kb
Host smart-8a7b3935-18f4-40d8-964b-1c9723d1b763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708856361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.hmac_stress_all_with_rand_reset.3708856361
Directory /workspace/161.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/162.hmac_stress_all_with_rand_reset.1618559658
Short name T117
Test name
Test status
Simulation time 80222562612 ps
CPU time 933.77 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 03:51:33 PM PST 24
Peak memory 243988 kb
Host smart-fb848c6b-d661-4f3d-a581-d01802a02e2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618559658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.hmac_stress_all_with_rand_reset.1618559658
Directory /workspace/162.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/164.hmac_stress_all_with_rand_reset.4188362012
Short name T692
Test name
Test status
Simulation time 65328168953 ps
CPU time 1087.75 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:54:06 PM PST 24
Peak memory 231916 kb
Host smart-22eabb45-2557-4c33-b8b2-e0d56350eb22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188362012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.hmac_stress_all_with_rand_reset.4188362012
Directory /workspace/164.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/166.hmac_stress_all_with_rand_reset.3852014295
Short name T46
Test name
Test status
Simulation time 18776070611 ps
CPU time 936.97 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 03:51:35 PM PST 24
Peak memory 231952 kb
Host smart-28856281-8ec9-476a-8c51-199f0bf51384
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852014295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.hmac_stress_all_with_rand_reset.3852014295
Directory /workspace/166.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/167.hmac_stress_all_with_rand_reset.3869597199
Short name T490
Test name
Test status
Simulation time 160480169105 ps
CPU time 1391.44 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:59:10 PM PST 24
Peak memory 215576 kb
Host smart-e12b2ebc-2c35-41d1-a8f7-ed543bfc6fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869597199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.hmac_stress_all_with_rand_reset.3869597199
Directory /workspace/167.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/168.hmac_stress_all_with_rand_reset.1553564800
Short name T763
Test name
Test status
Simulation time 589881505714 ps
CPU time 2908.34 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 04:24:26 PM PST 24
Peak memory 256516 kb
Host smart-4f484455-5a4b-4b06-8f10-6f9edba2d061
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553564800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.hmac_stress_all_with_rand_reset.1553564800
Directory /workspace/168.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/169.hmac_stress_all_with_rand_reset.1087390634
Short name T660
Test name
Test status
Simulation time 48085690373 ps
CPU time 734.15 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:48:12 PM PST 24
Peak memory 215576 kb
Host smart-db5d9831-a976-499d-8e91-6a554519b99d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1087390634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.hmac_stress_all_with_rand_reset.1087390634
Directory /workspace/169.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2131512831
Short name T250
Test name
Test status
Simulation time 15119475 ps
CPU time 0.61 seconds
Started Feb 07 03:26:52 PM PST 24
Finished Feb 07 03:26:53 PM PST 24
Peak memory 193412 kb
Host smart-a6c968eb-5d2a-4ede-9a35-4c01ab618515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131512831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2131512831
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.2339765144
Short name T667
Test name
Test status
Simulation time 2272509061 ps
CPU time 46.34 seconds
Started Feb 07 03:26:36 PM PST 24
Finished Feb 07 03:27:22 PM PST 24
Peak memory 225952 kb
Host smart-781daae1-53d2-49d4-85a1-b2f7fe406594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2339765144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.2339765144
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.152402483
Short name T565
Test name
Test status
Simulation time 1931869336 ps
CPU time 36.46 seconds
Started Feb 07 03:26:45 PM PST 24
Finished Feb 07 03:27:22 PM PST 24
Peak memory 199076 kb
Host smart-a18221cc-f84b-48d1-a450-1ae677c13bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152402483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.152402483
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3534928296
Short name T664
Test name
Test status
Simulation time 697574494 ps
CPU time 8.87 seconds
Started Feb 07 03:26:51 PM PST 24
Finished Feb 07 03:27:00 PM PST 24
Peak memory 198984 kb
Host smart-82a1034b-eb95-4257-93a6-1537478053d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3534928296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3534928296
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1377502861
Short name T790
Test name
Test status
Simulation time 13496230809 ps
CPU time 138.06 seconds
Started Feb 07 03:26:46 PM PST 24
Finished Feb 07 03:29:04 PM PST 24
Peak memory 199072 kb
Host smart-86b12ee7-2a92-47a7-b63a-7e361c3b3ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377502861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1377502861
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.1462248982
Short name T527
Test name
Test status
Simulation time 29363686007 ps
CPU time 54.99 seconds
Started Feb 07 03:26:40 PM PST 24
Finished Feb 07 03:27:36 PM PST 24
Peak memory 199064 kb
Host smart-03881c7a-fbad-46e2-bb85-6d1fbe52e3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462248982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.1462248982
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.667984117
Short name T315
Test name
Test status
Simulation time 217121229 ps
CPU time 2.72 seconds
Started Feb 07 03:26:36 PM PST 24
Finished Feb 07 03:26:39 PM PST 24
Peak memory 199016 kb
Host smart-194da43e-003b-4acb-894b-e3a64381d1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667984117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.667984117
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3622884822
Short name T818
Test name
Test status
Simulation time 13312964323 ps
CPU time 671.21 seconds
Started Feb 07 03:26:54 PM PST 24
Finished Feb 07 03:38:05 PM PST 24
Peak memory 219848 kb
Host smart-3ee397c0-c64b-4e80-85c9-1526b9dc32b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622884822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3622884822
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_stress_all_with_rand_reset.1749583459
Short name T786
Test name
Test status
Simulation time 6190421999 ps
CPU time 98.73 seconds
Started Feb 07 03:26:49 PM PST 24
Finished Feb 07 03:28:28 PM PST 24
Peak memory 223708 kb
Host smart-35ca98ae-864e-4d0b-b6b1-3e0c6c1a4d29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749583459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all_with_rand_reset.1749583459
Directory /workspace/17.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2501312623
Short name T547
Test name
Test status
Simulation time 68825945 ps
CPU time 1.13 seconds
Started Feb 07 03:26:53 PM PST 24
Finished Feb 07 03:26:54 PM PST 24
Peak memory 197852 kb
Host smart-908bf0ab-a88e-4172-80fd-cf1f4b41fc5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501312623 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2501312623
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2624431176
Short name T421
Test name
Test status
Simulation time 586624847 ps
CPU time 31.26 seconds
Started Feb 07 03:26:45 PM PST 24
Finished Feb 07 03:27:16 PM PST 24
Peak memory 199092 kb
Host smart-3dfb101b-c3df-4d66-8c89-111d52b9204a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624431176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2624431176
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.3098510963
Short name T505
Test name
Test status
Simulation time 92646285277 ps
CPU time 1388.81 seconds
Started Feb 07 03:36:01 PM PST 24
Finished Feb 07 03:59:11 PM PST 24
Peak memory 263784 kb
Host smart-1eff33ba-86ab-46cc-8920-e1d3f71efd0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3098510963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.3098510963
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.hmac_stress_all_with_rand_reset.1149089487
Short name T675
Test name
Test status
Simulation time 64046934937 ps
CPU time 546.23 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 03:45:09 PM PST 24
Peak memory 243608 kb
Host smart-5371ffae-e4e1-4520-b7bf-783cda3bbea5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1149089487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.hmac_stress_all_with_rand_reset.1149089487
Directory /workspace/171.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/172.hmac_stress_all_with_rand_reset.1409972298
Short name T406
Test name
Test status
Simulation time 189665853419 ps
CPU time 1063.58 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 03:53:43 PM PST 24
Peak memory 256580 kb
Host smart-04512571-aee6-462b-826b-81ca7b20ca90
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409972298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.hmac_stress_all_with_rand_reset.1409972298
Directory /workspace/172.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/173.hmac_stress_all_with_rand_reset.27919889
Short name T352
Test name
Test status
Simulation time 284933240279 ps
CPU time 1274.27 seconds
Started Feb 07 03:36:03 PM PST 24
Finished Feb 07 03:57:18 PM PST 24
Peak memory 256476 kb
Host smart-369c6824-14c7-4a9a-a7c2-7295a65ebf3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=27919889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.hmac_stress_all_with_rand_reset.27919889
Directory /workspace/173.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.3077206028
Short name T419
Test name
Test status
Simulation time 11644912919 ps
CPU time 530.39 seconds
Started Feb 07 03:35:58 PM PST 24
Finished Feb 07 03:44:49 PM PST 24
Peak memory 231136 kb
Host smart-fecb1a3f-15de-4b1f-8a8f-947cde0d51e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077206028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.3077206028
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/175.hmac_stress_all_with_rand_reset.3943026055
Short name T688
Test name
Test status
Simulation time 40433642720 ps
CPU time 544.16 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 03:45:04 PM PST 24
Peak memory 207420 kb
Host smart-b6406446-b35d-46d2-9b7d-c233cfec1b38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943026055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.hmac_stress_all_with_rand_reset.3943026055
Directory /workspace/175.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/177.hmac_stress_all_with_rand_reset.2644990640
Short name T787
Test name
Test status
Simulation time 71893360953 ps
CPU time 749.14 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 03:48:29 PM PST 24
Peak memory 215180 kb
Host smart-0abf20d8-d643-41b5-b0e7-aa24a0ec30e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644990640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.hmac_stress_all_with_rand_reset.2644990640
Directory /workspace/177.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.1118259538
Short name T839
Test name
Test status
Simulation time 54946420616 ps
CPU time 2245.75 seconds
Started Feb 07 03:35:59 PM PST 24
Finished Feb 07 04:13:25 PM PST 24
Peak memory 240508 kb
Host smart-b0d1c2e4-af5f-4380-8d02-f7e0d23eba3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118259538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.1118259538
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/179.hmac_stress_all_with_rand_reset.4197444551
Short name T122
Test name
Test status
Simulation time 131440820989 ps
CPU time 5653.24 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 05:10:17 PM PST 24
Peak memory 264752 kb
Host smart-a2cb1217-a11c-49d2-8ba9-9bca80687d65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197444551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.hmac_stress_all_with_rand_reset.4197444551
Directory /workspace/179.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1492610129
Short name T387
Test name
Test status
Simulation time 27794099 ps
CPU time 0.6 seconds
Started Feb 07 03:26:57 PM PST 24
Finished Feb 07 03:26:58 PM PST 24
Peak memory 194480 kb
Host smart-50ce8dce-601d-4fd7-9034-02ce2b4799fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492610129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1492610129
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.4107672684
Short name T262
Test name
Test status
Simulation time 1672875379 ps
CPU time 54.64 seconds
Started Feb 07 03:26:51 PM PST 24
Finished Feb 07 03:27:46 PM PST 24
Peak memory 219840 kb
Host smart-79a2ba15-281a-4722-89b2-748b603ac528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107672684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.4107672684
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.1576153332
Short name T528
Test name
Test status
Simulation time 10095912241 ps
CPU time 75.02 seconds
Started Feb 07 03:26:49 PM PST 24
Finished Feb 07 03:28:04 PM PST 24
Peak memory 198916 kb
Host smart-63e0d4d3-24c4-4c74-a565-654c7c8e7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576153332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.1576153332
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3070454818
Short name T608
Test name
Test status
Simulation time 1519032409 ps
CPU time 79.57 seconds
Started Feb 07 03:26:51 PM PST 24
Finished Feb 07 03:28:11 PM PST 24
Peak memory 199000 kb
Host smart-d313b178-ef24-4aa1-9fa0-2bbaa2bb1639
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070454818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3070454818
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.915789923
Short name T808
Test name
Test status
Simulation time 3484046222 ps
CPU time 43.03 seconds
Started Feb 07 03:26:57 PM PST 24
Finished Feb 07 03:27:41 PM PST 24
Peak memory 199088 kb
Host smart-7938f7f7-7cf2-469b-bb47-e8a05b49ff49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915789923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.915789923
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2654949311
Short name T519
Test name
Test status
Simulation time 2548388268 ps
CPU time 31.28 seconds
Started Feb 07 03:26:49 PM PST 24
Finished Feb 07 03:27:21 PM PST 24
Peak memory 199072 kb
Host smart-9b83f8f1-f44d-45db-884d-033f57a5c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654949311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2654949311
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4252586788
Short name T60
Test name
Test status
Simulation time 50898377 ps
CPU time 0.68 seconds
Started Feb 07 03:26:46 PM PST 24
Finished Feb 07 03:26:47 PM PST 24
Peak memory 194540 kb
Host smart-3b84d53b-3bd0-42b6-9583-6340f04546c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252586788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4252586788
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3975676678
Short name T720
Test name
Test status
Simulation time 503889898216 ps
CPU time 1397.38 seconds
Started Feb 07 03:26:57 PM PST 24
Finished Feb 07 03:50:15 PM PST 24
Peak memory 199144 kb
Host smart-62b7603e-8f70-46cc-9592-d5919ea5a5ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975676678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3975676678
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_stress_all_with_rand_reset.3132091350
Short name T551
Test name
Test status
Simulation time 48544332730 ps
CPU time 2486.86 seconds
Started Feb 07 03:26:58 PM PST 24
Finished Feb 07 04:08:25 PM PST 24
Peak memory 215540 kb
Host smart-a6b19b12-e7ec-4c6a-bdf8-7b4d47dfcfc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3132091350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all_with_rand_reset.3132091350
Directory /workspace/18.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.142680540
Short name T293
Test name
Test status
Simulation time 107684291 ps
CPU time 1.09 seconds
Started Feb 07 03:26:59 PM PST 24
Finished Feb 07 03:27:00 PM PST 24
Peak memory 196932 kb
Host smart-1074b7ec-975d-43c5-94d5-b8502cec8081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142680540 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_hmac_vectors.142680540
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3416478703
Short name T395
Test name
Test status
Simulation time 26885297093 ps
CPU time 433.15 seconds
Started Feb 07 03:26:58 PM PST 24
Finished Feb 07 03:34:12 PM PST 24
Peak memory 199112 kb
Host smart-29b82900-2e6a-4058-8d79-17944b8ade77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416478703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.3416478703
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.378805763
Short name T279
Test name
Test status
Simulation time 6087864506 ps
CPU time 34.66 seconds
Started Feb 07 03:26:59 PM PST 24
Finished Feb 07 03:27:34 PM PST 24
Peak memory 199080 kb
Host smart-bf9e874c-034b-4852-a674-75c9c60afa45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378805763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.378805763
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.1378802788
Short name T429
Test name
Test status
Simulation time 22347303335 ps
CPU time 392.58 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 03:42:35 PM PST 24
Peak memory 215544 kb
Host smart-270ef5fe-3f1a-4646-87a9-7f50c7cf2a8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1378802788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.1378802788
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.hmac_stress_all_with_rand_reset.2533332824
Short name T384
Test name
Test status
Simulation time 233764525338 ps
CPU time 648.92 seconds
Started Feb 07 03:35:57 PM PST 24
Finished Feb 07 03:46:47 PM PST 24
Peak memory 225372 kb
Host smart-3dc9e02d-260e-449d-abc0-db72eb1037b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533332824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.hmac_stress_all_with_rand_reset.2533332824
Directory /workspace/181.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.3854946889
Short name T45
Test name
Test status
Simulation time 70215899268 ps
CPU time 1225 seconds
Started Feb 07 03:36:04 PM PST 24
Finished Feb 07 03:56:29 PM PST 24
Peak memory 240116 kb
Host smart-3df0f624-d0dc-45e0-bf45-6730691c79b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854946889 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.3854946889
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/183.hmac_stress_all_with_rand_reset.1832031781
Short name T403
Test name
Test status
Simulation time 430958696620 ps
CPU time 3321.79 seconds
Started Feb 07 03:36:00 PM PST 24
Finished Feb 07 04:31:22 PM PST 24
Peak memory 242372 kb
Host smart-ff35d75e-f51c-4bcb-8d29-da0d94c93de3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1832031781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.hmac_stress_all_with_rand_reset.1832031781
Directory /workspace/183.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/184.hmac_stress_all_with_rand_reset.3833288919
Short name T670
Test name
Test status
Simulation time 230206900199 ps
CPU time 4350.86 seconds
Started Feb 07 03:36:01 PM PST 24
Finished Feb 07 04:48:33 PM PST 24
Peak memory 259688 kb
Host smart-7dcda26f-a498-47dd-ae88-aa487a4412fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833288919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.hmac_stress_all_with_rand_reset.3833288919
Directory /workspace/184.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/185.hmac_stress_all_with_rand_reset.4126285888
Short name T753
Test name
Test status
Simulation time 265844119904 ps
CPU time 1421 seconds
Started Feb 07 03:36:02 PM PST 24
Finished Feb 07 03:59:43 PM PST 24
Peak memory 256508 kb
Host smart-263e4266-4382-4e09-8935-6e966bd0dec7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126285888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.hmac_stress_all_with_rand_reset.4126285888
Directory /workspace/185.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/186.hmac_stress_all_with_rand_reset.1096979745
Short name T134
Test name
Test status
Simulation time 67093071952 ps
CPU time 2666.33 seconds
Started Feb 07 03:36:04 PM PST 24
Finished Feb 07 04:20:32 PM PST 24
Peak memory 245808 kb
Host smart-85b3a024-84d7-44d2-984c-b0250b0eb56f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1096979745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.hmac_stress_all_with_rand_reset.1096979745
Directory /workspace/186.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.688003442
Short name T502
Test name
Test status
Simulation time 366064086262 ps
CPU time 4357.25 seconds
Started Feb 07 03:36:24 PM PST 24
Finished Feb 07 04:49:06 PM PST 24
Peak memory 260272 kb
Host smart-87494918-c60d-4bd5-9437-473219c96d80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688003442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.688003442
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/188.hmac_stress_all_with_rand_reset.453268622
Short name T242
Test name
Test status
Simulation time 22072237372 ps
CPU time 32.18 seconds
Started Feb 07 03:36:27 PM PST 24
Finished Feb 07 03:37:01 PM PST 24
Peak memory 230348 kb
Host smart-1f39e9d1-169d-40dd-9b72-d4397a09cd85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453268622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.hmac_stress_all_with_rand_reset.453268622
Directory /workspace/188.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/189.hmac_stress_all_with_rand_reset.1775194924
Short name T143
Test name
Test status
Simulation time 83728776542 ps
CPU time 447.67 seconds
Started Feb 07 03:36:27 PM PST 24
Finished Feb 07 03:43:57 PM PST 24
Peak memory 228252 kb
Host smart-8897c489-fa8a-4125-aeaf-f300fa642e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775194924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.hmac_stress_all_with_rand_reset.1775194924
Directory /workspace/189.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4264381987
Short name T622
Test name
Test status
Simulation time 31386887 ps
CPU time 0.56 seconds
Started Feb 07 03:27:12 PM PST 24
Finished Feb 07 03:27:13 PM PST 24
Peak memory 193460 kb
Host smart-f8e77e63-947f-46ba-9ea4-485a9891b44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264381987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4264381987
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3183102283
Short name T277
Test name
Test status
Simulation time 849406658 ps
CPU time 33.97 seconds
Started Feb 07 03:26:59 PM PST 24
Finished Feb 07 03:27:34 PM PST 24
Peak memory 227648 kb
Host smart-b28e5330-9144-4ae1-ba5f-bc8bc502b3a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3183102283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3183102283
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3761051638
Short name T572
Test name
Test status
Simulation time 6944895439 ps
CPU time 23.16 seconds
Started Feb 07 03:27:00 PM PST 24
Finished Feb 07 03:27:24 PM PST 24
Peak memory 199128 kb
Host smart-10e93185-d632-4099-b8c9-beb3f1729bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761051638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3761051638
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.363188409
Short name T537
Test name
Test status
Simulation time 1323463068 ps
CPU time 52.04 seconds
Started Feb 07 03:26:58 PM PST 24
Finished Feb 07 03:27:50 PM PST 24
Peak memory 199020 kb
Host smart-242fa01d-6bc7-4731-a245-022b0a6c46d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=363188409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.363188409
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3770670264
Short name T575
Test name
Test status
Simulation time 10965866113 ps
CPU time 123.04 seconds
Started Feb 07 03:26:59 PM PST 24
Finished Feb 07 03:29:03 PM PST 24
Peak memory 199028 kb
Host smart-389c3360-26f6-45e3-9453-15f1978b0aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770670264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3770670264
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.40500899
Short name T501
Test name
Test status
Simulation time 9209359910 ps
CPU time 39.96 seconds
Started Feb 07 03:27:00 PM PST 24
Finished Feb 07 03:27:40 PM PST 24
Peak memory 199120 kb
Host smart-56a6fd2b-0361-4d2b-b376-b4fd572b30e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40500899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.40500899
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3925177410
Short name T654
Test name
Test status
Simulation time 154223342 ps
CPU time 1.32 seconds
Started Feb 07 03:26:57 PM PST 24
Finished Feb 07 03:26:59 PM PST 24
Peak memory 198776 kb
Host smart-5662469f-90b2-454f-b65f-f870d03af6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925177410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3925177410
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2710801297
Short name T640
Test name
Test status
Simulation time 48589048610 ps
CPU time 432.49 seconds
Started Feb 07 03:27:10 PM PST 24
Finished Feb 07 03:34:23 PM PST 24
Peak memory 199132 kb
Host smart-845f5803-5d5f-450c-ba7c-d6dc5cb19158
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710801297 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2710801297
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_stress_all_with_rand_reset.642146249
Short name T132
Test name
Test status
Simulation time 351605040700 ps
CPU time 1660.62 seconds
Started Feb 07 03:27:13 PM PST 24
Finished Feb 07 03:54:55 PM PST 24
Peak memory 245764 kb
Host smart-3217f84d-72d6-4441-917f-48c38d816548
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=642146249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all_with_rand_reset.642146249
Directory /workspace/19.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1113364075
Short name T761
Test name
Test status
Simulation time 96767388 ps
CPU time 1.09 seconds
Started Feb 07 03:27:12 PM PST 24
Finished Feb 07 03:27:14 PM PST 24
Peak memory 197516 kb
Host smart-12f9e080-6443-4bd2-92c5-e6659b006fac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113364075 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1113364075
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3081398027
Short name T236
Test name
Test status
Simulation time 16128614803 ps
CPU time 76.79 seconds
Started Feb 07 03:26:59 PM PST 24
Finished Feb 07 03:28:16 PM PST 24
Peak memory 199116 kb
Host smart-ea792fd5-9bae-4d43-8892-e82f89b822b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081398027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3081398027
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3864958213
Short name T604
Test name
Test status
Simulation time 18825917894 ps
CPU time 986.9 seconds
Started Feb 07 03:36:27 PM PST 24
Finished Feb 07 03:52:56 PM PST 24
Peak memory 215592 kb
Host smart-3b099a78-9825-457f-9ba1-71d157e682ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3864958213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3864958213
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/191.hmac_stress_all_with_rand_reset.979724845
Short name T573
Test name
Test status
Simulation time 154189406540 ps
CPU time 1043.12 seconds
Started Feb 07 03:36:46 PM PST 24
Finished Feb 07 03:54:10 PM PST 24
Peak memory 215544 kb
Host smart-c8cd9904-3aba-4773-a811-b4e0f425d241
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=979724845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.hmac_stress_all_with_rand_reset.979724845
Directory /workspace/191.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.3674956448
Short name T578
Test name
Test status
Simulation time 37535205396 ps
CPU time 594.58 seconds
Started Feb 07 03:36:36 PM PST 24
Finished Feb 07 03:46:32 PM PST 24
Peak memory 229276 kb
Host smart-8c49fb2e-9790-482d-8281-050f6bac1140
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3674956448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.3674956448
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.1971146948
Short name T484
Test name
Test status
Simulation time 171444730538 ps
CPU time 733.12 seconds
Started Feb 07 03:36:45 PM PST 24
Finished Feb 07 03:48:58 PM PST 24
Peak memory 214736 kb
Host smart-85f7f12f-178d-4a70-a604-52602a432834
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971146948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.1971146948
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.370327893
Short name T554
Test name
Test status
Simulation time 103656840747 ps
CPU time 634.02 seconds
Started Feb 07 03:36:48 PM PST 24
Finished Feb 07 03:47:23 PM PST 24
Peak memory 242328 kb
Host smart-2dc66980-e2e7-4bad-9ef8-598c0b5c0ce9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370327893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.370327893
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/196.hmac_stress_all_with_rand_reset.87347416
Short name T627
Test name
Test status
Simulation time 122640075354 ps
CPU time 5326.48 seconds
Started Feb 07 03:36:52 PM PST 24
Finished Feb 07 05:05:39 PM PST 24
Peak memory 264692 kb
Host smart-aa16d341-8cd0-436a-aa72-c9f2354fa475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=87347416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.hmac_stress_all_with_rand_reset.87347416
Directory /workspace/196.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/197.hmac_stress_all_with_rand_reset.2507063589
Short name T139
Test name
Test status
Simulation time 435465337082 ps
CPU time 2070.85 seconds
Started Feb 07 03:36:52 PM PST 24
Finished Feb 07 04:11:24 PM PST 24
Peak memory 245244 kb
Host smart-c4cb2425-1832-42a8-8a41-2a71a655f587
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2507063589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.hmac_stress_all_with_rand_reset.2507063589
Directory /workspace/197.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/198.hmac_stress_all_with_rand_reset.3714198788
Short name T110
Test name
Test status
Simulation time 118999780204 ps
CPU time 559.09 seconds
Started Feb 07 03:36:52 PM PST 24
Finished Feb 07 03:46:12 PM PST 24
Peak memory 215568 kb
Host smart-e3166c32-e2b0-4323-964d-59b864279b1b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3714198788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.hmac_stress_all_with_rand_reset.3714198788
Directory /workspace/198.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/199.hmac_stress_all_with_rand_reset.4013061700
Short name T124
Test name
Test status
Simulation time 221015350722 ps
CPU time 2400.09 seconds
Started Feb 07 03:37:02 PM PST 24
Finished Feb 07 04:17:03 PM PST 24
Peak memory 225672 kb
Host smart-868f3535-380e-45ea-87f7-58e395cdd105
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013061700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.hmac_stress_all_with_rand_reset.4013061700
Directory /workspace/199.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1270552337
Short name T464
Test name
Test status
Simulation time 11597019 ps
CPU time 0.55 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:24:34 PM PST 24
Peak memory 193360 kb
Host smart-8c817ddd-fda7-4643-aa59-b838eeb5dbd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270552337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1270552337
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1720293537
Short name T263
Test name
Test status
Simulation time 4836101945 ps
CPU time 46.9 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:25:20 PM PST 24
Peak memory 222760 kb
Host smart-51de7791-1918-43d6-af65-07c75c52b225
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1720293537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1720293537
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2720436790
Short name T374
Test name
Test status
Simulation time 629513625 ps
CPU time 2.74 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:24:37 PM PST 24
Peak memory 198952 kb
Host smart-25cc66a9-36bf-4073-ad12-2263734bfe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720436790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2720436790
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1679745243
Short name T735
Test name
Test status
Simulation time 1257191544 ps
CPU time 71.35 seconds
Started Feb 07 03:24:28 PM PST 24
Finished Feb 07 03:25:40 PM PST 24
Peak memory 199048 kb
Host smart-4efc6fe2-e311-47c4-9ba9-15d090f54669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679745243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1679745243
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4142808113
Short name T717
Test name
Test status
Simulation time 31165425679 ps
CPU time 99.35 seconds
Started Feb 07 03:24:34 PM PST 24
Finished Feb 07 03:26:14 PM PST 24
Peak memory 199092 kb
Host smart-8d61f706-0189-4707-8c91-0c73d062556a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142808113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4142808113
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3677398585
Short name T302
Test name
Test status
Simulation time 10216314620 ps
CPU time 37.49 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:25:10 PM PST 24
Peak memory 199092 kb
Host smart-c3b90e74-e05e-4dd6-8f99-ae3835a53b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677398585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3677398585
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.2952465664
Short name T54
Test name
Test status
Simulation time 374526891 ps
CPU time 0.92 seconds
Started Feb 07 03:24:23 PM PST 24
Finished Feb 07 03:24:25 PM PST 24
Peak memory 216104 kb
Host smart-b039e2bf-567e-4f91-9ced-d8ef7b8f5ced
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952465664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.2952465664
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.3075653639
Short name T659
Test name
Test status
Simulation time 20478314 ps
CPU time 0.61 seconds
Started Feb 07 03:24:28 PM PST 24
Finished Feb 07 03:24:29 PM PST 24
Peak memory 194128 kb
Host smart-ecd06240-b05f-483d-9608-f58c5c1fbf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075653639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.3075653639
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3247543302
Short name T658
Test name
Test status
Simulation time 263577506013 ps
CPU time 1096.9 seconds
Started Feb 07 03:24:29 PM PST 24
Finished Feb 07 03:42:46 PM PST 24
Peak memory 228820 kb
Host smart-8eb62cdb-2b33-480d-a2cf-19bb63293d59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247543302 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3247543302
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all_with_rand_reset.1359694025
Short name T721
Test name
Test status
Simulation time 970060469 ps
CPU time 14.3 seconds
Started Feb 07 03:24:37 PM PST 24
Finished Feb 07 03:24:52 PM PST 24
Peak memory 214444 kb
Host smart-ce9399f6-efe0-44b6-9280-ab1e6264d4bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359694025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all_with_rand_reset.1359694025
Directory /workspace/2.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.4015771457
Short name T488
Test name
Test status
Simulation time 42655458 ps
CPU time 0.89 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:24:34 PM PST 24
Peak memory 196672 kb
Host smart-6d49cd4f-0bb3-439d-98ac-69d2109a216d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015771457 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.4015771457
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.4156859293
Short name T33
Test name
Test status
Simulation time 70243515099 ps
CPU time 419.01 seconds
Started Feb 07 03:24:29 PM PST 24
Finished Feb 07 03:31:29 PM PST 24
Peak memory 199080 kb
Host smart-aa90bccd-aacd-4936-a6da-89566b63ecb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156859293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.4156859293
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.558694332
Short name T345
Test name
Test status
Simulation time 2687490237 ps
CPU time 23.29 seconds
Started Feb 07 03:24:34 PM PST 24
Finished Feb 07 03:24:58 PM PST 24
Peak memory 199016 kb
Host smart-834ad411-1847-483d-93bc-d268e8e5ec18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558694332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.558694332
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.301179193
Short name T834
Test name
Test status
Simulation time 24964597 ps
CPU time 0.57 seconds
Started Feb 07 03:27:21 PM PST 24
Finished Feb 07 03:27:25 PM PST 24
Peak memory 193472 kb
Host smart-832c3106-6750-4c2e-a1a1-adfc891adde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301179193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.301179193
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.751393876
Short name T231
Test name
Test status
Simulation time 1986456023 ps
CPU time 29.98 seconds
Started Feb 07 03:27:14 PM PST 24
Finished Feb 07 03:27:44 PM PST 24
Peak memory 215208 kb
Host smart-538b2a6d-497f-4597-8729-0453cbd287b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751393876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.751393876
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1196811480
Short name T323
Test name
Test status
Simulation time 2387959135 ps
CPU time 47.52 seconds
Started Feb 07 03:27:26 PM PST 24
Finished Feb 07 03:28:15 PM PST 24
Peak memory 199032 kb
Host smart-e1edae20-9c29-423a-9868-5e1e464acdbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196811480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1196811480
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.4288348433
Short name T440
Test name
Test status
Simulation time 2393163166 ps
CPU time 129.56 seconds
Started Feb 07 03:27:20 PM PST 24
Finished Feb 07 03:29:34 PM PST 24
Peak memory 199096 kb
Host smart-90131be5-b996-4bff-bb30-49351b16acbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4288348433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.4288348433
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.4022970781
Short name T601
Test name
Test status
Simulation time 9206466513 ps
CPU time 38.78 seconds
Started Feb 07 03:27:25 PM PST 24
Finished Feb 07 03:28:05 PM PST 24
Peak memory 199080 kb
Host smart-708e117a-8ee4-4e3f-b616-7b1584142a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022970781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.4022970781
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.748473315
Short name T474
Test name
Test status
Simulation time 11281241557 ps
CPU time 22.29 seconds
Started Feb 07 03:27:13 PM PST 24
Finished Feb 07 03:27:36 PM PST 24
Peak memory 199080 kb
Host smart-b7cf312b-12bd-4e2c-ab92-9aba402984fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748473315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.748473315
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.738351587
Short name T709
Test name
Test status
Simulation time 540021353 ps
CPU time 3.76 seconds
Started Feb 07 03:27:12 PM PST 24
Finished Feb 07 03:27:17 PM PST 24
Peak memory 199064 kb
Host smart-6ead11e2-c036-4efb-92e4-7229b5f21ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738351587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.738351587
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3892164621
Short name T482
Test name
Test status
Simulation time 24912031177 ps
CPU time 85.73 seconds
Started Feb 07 03:27:26 PM PST 24
Finished Feb 07 03:28:55 PM PST 24
Peak memory 199128 kb
Host smart-a1696c20-1609-4b90-9ae9-7fc3c473be3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892164621 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3892164621
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.2516207292
Short name T97
Test name
Test status
Simulation time 465805915857 ps
CPU time 3201.58 seconds
Started Feb 07 03:27:29 PM PST 24
Finished Feb 07 04:20:52 PM PST 24
Peak memory 231988 kb
Host smart-11ade940-9456-4907-bc30-aeb1481d21ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2516207292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.2516207292
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3211791695
Short name T770
Test name
Test status
Simulation time 241640535 ps
CPU time 1.14 seconds
Started Feb 07 03:27:22 PM PST 24
Finished Feb 07 03:27:26 PM PST 24
Peak memory 197192 kb
Host smart-d4319bde-dcbc-4352-a6dd-dba43a79a201
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211791695 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3211791695
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.2056759669
Short name T37
Test name
Test status
Simulation time 7934827437 ps
CPU time 408.04 seconds
Started Feb 07 03:27:22 PM PST 24
Finished Feb 07 03:34:13 PM PST 24
Peak memory 199108 kb
Host smart-731589d0-77c7-496a-92ee-ce80642c50bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056759669 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.2056759669
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2821141806
Short name T766
Test name
Test status
Simulation time 3210570661 ps
CPU time 20.5 seconds
Started Feb 07 03:27:21 PM PST 24
Finished Feb 07 03:27:45 PM PST 24
Peak memory 199152 kb
Host smart-1d2ed3de-3493-429f-a44a-c55ce1cd1f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821141806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2821141806
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4256148737
Short name T693
Test name
Test status
Simulation time 49390969 ps
CPU time 0.6 seconds
Started Feb 07 03:27:33 PM PST 24
Finished Feb 07 03:27:34 PM PST 24
Peak memory 193504 kb
Host smart-844773a5-16d1-40f2-8997-5f07a788fbdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256148737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4256148737
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1851994553
Short name T561
Test name
Test status
Simulation time 3244550238 ps
CPU time 27.61 seconds
Started Feb 07 03:27:27 PM PST 24
Finished Feb 07 03:27:57 PM PST 24
Peak memory 214712 kb
Host smart-386bee7f-893a-4192-8891-6e28ea7d4cc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851994553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1851994553
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4185871901
Short name T759
Test name
Test status
Simulation time 968349267 ps
CPU time 44.85 seconds
Started Feb 07 03:27:28 PM PST 24
Finished Feb 07 03:28:14 PM PST 24
Peak memory 198920 kb
Host smart-70a104ac-2c05-428a-a757-ef58f1128e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185871901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4185871901
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.661578200
Short name T215
Test name
Test status
Simulation time 392386702 ps
CPU time 18.7 seconds
Started Feb 07 03:27:29 PM PST 24
Finished Feb 07 03:27:48 PM PST 24
Peak memory 198908 kb
Host smart-aefda11b-c8e3-48f6-a120-6cbbd3813c04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661578200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.661578200
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2600442194
Short name T396
Test name
Test status
Simulation time 20088199461 ps
CPU time 209.83 seconds
Started Feb 07 03:27:24 PM PST 24
Finished Feb 07 03:30:55 PM PST 24
Peak memory 198896 kb
Host smart-6f260f5b-84f0-4f99-a6f4-cfa1d00ea166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600442194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2600442194
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.3238104499
Short name T436
Test name
Test status
Simulation time 845273283 ps
CPU time 45.76 seconds
Started Feb 07 03:27:26 PM PST 24
Finished Feb 07 03:28:14 PM PST 24
Peak memory 199000 kb
Host smart-7a74a080-6fe7-45a5-a709-67d70859e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238104499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.3238104499
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.1328778651
Short name T540
Test name
Test status
Simulation time 1105095404 ps
CPU time 3.37 seconds
Started Feb 07 03:27:25 PM PST 24
Finished Feb 07 03:27:29 PM PST 24
Peak memory 198992 kb
Host smart-624c1add-bc8b-4a10-9eb4-5249053d21e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328778651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.1328778651
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.2583951121
Short name T829
Test name
Test status
Simulation time 66265438923 ps
CPU time 1154.57 seconds
Started Feb 07 03:27:33 PM PST 24
Finished Feb 07 03:46:48 PM PST 24
Peak memory 231896 kb
Host smart-5aa3ff4c-1235-46d3-ac30-e23a20f868d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583951121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.2583951121
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_stress_all_with_rand_reset.2215647172
Short name T493
Test name
Test status
Simulation time 20057399937 ps
CPU time 294.46 seconds
Started Feb 07 03:27:33 PM PST 24
Finished Feb 07 03:32:28 PM PST 24
Peak memory 223796 kb
Host smart-b3570933-8aff-468a-b53f-b69c6ed63747
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2215647172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all_with_rand_reset.2215647172
Directory /workspace/21.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2197016331
Short name T333
Test name
Test status
Simulation time 116044847 ps
CPU time 1.1 seconds
Started Feb 07 03:27:26 PM PST 24
Finished Feb 07 03:27:29 PM PST 24
Peak memory 197460 kb
Host smart-f294d4ca-122d-46ad-979c-1c8fc6995236
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197016331 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2197016331
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.1810188371
Short name T827
Test name
Test status
Simulation time 11446031379 ps
CPU time 50.3 seconds
Started Feb 07 03:27:26 PM PST 24
Finished Feb 07 03:28:18 PM PST 24
Peak memory 199108 kb
Host smart-8e74ee3a-f9d3-46d7-8016-f98f6264b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810188371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.1810188371
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2635770973
Short name T135
Test name
Test status
Simulation time 882562237 ps
CPU time 29.45 seconds
Started Feb 07 03:27:39 PM PST 24
Finished Feb 07 03:28:09 PM PST 24
Peak memory 212196 kb
Host smart-0d975d50-9a93-416e-a0cd-c49ddfca2ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2635770973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2635770973
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.3765180731
Short name T276
Test name
Test status
Simulation time 2162787978 ps
CPU time 34.82 seconds
Started Feb 07 03:27:36 PM PST 24
Finished Feb 07 03:28:12 PM PST 24
Peak memory 199012 kb
Host smart-1ba8f198-5d54-4297-ac4b-e2d990bfc3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765180731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.3765180731
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2593795884
Short name T849
Test name
Test status
Simulation time 2693323869 ps
CPU time 59.03 seconds
Started Feb 07 03:27:43 PM PST 24
Finished Feb 07 03:28:42 PM PST 24
Peak memory 199136 kb
Host smart-42651919-f76b-4bbe-8da9-f380c06b71a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593795884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2593795884
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.292028563
Short name T582
Test name
Test status
Simulation time 9019205588 ps
CPU time 111.43 seconds
Started Feb 07 03:27:40 PM PST 24
Finished Feb 07 03:29:32 PM PST 24
Peak memory 199136 kb
Host smart-298ab7de-fed6-4572-a86f-816a538a8275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292028563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.292028563
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.681636608
Short name T297
Test name
Test status
Simulation time 52080589806 ps
CPU time 69.93 seconds
Started Feb 07 03:27:34 PM PST 24
Finished Feb 07 03:28:44 PM PST 24
Peak memory 199056 kb
Host smart-66c5e5bf-f6ed-4914-ab8b-1ccd2954ceab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681636608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.681636608
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1381593087
Short name T281
Test name
Test status
Simulation time 241006591 ps
CPU time 2.8 seconds
Started Feb 07 03:27:35 PM PST 24
Finished Feb 07 03:27:38 PM PST 24
Peak memory 199004 kb
Host smart-6981cef0-4438-4d96-a564-6bd9896b5503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381593087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1381593087
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3239220488
Short name T534
Test name
Test status
Simulation time 24874248871 ps
CPU time 1241.4 seconds
Started Feb 07 03:27:37 PM PST 24
Finished Feb 07 03:48:19 PM PST 24
Peak memory 246964 kb
Host smart-5608a139-36b4-45db-812b-6515e876eaf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239220488 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3239220488
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.626024422
Short name T535
Test name
Test status
Simulation time 485766752208 ps
CPU time 1240.16 seconds
Started Feb 07 03:27:42 PM PST 24
Finished Feb 07 03:48:23 PM PST 24
Peak memory 241204 kb
Host smart-ca2b9e7f-6c95-47ac-bef1-a86b44cdb120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=626024422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.626024422
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1305192348
Short name T339
Test name
Test status
Simulation time 250811216 ps
CPU time 1.21 seconds
Started Feb 07 03:27:36 PM PST 24
Finished Feb 07 03:27:38 PM PST 24
Peak memory 196664 kb
Host smart-dfba7188-f626-444c-a689-cde7290189f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305192348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.1305192348
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.2902495656
Short name T516
Test name
Test status
Simulation time 7529709927 ps
CPU time 393.91 seconds
Started Feb 07 03:27:39 PM PST 24
Finished Feb 07 03:34:14 PM PST 24
Peak memory 199088 kb
Host smart-1ee46c21-65dc-4dd5-a60e-68fbe7193f5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902495656 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.2902495656
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3020129999
Short name T2
Test name
Test status
Simulation time 4572374515 ps
CPU time 79.21 seconds
Started Feb 07 03:27:39 PM PST 24
Finished Feb 07 03:28:59 PM PST 24
Peak memory 199100 kb
Host smart-dfbfb55d-7b5d-49d0-9e4d-6e1744e4985c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020129999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3020129999
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3856972239
Short name T623
Test name
Test status
Simulation time 38224735 ps
CPU time 0.59 seconds
Started Feb 07 03:27:55 PM PST 24
Finished Feb 07 03:27:56 PM PST 24
Peak memory 194488 kb
Host smart-7bd6af8d-ecb3-4647-8c97-a0363ecb0569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856972239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3856972239
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3464783260
Short name T373
Test name
Test status
Simulation time 2507438548 ps
CPU time 24.79 seconds
Started Feb 07 03:27:45 PM PST 24
Finished Feb 07 03:28:11 PM PST 24
Peak memory 239960 kb
Host smart-da290572-840f-4e73-bb1e-996bfdfc187e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3464783260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3464783260
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1394955761
Short name T796
Test name
Test status
Simulation time 8415617137 ps
CPU time 40.97 seconds
Started Feb 07 03:27:51 PM PST 24
Finished Feb 07 03:28:34 PM PST 24
Peak memory 199124 kb
Host smart-3a6f8185-fe1c-484d-b7ed-a97db358775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394955761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1394955761
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.767110148
Short name T476
Test name
Test status
Simulation time 3872334988 ps
CPU time 50.56 seconds
Started Feb 07 03:27:47 PM PST 24
Finished Feb 07 03:28:39 PM PST 24
Peak memory 199120 kb
Host smart-91ae0dbd-35bb-4692-92f0-6c72982ded79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=767110148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.767110148
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.310591099
Short name T209
Test name
Test status
Simulation time 3811768282 ps
CPU time 51.77 seconds
Started Feb 07 03:27:51 PM PST 24
Finished Feb 07 03:28:44 PM PST 24
Peak memory 199108 kb
Host smart-aa376f08-1448-409e-afb5-d320ce542de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310591099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.310591099
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3254333960
Short name T364
Test name
Test status
Simulation time 3567713453 ps
CPU time 63.71 seconds
Started Feb 07 03:27:48 PM PST 24
Finished Feb 07 03:28:52 PM PST 24
Peak memory 199092 kb
Host smart-858bb566-5370-46f2-a336-4878222b5c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254333960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3254333960
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2850568602
Short name T751
Test name
Test status
Simulation time 181371168 ps
CPU time 2.64 seconds
Started Feb 07 03:27:43 PM PST 24
Finished Feb 07 03:27:46 PM PST 24
Peak memory 198852 kb
Host smart-71b54046-d2b2-410d-91ec-e4a19de2b770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850568602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2850568602
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2168466872
Short name T518
Test name
Test status
Simulation time 292533147009 ps
CPU time 677.91 seconds
Started Feb 07 03:27:59 PM PST 24
Finished Feb 07 03:39:18 PM PST 24
Peak memory 238640 kb
Host smart-f6d9a098-db46-461b-b095-3064e27f02b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168466872 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2168466872
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_stress_all_with_rand_reset.248355501
Short name T257
Test name
Test status
Simulation time 53688431385 ps
CPU time 780.46 seconds
Started Feb 07 03:27:50 PM PST 24
Finished Feb 07 03:40:53 PM PST 24
Peak memory 227784 kb
Host smart-8508e91d-6287-404d-a616-e66397e1912f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248355501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all_with_rand_reset.248355501
Directory /workspace/23.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.447749629
Short name T434
Test name
Test status
Simulation time 82031638 ps
CPU time 0.94 seconds
Started Feb 07 03:27:52 PM PST 24
Finished Feb 07 03:27:54 PM PST 24
Peak memory 196096 kb
Host smart-de12c5b3-e5a9-4fd8-a286-cfbbc31148cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447749629 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.447749629
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3196284120
Short name T830
Test name
Test status
Simulation time 7869990957 ps
CPU time 410.29 seconds
Started Feb 07 03:27:54 PM PST 24
Finished Feb 07 03:34:46 PM PST 24
Peak memory 199116 kb
Host smart-4094b89c-e761-4302-8cc7-75830b884601
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196284120 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.3196284120
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3282677268
Short name T571
Test name
Test status
Simulation time 21320613752 ps
CPU time 60.13 seconds
Started Feb 07 03:28:01 PM PST 24
Finished Feb 07 03:29:01 PM PST 24
Peak memory 199128 kb
Host smart-ee826290-b9ed-47f2-b3fc-0ac5fef2db96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282677268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3282677268
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2691696304
Short name T284
Test name
Test status
Simulation time 12410356 ps
CPU time 0.57 seconds
Started Feb 07 03:28:04 PM PST 24
Finished Feb 07 03:28:05 PM PST 24
Peak memory 193432 kb
Host smart-60a090ad-288d-46e2-b5ec-ae3fdf0d4162
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691696304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2691696304
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2422006857
Short name T288
Test name
Test status
Simulation time 679088153 ps
CPU time 5.37 seconds
Started Feb 07 03:28:02 PM PST 24
Finished Feb 07 03:28:08 PM PST 24
Peak memory 199028 kb
Host smart-6c8cebc8-1c11-4ca7-a64c-90ba1d1fac39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422006857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2422006857
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1803761007
Short name T332
Test name
Test status
Simulation time 15392524840 ps
CPU time 27.42 seconds
Started Feb 07 03:28:01 PM PST 24
Finished Feb 07 03:28:29 PM PST 24
Peak memory 199088 kb
Host smart-3cc5bc8f-b1a9-443f-a98a-11aec2a285d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803761007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1803761007
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2893643345
Short name T386
Test name
Test status
Simulation time 1179636456 ps
CPU time 57.13 seconds
Started Feb 07 03:28:01 PM PST 24
Finished Feb 07 03:28:58 PM PST 24
Peak memory 199112 kb
Host smart-de9e3907-8a2c-4a9b-9ab0-7ef3a9cba71d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893643345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2893643345
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.380493382
Short name T377
Test name
Test status
Simulation time 48451159688 ps
CPU time 134.53 seconds
Started Feb 07 03:28:05 PM PST 24
Finished Feb 07 03:30:20 PM PST 24
Peak memory 199124 kb
Host smart-773de7d9-29cf-45bb-b93d-e438313359c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380493382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.380493382
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.633344995
Short name T394
Test name
Test status
Simulation time 228748602 ps
CPU time 11.67 seconds
Started Feb 07 03:28:04 PM PST 24
Finished Feb 07 03:28:16 PM PST 24
Peak memory 198976 kb
Host smart-7ffb8546-b4c8-40a3-a457-dc199f27e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633344995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.633344995
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2040642033
Short name T320
Test name
Test status
Simulation time 66746954 ps
CPU time 0.9 seconds
Started Feb 07 03:28:01 PM PST 24
Finished Feb 07 03:28:02 PM PST 24
Peak memory 196016 kb
Host smart-a3ca30c1-fd14-4a2e-8bca-5e0a66cf126e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040642033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2040642033
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3378320135
Short name T385
Test name
Test status
Simulation time 54679596148 ps
CPU time 648.16 seconds
Started Feb 07 03:28:04 PM PST 24
Finished Feb 07 03:38:52 PM PST 24
Peak memory 225564 kb
Host smart-29fcc3f4-1a61-421b-8d4c-02739c01a7ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378320135 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3378320135
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all_with_rand_reset.2617494130
Short name T520
Test name
Test status
Simulation time 86346595330 ps
CPU time 709.2 seconds
Started Feb 07 03:28:05 PM PST 24
Finished Feb 07 03:39:55 PM PST 24
Peak memory 210592 kb
Host smart-443a860f-aa78-4081-85e7-b5c17d207c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617494130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all_with_rand_reset.2617494130
Directory /workspace/24.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3067254364
Short name T783
Test name
Test status
Simulation time 68162653 ps
CPU time 1.14 seconds
Started Feb 07 03:28:04 PM PST 24
Finished Feb 07 03:28:06 PM PST 24
Peak memory 197252 kb
Host smart-6e4811c7-3068-4d88-8b1b-559ee2ac131b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067254364 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3067254364
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2668083691
Short name T366
Test name
Test status
Simulation time 26336498541 ps
CPU time 437.4 seconds
Started Feb 07 03:28:01 PM PST 24
Finished Feb 07 03:35:19 PM PST 24
Peak memory 199124 kb
Host smart-6a61c031-18e8-42a8-9a6d-cefafe52f213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668083691 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2668083691
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.978264879
Short name T592
Test name
Test status
Simulation time 10600283169 ps
CPU time 35.72 seconds
Started Feb 07 03:28:04 PM PST 24
Finished Feb 07 03:28:40 PM PST 24
Peak memory 198896 kb
Host smart-b8d6a651-770b-4e84-8aca-57215ab3d501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978264879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.978264879
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2489644484
Short name T515
Test name
Test status
Simulation time 12637664 ps
CPU time 0.59 seconds
Started Feb 07 03:28:11 PM PST 24
Finished Feb 07 03:28:12 PM PST 24
Peak memory 193444 kb
Host smart-03128ed1-f862-437f-bb89-8f5ee3a9db08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489644484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2489644484
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.3028143174
Short name T426
Test name
Test status
Simulation time 1068984997 ps
CPU time 34.68 seconds
Started Feb 07 03:28:08 PM PST 24
Finished Feb 07 03:28:43 PM PST 24
Peak memory 207236 kb
Host smart-167e4e6d-b5ba-470c-80d7-bf3d13164ccf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3028143174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.3028143174
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3484131574
Short name T353
Test name
Test status
Simulation time 819561917 ps
CPU time 37.75 seconds
Started Feb 07 03:28:08 PM PST 24
Finished Feb 07 03:28:46 PM PST 24
Peak memory 199060 kb
Host smart-de13eb5f-9d4f-4bbf-aa4d-43398bd8dc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484131574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3484131574
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.510389494
Short name T309
Test name
Test status
Simulation time 4840531630 ps
CPU time 137.28 seconds
Started Feb 07 03:28:09 PM PST 24
Finished Feb 07 03:30:27 PM PST 24
Peak memory 199088 kb
Host smart-cc42d495-f52a-4e59-9aab-896e763c21eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510389494 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.510389494
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.101212910
Short name T767
Test name
Test status
Simulation time 11195980032 ps
CPU time 139.08 seconds
Started Feb 07 03:28:10 PM PST 24
Finished Feb 07 03:30:29 PM PST 24
Peak memory 199080 kb
Host smart-a25e32b3-7b32-429d-837b-dab900b4a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101212910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.101212910
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1090633892
Short name T125
Test name
Test status
Simulation time 7140444079 ps
CPU time 102.91 seconds
Started Feb 07 03:28:06 PM PST 24
Finished Feb 07 03:29:49 PM PST 24
Peak memory 199064 kb
Host smart-11508663-5698-4f20-bf9d-fa8fc863a2b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090633892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1090633892
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2028867562
Short name T845
Test name
Test status
Simulation time 534637272 ps
CPU time 3.31 seconds
Started Feb 07 03:28:03 PM PST 24
Finished Feb 07 03:28:06 PM PST 24
Peak memory 198872 kb
Host smart-1bc8894c-7bf7-4828-82b9-4dee8653c2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028867562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2028867562
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3526689304
Short name T291
Test name
Test status
Simulation time 77930216547 ps
CPU time 1253.36 seconds
Started Feb 07 03:28:10 PM PST 24
Finished Feb 07 03:49:04 PM PST 24
Peak memory 199080 kb
Host smart-b8b267f5-64f3-4eb5-969a-1287b7ae84f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526689304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3526689304
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2017786353
Short name T107
Test name
Test status
Simulation time 200648703651 ps
CPU time 1857.2 seconds
Started Feb 07 03:28:10 PM PST 24
Finished Feb 07 03:59:08 PM PST 24
Peak memory 251344 kb
Host smart-0162c7fc-f50b-42e7-b899-ee043c9c50d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017786353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.2017786353
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.79469883
Short name T489
Test name
Test status
Simulation time 45862531 ps
CPU time 0.92 seconds
Started Feb 07 03:28:13 PM PST 24
Finished Feb 07 03:28:14 PM PST 24
Peak memory 196176 kb
Host smart-ace65004-4f41-47ed-9925-284bf410af76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79469883 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_hmac_vectors.79469883
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.2689498127
Short name T522
Test name
Test status
Simulation time 119155235485 ps
CPU time 509.46 seconds
Started Feb 07 03:28:13 PM PST 24
Finished Feb 07 03:36:44 PM PST 24
Peak memory 199144 kb
Host smart-7b0d9949-5616-4299-baee-51486e9b80ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689498127 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.2689498127
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2119605151
Short name T144
Test name
Test status
Simulation time 18538144018 ps
CPU time 75.05 seconds
Started Feb 07 03:28:12 PM PST 24
Finished Feb 07 03:29:27 PM PST 24
Peak memory 199096 kb
Host smart-1b9f41c2-22ae-409e-8f78-e3026f8754fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119605151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2119605151
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3212857299
Short name T779
Test name
Test status
Simulation time 148477803 ps
CPU time 0.58 seconds
Started Feb 07 03:28:21 PM PST 24
Finished Feb 07 03:28:22 PM PST 24
Peak memory 193524 kb
Host smart-4fe13385-4d2f-47dd-9f15-03e11ce5aefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212857299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3212857299
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.4023343679
Short name T423
Test name
Test status
Simulation time 3528974100 ps
CPU time 52.14 seconds
Started Feb 07 03:28:17 PM PST 24
Finished Feb 07 03:29:10 PM PST 24
Peak memory 239940 kb
Host smart-936db9f7-d014-432c-8ed0-bb60e7fb9b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023343679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.4023343679
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.982122677
Short name T598
Test name
Test status
Simulation time 4459648202 ps
CPU time 30.01 seconds
Started Feb 07 03:28:19 PM PST 24
Finished Feb 07 03:28:49 PM PST 24
Peak memory 199148 kb
Host smart-3f57fbe7-a152-4e66-8fab-559906a880bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982122677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.982122677
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3268538902
Short name T325
Test name
Test status
Simulation time 57305959 ps
CPU time 0.75 seconds
Started Feb 07 03:28:16 PM PST 24
Finished Feb 07 03:28:17 PM PST 24
Peak memory 194528 kb
Host smart-ecfc1705-e04a-44be-b49b-3d9868ab286f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3268538902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3268538902
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1278304898
Short name T344
Test name
Test status
Simulation time 2922307537 ps
CPU time 153.54 seconds
Started Feb 07 03:28:14 PM PST 24
Finished Feb 07 03:30:48 PM PST 24
Peak memory 199084 kb
Host smart-634b59bf-0c57-4acd-8a4a-99011b3fcc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278304898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1278304898
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.2655799999
Short name T307
Test name
Test status
Simulation time 23713415016 ps
CPU time 115.46 seconds
Started Feb 07 03:28:15 PM PST 24
Finished Feb 07 03:30:11 PM PST 24
Peak memory 199080 kb
Host smart-8a36ca27-4b1c-46f6-baa2-148bec5dbf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655799999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.2655799999
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.591042671
Short name T506
Test name
Test status
Simulation time 563847289 ps
CPU time 2.14 seconds
Started Feb 07 03:28:15 PM PST 24
Finished Feb 07 03:28:17 PM PST 24
Peak memory 198460 kb
Host smart-35f8ab42-e700-45c5-ac9a-586d0a294e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591042671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.591042671
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3405654972
Short name T703
Test name
Test status
Simulation time 121510474656 ps
CPU time 309.6 seconds
Started Feb 07 03:28:22 PM PST 24
Finished Feb 07 03:33:32 PM PST 24
Peak memory 199124 kb
Host smart-0e9e5c48-7d33-4898-9c2f-c4125a407f8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405654972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3405654972
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_stress_all_with_rand_reset.1059163724
Short name T663
Test name
Test status
Simulation time 220230819349 ps
CPU time 962.38 seconds
Started Feb 07 03:28:22 PM PST 24
Finished Feb 07 03:44:25 PM PST 24
Peak memory 240128 kb
Host smart-55995855-346d-43e7-a04d-71f31c18bc36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059163724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all_with_rand_reset.1059163724
Directory /workspace/26.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.53385789
Short name T213
Test name
Test status
Simulation time 124733029 ps
CPU time 1.16 seconds
Started Feb 07 03:28:15 PM PST 24
Finished Feb 07 03:28:16 PM PST 24
Peak memory 198500 kb
Host smart-acd6c450-3b0e-42e4-82f9-8e7036d98139
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53385789 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_hmac_vectors.53385789
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.1213797637
Short name T327
Test name
Test status
Simulation time 53743365397 ps
CPU time 392.32 seconds
Started Feb 07 03:28:17 PM PST 24
Finished Feb 07 03:34:50 PM PST 24
Peak memory 198860 kb
Host smart-5eb0daa4-c573-4d24-8e7d-94974606ba2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213797637 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.1213797637
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.2960489373
Short name T292
Test name
Test status
Simulation time 1660368984 ps
CPU time 64.28 seconds
Started Feb 07 03:28:14 PM PST 24
Finished Feb 07 03:29:19 PM PST 24
Peak memory 199128 kb
Host smart-d474c07a-e221-4e16-bbc6-02489beb09ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960489373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.2960489373
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4125373533
Short name T586
Test name
Test status
Simulation time 38463952 ps
CPU time 0.59 seconds
Started Feb 07 03:28:30 PM PST 24
Finished Feb 07 03:28:31 PM PST 24
Peak memory 193492 kb
Host smart-2762b043-2288-4b7c-b081-ec8586b1705f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125373533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4125373533
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3871406695
Short name T550
Test name
Test status
Simulation time 2503673586 ps
CPU time 20.65 seconds
Started Feb 07 03:28:23 PM PST 24
Finished Feb 07 03:28:44 PM PST 24
Peak memory 218644 kb
Host smart-737c8d98-d750-41a9-aeda-b47ac2c30e87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3871406695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3871406695
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.48727151
Short name T329
Test name
Test status
Simulation time 308533789 ps
CPU time 14.08 seconds
Started Feb 07 03:28:30 PM PST 24
Finished Feb 07 03:28:44 PM PST 24
Peak memory 199080 kb
Host smart-9daa9e04-b8f9-42fd-9e36-c2b6a181541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48727151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.48727151
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2617830858
Short name T541
Test name
Test status
Simulation time 1403345826 ps
CPU time 34.6 seconds
Started Feb 07 03:28:24 PM PST 24
Finished Feb 07 03:28:59 PM PST 24
Peak memory 198980 kb
Host smart-d7c398e6-71d8-477b-aa09-01f318df54ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2617830858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2617830858
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1512338806
Short name T714
Test name
Test status
Simulation time 24914391036 ps
CPU time 142.55 seconds
Started Feb 07 03:28:34 PM PST 24
Finished Feb 07 03:30:57 PM PST 24
Peak memory 199076 kb
Host smart-59982049-9dd1-4e5a-a322-982ca7486309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512338806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1512338806
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3596523133
Short name T665
Test name
Test status
Simulation time 4986768895 ps
CPU time 66.1 seconds
Started Feb 07 03:28:24 PM PST 24
Finished Feb 07 03:29:31 PM PST 24
Peak memory 199072 kb
Host smart-074e9a7a-85df-4095-af20-c8c3053775a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596523133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3596523133
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.4145012824
Short name T513
Test name
Test status
Simulation time 85191655 ps
CPU time 0.84 seconds
Started Feb 07 03:28:23 PM PST 24
Finished Feb 07 03:28:24 PM PST 24
Peak memory 195880 kb
Host smart-6a2deac9-bbcb-44f0-878c-177feb047771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145012824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.4145012824
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1918769638
Short name T743
Test name
Test status
Simulation time 67553086530 ps
CPU time 1157.95 seconds
Started Feb 07 03:28:30 PM PST 24
Finished Feb 07 03:47:48 PM PST 24
Peak memory 234536 kb
Host smart-de122690-ec0b-46d0-8775-5df1b5d388d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918769638 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1918769638
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_stress_all_with_rand_reset.1314658913
Short name T662
Test name
Test status
Simulation time 31241014385 ps
CPU time 1283.48 seconds
Started Feb 07 03:28:33 PM PST 24
Finished Feb 07 03:49:57 PM PST 24
Peak memory 240180 kb
Host smart-0c1d84ee-3cab-405e-80e6-78e9aa27d5a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314658913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all_with_rand_reset.1314658913
Directory /workspace/27.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1317481009
Short name T41
Test name
Test status
Simulation time 85415376 ps
CPU time 0.96 seconds
Started Feb 07 03:28:33 PM PST 24
Finished Feb 07 03:28:34 PM PST 24
Peak memory 196040 kb
Host smart-fe73a3d5-f786-4f72-b77b-edbe18025b0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317481009 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1317481009
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1405407154
Short name T701
Test name
Test status
Simulation time 42549722401 ps
CPU time 487.09 seconds
Started Feb 07 03:28:31 PM PST 24
Finished Feb 07 03:36:39 PM PST 24
Peak memory 199112 kb
Host smart-557c6814-cfaf-4fca-88e8-c15334292126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405407154 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1405407154
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3363563677
Short name T637
Test name
Test status
Simulation time 7362325338 ps
CPU time 69.2 seconds
Started Feb 07 03:28:30 PM PST 24
Finished Feb 07 03:29:40 PM PST 24
Peak memory 199080 kb
Host smart-e05ae283-9e8e-4f25-93bf-fb601f389d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363563677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3363563677
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1075885230
Short name T50
Test name
Test status
Simulation time 12677328 ps
CPU time 0.54 seconds
Started Feb 07 03:28:45 PM PST 24
Finished Feb 07 03:28:46 PM PST 24
Peak memory 193460 kb
Host smart-6bf855b3-fb60-4048-a7c5-4e3626676a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075885230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1075885230
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2956443553
Short name T605
Test name
Test status
Simulation time 4261932204 ps
CPU time 38.75 seconds
Started Feb 07 03:28:42 PM PST 24
Finished Feb 07 03:29:21 PM PST 24
Peak memory 231860 kb
Host smart-a67c753c-63b7-4810-90b7-e28e2e533ed0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2956443553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2956443553
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.528939884
Short name T816
Test name
Test status
Simulation time 2146234737 ps
CPU time 6.93 seconds
Started Feb 07 03:28:43 PM PST 24
Finished Feb 07 03:28:50 PM PST 24
Peak memory 198984 kb
Host smart-98321bc0-cde8-4e58-b0c1-adf9f9f7dcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528939884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.528939884
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.442607215
Short name T392
Test name
Test status
Simulation time 2329344433 ps
CPU time 32.18 seconds
Started Feb 07 03:28:40 PM PST 24
Finished Feb 07 03:29:13 PM PST 24
Peak memory 198876 kb
Host smart-f9aacf9c-8085-4bfb-8a4c-578900948d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=442607215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.442607215
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2518250218
Short name T584
Test name
Test status
Simulation time 70043398908 ps
CPU time 203.01 seconds
Started Feb 07 03:28:41 PM PST 24
Finished Feb 07 03:32:05 PM PST 24
Peak memory 199156 kb
Host smart-029c4647-91aa-4124-aa25-5f2e94b53b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518250218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2518250218
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1626849481
Short name T793
Test name
Test status
Simulation time 21310850468 ps
CPU time 101.64 seconds
Started Feb 07 03:28:41 PM PST 24
Finished Feb 07 03:30:23 PM PST 24
Peak memory 199080 kb
Host smart-befc6c39-f9fb-475b-8a8b-e1724330f89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626849481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1626849481
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.249793191
Short name T683
Test name
Test status
Simulation time 30680576 ps
CPU time 0.62 seconds
Started Feb 07 03:28:35 PM PST 24
Finished Feb 07 03:28:36 PM PST 24
Peak memory 193648 kb
Host smart-191ef73e-6f0d-48de-9dbc-51dd8d4d6c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249793191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.249793191
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.703467859
Short name T367
Test name
Test status
Simulation time 39604970151 ps
CPU time 499.14 seconds
Started Feb 07 03:28:52 PM PST 24
Finished Feb 07 03:37:12 PM PST 24
Peak memory 215488 kb
Host smart-ac3c197e-8e32-4408-aaaf-b6ff92fa734e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703467859 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.703467859
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_stress_all_with_rand_reset.2430078387
Short name T656
Test name
Test status
Simulation time 240097011215 ps
CPU time 1730.79 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:57:42 PM PST 24
Peak memory 215528 kb
Host smart-24f9e762-ef8b-44aa-a08a-4fa290a70df0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430078387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all_with_rand_reset.2430078387
Directory /workspace/28.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2115713336
Short name T379
Test name
Test status
Simulation time 149151572 ps
CPU time 0.9 seconds
Started Feb 07 03:28:48 PM PST 24
Finished Feb 07 03:28:49 PM PST 24
Peak memory 196100 kb
Host smart-2509ecbc-d50e-4205-8199-f0112a6fef5f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115713336 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2115713336
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1839270628
Short name T472
Test name
Test status
Simulation time 38532568139 ps
CPU time 473.29 seconds
Started Feb 07 03:28:46 PM PST 24
Finished Feb 07 03:36:40 PM PST 24
Peak memory 199168 kb
Host smart-8d40e64d-8d9d-4b40-b6c1-2b07252505b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839270628 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.1839270628
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.3569063361
Short name T336
Test name
Test status
Simulation time 1545117161 ps
CPU time 17.2 seconds
Started Feb 07 03:28:43 PM PST 24
Finished Feb 07 03:29:01 PM PST 24
Peak memory 199040 kb
Host smart-dd49e24d-8388-43d6-a6ce-45578694f806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569063361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.3569063361
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2348345502
Short name T814
Test name
Test status
Simulation time 11987035 ps
CPU time 0.57 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:28:51 PM PST 24
Peak memory 193232 kb
Host smart-8e63f852-c442-49a4-86e8-d0050eafe964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348345502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2348345502
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.4188213906
Short name T389
Test name
Test status
Simulation time 6797385568 ps
CPU time 56.4 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:29:46 PM PST 24
Peak memory 231856 kb
Host smart-8d091ddf-c83a-41ad-9004-0f6c049798e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188213906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.4188213906
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.1821472160
Short name T636
Test name
Test status
Simulation time 3728777356 ps
CPU time 41.15 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:29:35 PM PST 24
Peak memory 198916 kb
Host smart-261c9b8a-4d84-4f83-b140-4aa0062a45a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821472160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.1821472160
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2413357976
Short name T260
Test name
Test status
Simulation time 1885348501 ps
CPU time 23.42 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:29:14 PM PST 24
Peak memory 199036 kb
Host smart-34b927f0-201b-4afb-b75e-b0e976aabf41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2413357976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2413357976
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.801350913
Short name T454
Test name
Test status
Simulation time 6362175429 ps
CPU time 80.8 seconds
Started Feb 07 03:28:48 PM PST 24
Finished Feb 07 03:30:09 PM PST 24
Peak memory 199068 kb
Host smart-0ee58b2b-47c2-4bb8-ad4a-802a60694913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801350913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.801350913
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.4042044761
Short name T634
Test name
Test status
Simulation time 4780250260 ps
CPU time 17.16 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:29:07 PM PST 24
Peak memory 199028 kb
Host smart-2ae8f104-81cb-4e1a-9136-2ae4e8120a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042044761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.4042044761
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2790103879
Short name T803
Test name
Test status
Simulation time 341590703 ps
CPU time 3.56 seconds
Started Feb 07 03:28:48 PM PST 24
Finished Feb 07 03:28:52 PM PST 24
Peak memory 198960 kb
Host smart-8463f980-4bf8-49e7-bac7-364adb203823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790103879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2790103879
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.125247078
Short name T460
Test name
Test status
Simulation time 316782873387 ps
CPU time 1285.66 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:50:20 PM PST 24
Peak memory 223480 kb
Host smart-da722096-b6f1-48bc-ad24-2026b371c7f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125247078 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.125247078
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_stress_all_with_rand_reset.4185070218
Short name T338
Test name
Test status
Simulation time 78518001671 ps
CPU time 372.27 seconds
Started Feb 07 03:28:49 PM PST 24
Finished Feb 07 03:35:02 PM PST 24
Peak memory 238496 kb
Host smart-b0488131-f14d-4bff-a371-d73c48ec821c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185070218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all_with_rand_reset.4185070218
Directory /workspace/29.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.3526117660
Short name T414
Test name
Test status
Simulation time 29851019 ps
CPU time 0.91 seconds
Started Feb 07 03:28:47 PM PST 24
Finished Feb 07 03:28:49 PM PST 24
Peak memory 196760 kb
Host smart-58d8c04b-8c8d-44be-8597-ff0fbb5443a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526117660 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.3526117660
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3688399843
Short name T526
Test name
Test status
Simulation time 7877666134 ps
CPU time 384.7 seconds
Started Feb 07 03:28:49 PM PST 24
Finished Feb 07 03:35:14 PM PST 24
Peak memory 199004 kb
Host smart-a2dbfe85-7b65-4d73-99bd-70cedf1d683a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688399843 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3688399843
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3104730557
Short name T678
Test name
Test status
Simulation time 6692469279 ps
CPU time 40.32 seconds
Started Feb 07 03:28:50 PM PST 24
Finished Feb 07 03:29:30 PM PST 24
Peak memory 199108 kb
Host smart-46d46c41-b1c9-48c4-bcc3-d86ba3adeafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104730557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3104730557
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.1336189511
Short name T775
Test name
Test status
Simulation time 14096014 ps
CPU time 0.58 seconds
Started Feb 07 03:24:36 PM PST 24
Finished Feb 07 03:24:37 PM PST 24
Peak memory 193432 kb
Host smart-c1234069-379a-4fef-be0b-73e772822cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336189511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.1336189511
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3974059973
Short name T461
Test name
Test status
Simulation time 4663913511 ps
CPU time 53.82 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 03:25:25 PM PST 24
Peak memory 229188 kb
Host smart-2148e4d1-f5a2-478c-9488-999256c99cdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974059973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3974059973
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1745632070
Short name T641
Test name
Test status
Simulation time 1481733731 ps
CPU time 80.34 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:25:53 PM PST 24
Peak memory 199016 kb
Host smart-3eb22c1f-2fc3-477a-b28e-0de8e2dfb416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1745632070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1745632070
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.2822455101
Short name T413
Test name
Test status
Simulation time 18125170858 ps
CPU time 116.75 seconds
Started Feb 07 03:24:23 PM PST 24
Finished Feb 07 03:26:20 PM PST 24
Peak memory 199108 kb
Host smart-0508f633-4680-483a-bee4-9a1691aed90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822455101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2822455101
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3364946472
Short name T44
Test name
Test status
Simulation time 7961594206 ps
CPU time 54.15 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 03:25:26 PM PST 24
Peak memory 199052 kb
Host smart-f14f1425-1b2b-473e-a792-0018e8d16a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364946472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3364946472
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1937537252
Short name T55
Test name
Test status
Simulation time 219481867 ps
CPU time 0.98 seconds
Started Feb 07 03:24:26 PM PST 24
Finished Feb 07 03:24:27 PM PST 24
Peak memory 217376 kb
Host smart-12b74e7c-429a-491f-b7f9-fe3c20b44e46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937537252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1937537252
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.1580042485
Short name T411
Test name
Test status
Simulation time 23284929 ps
CPU time 0.8 seconds
Started Feb 07 03:24:30 PM PST 24
Finished Feb 07 03:24:31 PM PST 24
Peak memory 195980 kb
Host smart-b65bdf78-cc46-4194-a638-83ca96f516c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580042485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.1580042485
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2493502301
Short name T631
Test name
Test status
Simulation time 701396006080 ps
CPU time 2139.82 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 04:00:14 PM PST 24
Peak memory 225772 kb
Host smart-35c54e2e-5d79-41e0-ba9e-e2e4631b9217
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493502301 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2493502301
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_stress_all_with_rand_reset.893768112
Short name T100
Test name
Test status
Simulation time 65888654618 ps
CPU time 2542.66 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 04:06:55 PM PST 24
Peak memory 248324 kb
Host smart-cfcc2829-91b4-44be-8fad-4be12e931f92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893768112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all_with_rand_reset.893768112
Directory /workspace/3.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2343686680
Short name T706
Test name
Test status
Simulation time 29042597 ps
CPU time 0.87 seconds
Started Feb 07 03:24:22 PM PST 24
Finished Feb 07 03:24:24 PM PST 24
Peak memory 196780 kb
Host smart-e363c74c-2522-419d-b30b-d56ae37c735d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343686680 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2343686680
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1435398250
Short name T469
Test name
Test status
Simulation time 52990990933 ps
CPU time 446.53 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 03:31:58 PM PST 24
Peak memory 199168 kb
Host smart-d2349c9a-c4c8-430e-a24f-66eced2d9614
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435398250 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1435398250
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1085268100
Short name T729
Test name
Test status
Simulation time 883055074 ps
CPU time 11.22 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:24:44 PM PST 24
Peak memory 199028 kb
Host smart-380452cd-551d-4ee6-8f39-06310bb7e08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085268100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1085268100
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1571675923
Short name T510
Test name
Test status
Simulation time 17524431 ps
CPU time 0.55 seconds
Started Feb 07 03:29:00 PM PST 24
Finished Feb 07 03:29:04 PM PST 24
Peak memory 193248 kb
Host smart-b3542972-02e8-44b9-9e7a-1d25100efad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571675923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1571675923
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3432367355
Short name T702
Test name
Test status
Simulation time 656924279 ps
CPU time 10.88 seconds
Started Feb 07 03:28:49 PM PST 24
Finished Feb 07 03:29:00 PM PST 24
Peak memory 199044 kb
Host smart-1f22f748-4cbf-47e8-8d7d-4dd481abb050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432367355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3432367355
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3975935191
Short name T335
Test name
Test status
Simulation time 2676549115 ps
CPU time 31.43 seconds
Started Feb 07 03:28:53 PM PST 24
Finished Feb 07 03:29:24 PM PST 24
Peak memory 199072 kb
Host smart-7382975c-c610-49c2-bc2d-c5c59e4f47ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975935191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3975935191
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2595791210
Short name T399
Test name
Test status
Simulation time 393349804 ps
CPU time 21.04 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:29:16 PM PST 24
Peak memory 199048 kb
Host smart-e3ff7012-0d74-488a-9282-0989e168296b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2595791210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2595791210
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3395190769
Short name T801
Test name
Test status
Simulation time 10752512257 ps
CPU time 89.89 seconds
Started Feb 07 03:28:53 PM PST 24
Finished Feb 07 03:30:23 PM PST 24
Peak memory 199036 kb
Host smart-8dd920d6-c550-4b9f-ba0e-cde14426c23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395190769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3395190769
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.182888016
Short name T351
Test name
Test status
Simulation time 9467269088 ps
CPU time 14.11 seconds
Started Feb 07 03:28:49 PM PST 24
Finished Feb 07 03:29:03 PM PST 24
Peak memory 199124 kb
Host smart-3c0fb760-b2eb-4be3-aa1f-72e92ef47ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182888016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.182888016
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.496196926
Short name T650
Test name
Test status
Simulation time 641876129 ps
CPU time 2.11 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:28:56 PM PST 24
Peak memory 198848 kb
Host smart-b7c372ad-d90d-48b9-9c27-935cf7cce60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496196926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.496196926
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2075468266
Short name T765
Test name
Test status
Simulation time 117870429147 ps
CPU time 1497.17 seconds
Started Feb 07 03:28:53 PM PST 24
Finished Feb 07 03:53:51 PM PST 24
Peak memory 231924 kb
Host smart-300aac88-0279-4c45-9259-bc386861c7e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075468266 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2075468266
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_stress_all_with_rand_reset.3599926776
Short name T718
Test name
Test status
Simulation time 87231565237 ps
CPU time 437.48 seconds
Started Feb 07 03:28:58 PM PST 24
Finished Feb 07 03:36:16 PM PST 24
Peak memory 207360 kb
Host smart-46d91b4c-6915-46d0-bbaf-ca0a541b5eff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599926776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all_with_rand_reset.3599926776
Directory /workspace/30.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1309736169
Short name T363
Test name
Test status
Simulation time 31152061 ps
CPU time 0.96 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:28:55 PM PST 24
Peak memory 197468 kb
Host smart-e086b55f-c51a-4a97-90cd-a61c3a0e4aa8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309736169 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.1309736169
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.62201216
Short name T580
Test name
Test status
Simulation time 170417851492 ps
CPU time 454.8 seconds
Started Feb 07 03:28:54 PM PST 24
Finished Feb 07 03:36:29 PM PST 24
Peak memory 198868 kb
Host smart-d1cdfb36-5507-4e72-a394-ef5b8fde1da9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62201216 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 30.hmac_test_sha_vectors.62201216
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.869866808
Short name T458
Test name
Test status
Simulation time 4834447843 ps
CPU time 72.78 seconds
Started Feb 07 03:28:53 PM PST 24
Finished Feb 07 03:30:06 PM PST 24
Peak memory 199064 kb
Host smart-4030b2ff-a99f-4780-8b35-86e1386a06a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869866808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.869866808
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3062713378
Short name T764
Test name
Test status
Simulation time 18279364 ps
CPU time 0.56 seconds
Started Feb 07 03:29:09 PM PST 24
Finished Feb 07 03:29:11 PM PST 24
Peak memory 193472 kb
Host smart-6335bf3b-e6b9-4e7c-9a46-1e5187f0d2b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062713378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3062713378
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.1214516554
Short name T471
Test name
Test status
Simulation time 120932940 ps
CPU time 5.26 seconds
Started Feb 07 03:29:01 PM PST 24
Finished Feb 07 03:29:09 PM PST 24
Peak memory 215396 kb
Host smart-96d53802-5bb1-4a6d-b7e1-e2444eb912f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1214516554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.1214516554
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3853197899
Short name T375
Test name
Test status
Simulation time 932985670 ps
CPU time 18.61 seconds
Started Feb 07 03:29:02 PM PST 24
Finished Feb 07 03:29:22 PM PST 24
Peak memory 199044 kb
Host smart-c8e0eb3a-6af0-4f91-abf1-cfc6dd61c9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853197899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3853197899
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3401239229
Short name T745
Test name
Test status
Simulation time 2474155135 ps
CPU time 144.1 seconds
Started Feb 07 03:29:04 PM PST 24
Finished Feb 07 03:31:32 PM PST 24
Peak memory 199076 kb
Host smart-3c0bb933-848c-4afa-9d57-25b5ec14dd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3401239229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3401239229
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.205745594
Short name T137
Test name
Test status
Simulation time 34598251351 ps
CPU time 208.22 seconds
Started Feb 07 03:29:03 PM PST 24
Finished Feb 07 03:32:32 PM PST 24
Peak memory 199068 kb
Host smart-da73f6c1-0c44-455f-86d1-0f3f1d85507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205745594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.205745594
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.844421554
Short name T533
Test name
Test status
Simulation time 12113517406 ps
CPU time 57.88 seconds
Started Feb 07 03:29:03 PM PST 24
Finished Feb 07 03:30:02 PM PST 24
Peak memory 199176 kb
Host smart-2f978b20-d38c-4e23-997e-cd483f0f7509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844421554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.844421554
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.3026239444
Short name T466
Test name
Test status
Simulation time 395197065 ps
CPU time 4.79 seconds
Started Feb 07 03:28:58 PM PST 24
Finished Feb 07 03:29:04 PM PST 24
Peak memory 199016 kb
Host smart-6a527ba2-020f-459d-bfaa-5627fdac1889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026239444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.3026239444
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.319037215
Short name T350
Test name
Test status
Simulation time 81348645023 ps
CPU time 682.86 seconds
Started Feb 07 03:29:09 PM PST 24
Finished Feb 07 03:40:34 PM PST 24
Peak memory 214600 kb
Host smart-1cb0e259-4bdc-4492-9d2e-4588a91391a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319037215 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.319037215
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.501079630
Short name T568
Test name
Test status
Simulation time 203492548457 ps
CPU time 345.28 seconds
Started Feb 07 03:29:14 PM PST 24
Finished Feb 07 03:35:00 PM PST 24
Peak memory 225852 kb
Host smart-71cc53c8-4f6c-448d-b1c1-62b41e583db1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501079630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.501079630
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.4129603155
Short name T299
Test name
Test status
Simulation time 88252299 ps
CPU time 0.99 seconds
Started Feb 07 03:29:10 PM PST 24
Finished Feb 07 03:29:12 PM PST 24
Peak memory 196708 kb
Host smart-8aaa1edb-5661-4d91-be6c-33ec2be674fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129603155 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.4129603155
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3283672286
Short name T418
Test name
Test status
Simulation time 160403091764 ps
CPU time 468.16 seconds
Started Feb 07 03:29:09 PM PST 24
Finished Feb 07 03:36:59 PM PST 24
Peak memory 199116 kb
Host smart-a079816f-9ffb-4a3f-8e4e-1a351fc0787c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283672286 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.3283672286
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2890584097
Short name T241
Test name
Test status
Simulation time 3455775400 ps
CPU time 61.6 seconds
Started Feb 07 03:29:08 PM PST 24
Finished Feb 07 03:30:10 PM PST 24
Peak memory 199104 kb
Host smart-09fb4f50-bb53-4570-b9b1-22c3167e23f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890584097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2890584097
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2894027268
Short name T552
Test name
Test status
Simulation time 27529956 ps
CPU time 0.55 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:29:30 PM PST 24
Peak memory 193236 kb
Host smart-94daa2b9-46e4-457f-8d3c-39071d980cdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894027268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2894027268
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2931072541
Short name T226
Test name
Test status
Simulation time 1473690431 ps
CPU time 17.08 seconds
Started Feb 07 03:29:15 PM PST 24
Finished Feb 07 03:29:33 PM PST 24
Peak memory 215252 kb
Host smart-2e43adca-958e-4b9b-b779-48496ac5dfca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2931072541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2931072541
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3371896296
Short name T446
Test name
Test status
Simulation time 435022942 ps
CPU time 19.58 seconds
Started Feb 07 03:29:30 PM PST 24
Finished Feb 07 03:29:50 PM PST 24
Peak memory 199024 kb
Host smart-58addd6d-19fe-4df4-8e41-d679be7824c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371896296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3371896296
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4012694365
Short name T539
Test name
Test status
Simulation time 1037605581 ps
CPU time 29.22 seconds
Started Feb 07 03:29:22 PM PST 24
Finished Feb 07 03:29:52 PM PST 24
Peak memory 199068 kb
Host smart-0005709e-694d-4e88-8273-b076dc44eb9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4012694365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4012694365
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.910775315
Short name T851
Test name
Test status
Simulation time 3369794684 ps
CPU time 148.42 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:31:59 PM PST 24
Peak memory 199056 kb
Host smart-27094736-cd87-491b-b735-033ef1faa16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910775315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.910775315
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.1430027753
Short name T383
Test name
Test status
Simulation time 166258051 ps
CPU time 4.63 seconds
Started Feb 07 03:29:13 PM PST 24
Finished Feb 07 03:29:19 PM PST 24
Peak memory 199056 kb
Host smart-5c1f2a64-d6eb-4eea-9f88-8148d2b3f2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430027753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.1430027753
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1109577390
Short name T305
Test name
Test status
Simulation time 136138653 ps
CPU time 3.44 seconds
Started Feb 07 03:29:15 PM PST 24
Finished Feb 07 03:29:19 PM PST 24
Peak memory 198956 kb
Host smart-c53e88b8-1e08-4e32-8956-cf182e751f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109577390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1109577390
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.2901308223
Short name T451
Test name
Test status
Simulation time 27343637213 ps
CPU time 675.85 seconds
Started Feb 07 03:29:24 PM PST 24
Finished Feb 07 03:40:41 PM PST 24
Peak memory 231892 kb
Host smart-6926e886-99fc-44c2-b9a8-2095d1333422
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901308223 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.2901308223
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all_with_rand_reset.2336834015
Short name T599
Test name
Test status
Simulation time 205502825554 ps
CPU time 849.42 seconds
Started Feb 07 03:29:24 PM PST 24
Finished Feb 07 03:43:34 PM PST 24
Peak memory 246004 kb
Host smart-fcc11129-b8d9-42cb-9c0d-0729155b9176
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2336834015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all_with_rand_reset.2336834015
Directory /workspace/32.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2332517222
Short name T286
Test name
Test status
Simulation time 50172898 ps
CPU time 0.88 seconds
Started Feb 07 03:29:22 PM PST 24
Finished Feb 07 03:29:23 PM PST 24
Peak memory 196856 kb
Host smart-7eb9cf60-13b8-44a2-88cc-0a9fa40ab8fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332517222 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2332517222
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3828361927
Short name T405
Test name
Test status
Simulation time 30521163307 ps
CPU time 385.13 seconds
Started Feb 07 03:29:23 PM PST 24
Finished Feb 07 03:35:49 PM PST 24
Peak memory 199120 kb
Host smart-bf2bdbfb-6fcc-4a77-a97d-cabab849dc6d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828361927 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_sha_vectors.3828361927
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1014445287
Short name T570
Test name
Test status
Simulation time 1237176129 ps
CPU time 55.77 seconds
Started Feb 07 03:29:25 PM PST 24
Finished Feb 07 03:30:21 PM PST 24
Peak memory 199068 kb
Host smart-5fed83b1-c684-43eb-8f95-bfed02137aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014445287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1014445287
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.3097869554
Short name T408
Test name
Test status
Simulation time 31116781 ps
CPU time 0.59 seconds
Started Feb 07 03:29:25 PM PST 24
Finished Feb 07 03:29:26 PM PST 24
Peak memory 193448 kb
Host smart-69ca6df0-ec07-48d6-ac9f-c6711c149bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097869554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.3097869554
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3725998214
Short name T536
Test name
Test status
Simulation time 2997083745 ps
CPU time 21.48 seconds
Started Feb 07 03:29:28 PM PST 24
Finished Feb 07 03:29:50 PM PST 24
Peak memory 199040 kb
Host smart-e5d19bd4-769b-4dc1-b246-6f5a908972f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725998214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3725998214
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.816801172
Short name T217
Test name
Test status
Simulation time 2369203893 ps
CPU time 52.61 seconds
Started Feb 07 03:29:28 PM PST 24
Finished Feb 07 03:30:21 PM PST 24
Peak memory 198832 kb
Host smart-5b473d92-5f4a-4237-a0cb-ad6155715b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816801172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.816801172
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.4205216063
Short name T452
Test name
Test status
Simulation time 2978230153 ps
CPU time 44.5 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:30:14 PM PST 24
Peak memory 198680 kb
Host smart-99bea29c-840a-4c6c-b9c8-e106d591b5b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4205216063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.4205216063
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2797768690
Short name T614
Test name
Test status
Simulation time 3402696467 ps
CPU time 58.24 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:30:29 PM PST 24
Peak memory 199052 kb
Host smart-3fb6f239-7d24-4a2c-8dbf-bcefdb4a4036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797768690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2797768690
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1357778126
Short name T740
Test name
Test status
Simulation time 2917269186 ps
CPU time 21.44 seconds
Started Feb 07 03:29:23 PM PST 24
Finished Feb 07 03:29:45 PM PST 24
Peak memory 199136 kb
Host smart-b4cc2738-af78-4b7b-9e60-bdb728f4bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357778126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1357778126
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2723779995
Short name T365
Test name
Test status
Simulation time 87935670 ps
CPU time 1.4 seconds
Started Feb 07 03:29:25 PM PST 24
Finished Feb 07 03:29:27 PM PST 24
Peak memory 197552 kb
Host smart-fe3086d2-5d7e-4910-a18c-cc69fd31dbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723779995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2723779995
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.306544841
Short name T112
Test name
Test status
Simulation time 10061988082 ps
CPU time 128.3 seconds
Started Feb 07 03:29:23 PM PST 24
Finished Feb 07 03:31:32 PM PST 24
Peak memory 199100 kb
Host smart-e6b528a1-cdda-4c3d-b73d-8a87d05d06aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306544841 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.306544841
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_stress_all_with_rand_reset.1986589017
Short name T109
Test name
Test status
Simulation time 225455292622 ps
CPU time 1066.77 seconds
Started Feb 07 03:29:30 PM PST 24
Finished Feb 07 03:47:20 PM PST 24
Peak memory 248336 kb
Host smart-87d8a067-1953-46cb-95a0-e4b4f2270add
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1986589017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all_with_rand_reset.1986589017
Directory /workspace/33.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.721772756
Short name T727
Test name
Test status
Simulation time 67907274 ps
CPU time 1.11 seconds
Started Feb 07 03:29:28 PM PST 24
Finished Feb 07 03:29:29 PM PST 24
Peak memory 197372 kb
Host smart-fa4b67e8-b4d5-499d-98cb-64c8e317044a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721772756 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_hmac_vectors.721772756
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.1324364717
Short name T844
Test name
Test status
Simulation time 28303784416 ps
CPU time 469.11 seconds
Started Feb 07 03:29:27 PM PST 24
Finished Feb 07 03:37:17 PM PST 24
Peak memory 199100 kb
Host smart-1882aa93-3d06-4263-a825-bffbf9bdccf6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324364717 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.1324364717
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1750449274
Short name T768
Test name
Test status
Simulation time 2821970758 ps
CPU time 27.02 seconds
Started Feb 07 03:29:30 PM PST 24
Finished Feb 07 03:29:58 PM PST 24
Peak memory 199096 kb
Host smart-dea21b3a-e0ff-421b-831c-ed87aeb357b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750449274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1750449274
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.397923143
Short name T596
Test name
Test status
Simulation time 12209516 ps
CPU time 0.57 seconds
Started Feb 07 03:29:38 PM PST 24
Finished Feb 07 03:29:40 PM PST 24
Peak memory 193392 kb
Host smart-e9703b9b-23b3-4196-8e62-d385e4d60a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397923143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.397923143
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2746429796
Short name T778
Test name
Test status
Simulation time 57207146 ps
CPU time 2.7 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:29:32 PM PST 24
Peak memory 207268 kb
Host smart-c6e401b7-5c9e-49d7-99ce-18037043232f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746429796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2746429796
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3816961380
Short name T652
Test name
Test status
Simulation time 2854261606 ps
CPU time 31.97 seconds
Started Feb 07 03:29:30 PM PST 24
Finished Feb 07 03:30:06 PM PST 24
Peak memory 199096 kb
Host smart-ce0b7999-5247-458f-9488-7efebef4374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816961380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3816961380
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.250939571
Short name T807
Test name
Test status
Simulation time 1533509224 ps
CPU time 38.25 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:30:08 PM PST 24
Peak memory 199040 kb
Host smart-47295ed8-c925-432c-8af1-013ddf05808e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=250939571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.250939571
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1402582579
Short name T435
Test name
Test status
Simulation time 14797726849 ps
CPU time 118.7 seconds
Started Feb 07 03:29:37 PM PST 24
Finished Feb 07 03:31:38 PM PST 24
Peak memory 199044 kb
Host smart-643e5fcb-99f8-4383-a04e-faf6cd60cb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402582579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1402582579
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3691065430
Short name T483
Test name
Test status
Simulation time 1385248245 ps
CPU time 78.78 seconds
Started Feb 07 03:29:28 PM PST 24
Finished Feb 07 03:30:48 PM PST 24
Peak memory 198544 kb
Host smart-28f74bf4-d692-4fff-b34d-01848e600cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691065430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3691065430
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2552359230
Short name T746
Test name
Test status
Simulation time 1167853754 ps
CPU time 3.25 seconds
Started Feb 07 03:29:29 PM PST 24
Finished Feb 07 03:29:33 PM PST 24
Peak memory 198696 kb
Host smart-d80f7e94-e27d-42fc-8e8a-99ac95c78105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552359230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2552359230
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3847325584
Short name T615
Test name
Test status
Simulation time 22230425557 ps
CPU time 568.34 seconds
Started Feb 07 03:29:33 PM PST 24
Finished Feb 07 03:39:03 PM PST 24
Peak memory 231832 kb
Host smart-95ea893e-34ca-4c6f-b85c-16fa17ddde23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847325584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3847325584
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.337058893
Short name T355
Test name
Test status
Simulation time 520299894659 ps
CPU time 1326.15 seconds
Started Feb 07 03:29:34 PM PST 24
Finished Feb 07 03:51:42 PM PST 24
Peak memory 231968 kb
Host smart-553e8021-d927-4dfb-922e-c1f9f77825c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337058893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.337058893
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2599331605
Short name T741
Test name
Test status
Simulation time 27498418 ps
CPU time 0.92 seconds
Started Feb 07 03:29:33 PM PST 24
Finished Feb 07 03:29:36 PM PST 24
Peak memory 196292 kb
Host smart-cfd34d5f-9764-4776-9de4-44a126c820ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599331605 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2599331605
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3844970619
Short name T211
Test name
Test status
Simulation time 40397063946 ps
CPU time 459.47 seconds
Started Feb 07 03:29:33 PM PST 24
Finished Feb 07 03:37:14 PM PST 24
Peak memory 199040 kb
Host smart-8659d410-33b5-4fbb-89ec-6c3fa71aaaaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844970619 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.3844970619
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.463208160
Short name T847
Test name
Test status
Simulation time 6161775148 ps
CPU time 19.61 seconds
Started Feb 07 03:29:34 PM PST 24
Finished Feb 07 03:29:54 PM PST 24
Peak memory 199096 kb
Host smart-29f2b160-433d-44f9-926b-1cfd78fc1f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463208160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.463208160
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.4080653340
Short name T393
Test name
Test status
Simulation time 61370519 ps
CPU time 0.54 seconds
Started Feb 07 03:29:43 PM PST 24
Finished Feb 07 03:29:44 PM PST 24
Peak memory 193428 kb
Host smart-99730076-a3d2-479a-b87d-f0fdbab19435
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080653340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.4080653340
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4229950109
Short name T268
Test name
Test status
Simulation time 191539487 ps
CPU time 5.94 seconds
Started Feb 07 03:29:40 PM PST 24
Finished Feb 07 03:29:47 PM PST 24
Peak memory 199008 kb
Host smart-6e31309d-28dc-46bf-8071-26f2dac80242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4229950109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4229950109
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2252046118
Short name T346
Test name
Test status
Simulation time 1228887972 ps
CPU time 9.42 seconds
Started Feb 07 03:29:39 PM PST 24
Finished Feb 07 03:29:49 PM PST 24
Peak memory 199032 kb
Host smart-8c6f81d0-5be7-451f-bf17-6d23df8f10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252046118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2252046118
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.290982517
Short name T8
Test name
Test status
Simulation time 564012158 ps
CPU time 27.43 seconds
Started Feb 07 03:29:40 PM PST 24
Finished Feb 07 03:30:08 PM PST 24
Peak memory 199016 kb
Host smart-8eb34303-1e0e-43f0-b241-666fb38fdf4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=290982517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.290982517
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.4054629171
Short name T842
Test name
Test status
Simulation time 11115549031 ps
CPU time 177.44 seconds
Started Feb 07 03:29:37 PM PST 24
Finished Feb 07 03:32:36 PM PST 24
Peak memory 199128 kb
Host smart-c5b3f095-54b4-415b-9384-4cfcca41e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054629171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.4054629171
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2491823836
Short name T771
Test name
Test status
Simulation time 9935973090 ps
CPU time 79.18 seconds
Started Feb 07 03:29:41 PM PST 24
Finished Feb 07 03:31:01 PM PST 24
Peak memory 199056 kb
Host smart-a1a67c34-a6aa-427e-afc1-f05a1f703745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491823836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2491823836
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.653684121
Short name T697
Test name
Test status
Simulation time 327145459 ps
CPU time 3.85 seconds
Started Feb 07 03:29:41 PM PST 24
Finished Feb 07 03:29:45 PM PST 24
Peak memory 198808 kb
Host smart-f352a53f-ddf1-4978-ab6b-42eb6b17badd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653684121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.653684121
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4260635449
Short name T813
Test name
Test status
Simulation time 57276245428 ps
CPU time 390.27 seconds
Started Feb 07 03:29:45 PM PST 24
Finished Feb 07 03:36:16 PM PST 24
Peak memory 199112 kb
Host smart-ff2b0900-b514-4423-a7f0-192d1a9cc502
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260635449 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4260635449
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.2770003639
Short name T128
Test name
Test status
Simulation time 277635766164 ps
CPU time 2258.42 seconds
Started Feb 07 03:29:45 PM PST 24
Finished Feb 07 04:07:24 PM PST 24
Peak memory 256280 kb
Host smart-7094fdad-f60e-4b8a-aa1b-9ccd3aef23e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2770003639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.2770003639
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3280888252
Short name T287
Test name
Test status
Simulation time 332862631 ps
CPU time 0.91 seconds
Started Feb 07 03:29:37 PM PST 24
Finished Feb 07 03:29:40 PM PST 24
Peak memory 196644 kb
Host smart-e2ae257a-ecf0-4a87-b3b0-b8be50a1d4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280888252 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.3280888252
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.133783223
Short name T401
Test name
Test status
Simulation time 101703636322 ps
CPU time 409.79 seconds
Started Feb 07 03:29:37 PM PST 24
Finished Feb 07 03:36:29 PM PST 24
Peak memory 199008 kb
Host smart-9aea3319-f0f4-47b0-b631-f164002d05af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133783223 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.hmac_test_sha_vectors.133783223
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3524353991
Short name T815
Test name
Test status
Simulation time 2134513427 ps
CPU time 78.49 seconds
Started Feb 07 03:29:37 PM PST 24
Finished Feb 07 03:30:57 PM PST 24
Peak memory 199048 kb
Host smart-2372d4c0-2c1d-432f-a763-827e262158b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524353991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3524353991
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4147505496
Short name T370
Test name
Test status
Simulation time 16168258 ps
CPU time 0.59 seconds
Started Feb 07 03:29:57 PM PST 24
Finished Feb 07 03:29:58 PM PST 24
Peak memory 193436 kb
Host smart-d500b3ac-5c2e-48b4-b9b7-7011b62db03f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147505496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4147505496
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3397718778
Short name T672
Test name
Test status
Simulation time 275813113 ps
CPU time 8.32 seconds
Started Feb 07 03:29:49 PM PST 24
Finished Feb 07 03:29:57 PM PST 24
Peak memory 207208 kb
Host smart-028028e3-82cb-45c0-9312-04da4a4b90e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397718778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3397718778
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1173121262
Short name T410
Test name
Test status
Simulation time 187903327 ps
CPU time 3.26 seconds
Started Feb 07 03:29:52 PM PST 24
Finished Feb 07 03:29:56 PM PST 24
Peak memory 199060 kb
Host smart-0f67e02a-c2e9-4cc0-9305-3dbb7ce303bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173121262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1173121262
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1839736770
Short name T349
Test name
Test status
Simulation time 3038127918 ps
CPU time 54.48 seconds
Started Feb 07 03:29:50 PM PST 24
Finished Feb 07 03:30:45 PM PST 24
Peak memory 199088 kb
Host smart-2d4fc5df-95cc-4b01-ad10-e74ebb1d8879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1839736770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1839736770
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1731329060
Short name T422
Test name
Test status
Simulation time 7605855716 ps
CPU time 65.04 seconds
Started Feb 07 03:29:48 PM PST 24
Finished Feb 07 03:30:54 PM PST 24
Peak memory 199136 kb
Host smart-19de7e2f-e776-4a64-be70-1eb31cf8580e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731329060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1731329060
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3490439006
Short name T549
Test name
Test status
Simulation time 24883425005 ps
CPU time 59.39 seconds
Started Feb 07 03:29:54 PM PST 24
Finished Feb 07 03:30:54 PM PST 24
Peak memory 199052 kb
Host smart-207b824e-98f2-4bed-af7e-43f33f344075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490439006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3490439006
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3717441324
Short name T450
Test name
Test status
Simulation time 312250861 ps
CPU time 3.66 seconds
Started Feb 07 03:29:44 PM PST 24
Finished Feb 07 03:29:48 PM PST 24
Peak memory 198960 kb
Host smart-8f0a24fe-7b35-4586-9db2-7be855776ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717441324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3717441324
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.2853167349
Short name T118
Test name
Test status
Simulation time 56346272707 ps
CPU time 662.52 seconds
Started Feb 07 03:29:56 PM PST 24
Finished Feb 07 03:40:59 PM PST 24
Peak memory 228852 kb
Host smart-f72d370c-797a-4eab-9386-40368236349f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853167349 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.2853167349
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.4117129082
Short name T624
Test name
Test status
Simulation time 11004318301 ps
CPU time 163.94 seconds
Started Feb 07 03:29:55 PM PST 24
Finished Feb 07 03:32:40 PM PST 24
Peak memory 207300 kb
Host smart-43f47e30-642d-4cf1-ab74-5501b39abd91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117129082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.4117129082
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.55069296
Short name T719
Test name
Test status
Simulation time 174348661 ps
CPU time 0.89 seconds
Started Feb 07 03:29:54 PM PST 24
Finished Feb 07 03:29:56 PM PST 24
Peak memory 196672 kb
Host smart-715edd56-c4a2-4cfb-a860-2cee9735cdb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55069296 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_hmac_vectors.55069296
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.319951640
Short name T691
Test name
Test status
Simulation time 100492816600 ps
CPU time 402.18 seconds
Started Feb 07 03:29:56 PM PST 24
Finished Feb 07 03:36:39 PM PST 24
Peak memory 199136 kb
Host smart-38f7bc1b-8689-4496-91c1-0a03006e725b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319951640 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.319951640
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.500309126
Short name T606
Test name
Test status
Simulation time 7287644575 ps
CPU time 50.15 seconds
Started Feb 07 03:29:51 PM PST 24
Finished Feb 07 03:30:42 PM PST 24
Peak memory 199048 kb
Host smart-b245faec-5e06-4ce5-830f-57026ad936e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500309126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.500309126
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3509686529
Short name T448
Test name
Test status
Simulation time 13191123 ps
CPU time 0.58 seconds
Started Feb 07 03:30:08 PM PST 24
Finished Feb 07 03:30:09 PM PST 24
Peak memory 193460 kb
Host smart-6d232180-67f7-458a-ad18-d48a2b0a6270
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509686529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3509686529
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2604857628
Short name T726
Test name
Test status
Simulation time 1010809749 ps
CPU time 38.13 seconds
Started Feb 07 03:30:03 PM PST 24
Finished Feb 07 03:30:42 PM PST 24
Peak memory 224620 kb
Host smart-6d645730-953d-4a8d-9c03-f62a14f72bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604857628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2604857628
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.450215008
Short name T447
Test name
Test status
Simulation time 2704811165 ps
CPU time 40.7 seconds
Started Feb 07 03:30:02 PM PST 24
Finished Feb 07 03:30:43 PM PST 24
Peak memory 199132 kb
Host smart-fe6a0742-d577-46ba-a760-3d219edd04ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450215008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.450215008
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.712618341
Short name T477
Test name
Test status
Simulation time 146600002 ps
CPU time 7.75 seconds
Started Feb 07 03:30:08 PM PST 24
Finished Feb 07 03:30:16 PM PST 24
Peak memory 198976 kb
Host smart-6d7fb9bb-9ea7-496c-b979-2cf77ff1c8d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712618341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.712618341
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2289320559
Short name T480
Test name
Test status
Simulation time 23805147258 ps
CPU time 52.73 seconds
Started Feb 07 03:30:08 PM PST 24
Finished Feb 07 03:31:01 PM PST 24
Peak memory 199096 kb
Host smart-e568a855-785a-41a2-b9d3-9d0cb8e33683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289320559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2289320559
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1625978787
Short name T273
Test name
Test status
Simulation time 1384072864 ps
CPU time 72.92 seconds
Started Feb 07 03:30:08 PM PST 24
Finished Feb 07 03:31:21 PM PST 24
Peak memory 199032 kb
Host smart-ae6032c1-6b53-472c-9386-313310f2d0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625978787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1625978787
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3133893740
Short name T581
Test name
Test status
Simulation time 214678747 ps
CPU time 1.28 seconds
Started Feb 07 03:30:07 PM PST 24
Finished Feb 07 03:30:09 PM PST 24
Peak memory 198380 kb
Host smart-e5e827a0-59fd-44b8-a4dc-2830f7c4f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133893740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3133893740
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.336552617
Short name T485
Test name
Test status
Simulation time 7845882547 ps
CPU time 331.23 seconds
Started Feb 07 03:30:08 PM PST 24
Finished Feb 07 03:35:40 PM PST 24
Peak memory 199108 kb
Host smart-b79ed5a1-89d2-4b11-b94e-4e58b0674883
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336552617 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.336552617
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.285851930
Short name T591
Test name
Test status
Simulation time 50329950 ps
CPU time 0.94 seconds
Started Feb 07 03:30:09 PM PST 24
Finished Feb 07 03:30:10 PM PST 24
Peak memory 195860 kb
Host smart-9c079e8f-5751-418f-90a1-f5c73cbc827f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285851930 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_hmac_vectors.285851930
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1796025126
Short name T397
Test name
Test status
Simulation time 31719919960 ps
CPU time 411.42 seconds
Started Feb 07 03:30:02 PM PST 24
Finished Feb 07 03:36:54 PM PST 24
Peak memory 199120 kb
Host smart-eb203edf-0c0f-4830-bccb-4aec5324fdff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796025126 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.1796025126
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.772070766
Short name T255
Test name
Test status
Simulation time 17735366610 ps
CPU time 18.98 seconds
Started Feb 07 03:30:10 PM PST 24
Finished Feb 07 03:30:30 PM PST 24
Peak memory 198728 kb
Host smart-3ce2005d-d3e7-468e-ac82-2a8430544ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772070766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.772070766
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1224375651
Short name T321
Test name
Test status
Simulation time 22951167 ps
CPU time 0.56 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:30:16 PM PST 24
Peak memory 193488 kb
Host smart-a9962ea2-9cc0-4ee0-95bc-cc68b84ce2f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224375651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1224375651
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.3839180853
Short name T754
Test name
Test status
Simulation time 2430381502 ps
CPU time 22.28 seconds
Started Feb 07 03:30:07 PM PST 24
Finished Feb 07 03:30:30 PM PST 24
Peak memory 211972 kb
Host smart-9c62621f-044a-4fa0-bd48-20a46e2ab738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3839180853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.3839180853
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2871473934
Short name T205
Test name
Test status
Simulation time 580475691 ps
CPU time 4.41 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:30:19 PM PST 24
Peak memory 199024 kb
Host smart-ae20e974-900b-44d1-b535-ec3c637b96fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871473934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2871473934
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.115991854
Short name T467
Test name
Test status
Simulation time 2595869728 ps
CPU time 146.95 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:32:42 PM PST 24
Peak memory 199076 kb
Host smart-caa2512f-3dc7-4ce8-84bb-d48c269efce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=115991854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.115991854
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.974468091
Short name T544
Test name
Test status
Simulation time 31241436963 ps
CPU time 203.98 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:33:39 PM PST 24
Peak memory 199052 kb
Host smart-1252be90-b200-46eb-a45c-b3941e68cf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974468091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.974468091
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.967848915
Short name T7
Test name
Test status
Simulation time 1557025885 ps
CPU time 21.38 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:30:36 PM PST 24
Peak memory 198908 kb
Host smart-2795f137-d92c-451e-833e-358316273118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967848915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.967848915
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3453482485
Short name T769
Test name
Test status
Simulation time 26937718 ps
CPU time 0.77 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:30:15 PM PST 24
Peak memory 194908 kb
Host smart-f910611d-9ac4-4f76-b3a0-8e0131f50658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453482485 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3453482485
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.157313478
Short name T348
Test name
Test status
Simulation time 156055292276 ps
CPU time 708.45 seconds
Started Feb 07 03:30:13 PM PST 24
Finished Feb 07 03:42:03 PM PST 24
Peak memory 199084 kb
Host smart-159f377d-beac-41a1-b661-537fee022dc5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157313478 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.157313478
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_stress_all_with_rand_reset.1406107719
Short name T453
Test name
Test status
Simulation time 124370662164 ps
CPU time 2355.04 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 04:09:30 PM PST 24
Peak memory 248100 kb
Host smart-8da28219-0b80-47e8-aa34-b0e1dce9e161
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406107719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all_with_rand_reset.1406107719
Directory /workspace/38.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1790387974
Short name T635
Test name
Test status
Simulation time 59674269 ps
CPU time 1.16 seconds
Started Feb 07 03:30:14 PM PST 24
Finished Feb 07 03:30:16 PM PST 24
Peak memory 198184 kb
Host smart-895decf3-f883-4915-99cb-0c2377855c36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790387974 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1790387974
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1838006837
Short name T272
Test name
Test status
Simulation time 2245787930 ps
CPU time 69.9 seconds
Started Feb 07 03:30:15 PM PST 24
Finished Feb 07 03:31:26 PM PST 24
Peak memory 199084 kb
Host smart-987b521d-4f7e-47dd-9725-792aa732913b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838006837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1838006837
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.1366975607
Short name T850
Test name
Test status
Simulation time 36296268 ps
CPU time 0.55 seconds
Started Feb 07 03:30:31 PM PST 24
Finished Feb 07 03:30:32 PM PST 24
Peak memory 193420 kb
Host smart-bcacfa22-354a-412c-b163-4273e56f130b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366975607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.1366975607
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.307279007
Short name T34
Test name
Test status
Simulation time 899330937 ps
CPU time 40.62 seconds
Started Feb 07 03:30:18 PM PST 24
Finished Feb 07 03:30:59 PM PST 24
Peak memory 216476 kb
Host smart-e7b1c1cb-a4ad-4c50-945e-5f64df4776a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=307279007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.307279007
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2650111705
Short name T492
Test name
Test status
Simulation time 4629140560 ps
CPU time 41.62 seconds
Started Feb 07 03:30:24 PM PST 24
Finished Feb 07 03:31:06 PM PST 24
Peak memory 198916 kb
Host smart-e3eb253e-753b-43b8-b659-e62d236a7f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650111705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2650111705
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3755934931
Short name T626
Test name
Test status
Simulation time 804055232 ps
CPU time 41.78 seconds
Started Feb 07 03:30:18 PM PST 24
Finished Feb 07 03:31:00 PM PST 24
Peak memory 199064 kb
Host smart-a36b686f-aac8-42aa-b5b8-7446e5612c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755934931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3755934931
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.162423694
Short name T43
Test name
Test status
Simulation time 2379684076 ps
CPU time 18.38 seconds
Started Feb 07 03:30:24 PM PST 24
Finished Feb 07 03:30:42 PM PST 24
Peak memory 199116 kb
Host smart-12dbf2ad-5255-4d9a-aacf-90f798dcf3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162423694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.162423694
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2420767219
Short name T823
Test name
Test status
Simulation time 17311815851 ps
CPU time 75.99 seconds
Started Feb 07 03:30:17 PM PST 24
Finished Feb 07 03:31:34 PM PST 24
Peak memory 199036 kb
Host smart-2e0765dc-325b-460f-a7d4-99ac38c2689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420767219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2420767219
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2265805223
Short name T233
Test name
Test status
Simulation time 210834833 ps
CPU time 2.8 seconds
Started Feb 07 03:30:17 PM PST 24
Finished Feb 07 03:30:20 PM PST 24
Peak memory 199032 kb
Host smart-0c4c7e3f-4ff8-44d2-a1ad-ac4a0fa70110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265805223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2265805223
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3354640492
Short name T686
Test name
Test status
Simulation time 58795786624 ps
CPU time 739.32 seconds
Started Feb 07 03:30:23 PM PST 24
Finished Feb 07 03:42:42 PM PST 24
Peak memory 199108 kb
Host smart-f40088ea-ed96-471d-8269-1c9c04567706
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354640492 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3354640492
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_stress_all_with_rand_reset.2309183477
Short name T713
Test name
Test status
Simulation time 90691247097 ps
CPU time 1651.15 seconds
Started Feb 07 03:30:31 PM PST 24
Finished Feb 07 03:58:02 PM PST 24
Peak memory 258528 kb
Host smart-a30fe249-4eaa-4d43-8bac-9ad00b075227
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309183477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all_with_rand_reset.2309183477
Directory /workspace/39.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1471017181
Short name T525
Test name
Test status
Simulation time 247406260 ps
CPU time 1.21 seconds
Started Feb 07 03:30:23 PM PST 24
Finished Feb 07 03:30:25 PM PST 24
Peak memory 197524 kb
Host smart-63a1456c-ca3f-4525-9683-f05b3032eec2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471017181 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1471017181
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.1712351654
Short name T597
Test name
Test status
Simulation time 71899559845 ps
CPU time 423.14 seconds
Started Feb 07 03:30:23 PM PST 24
Finished Feb 07 03:37:27 PM PST 24
Peak memory 198956 kb
Host smart-627cb563-cee7-4945-bd86-c0fe67b3e677
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712351654 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.1712351654
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1238010654
Short name T310
Test name
Test status
Simulation time 19087132419 ps
CPU time 85.68 seconds
Started Feb 07 03:30:24 PM PST 24
Finished Feb 07 03:31:51 PM PST 24
Peak memory 199116 kb
Host smart-fc03a7e5-8834-4649-a027-48aef88f9f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238010654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1238010654
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.2039423042
Short name T508
Test name
Test status
Simulation time 26347068 ps
CPU time 0.59 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:24:34 PM PST 24
Peak memory 193440 kb
Host smart-441505f1-bdb5-4e21-8350-63886fa4c374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039423042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.2039423042
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4221251367
Short name T35
Test name
Test status
Simulation time 1540263386 ps
CPU time 67.49 seconds
Started Feb 07 03:24:28 PM PST 24
Finished Feb 07 03:25:36 PM PST 24
Peak memory 230756 kb
Host smart-ad5ca219-4996-4c8e-943c-e4a7e5089ca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221251367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4221251367
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3396547608
Short name T376
Test name
Test status
Simulation time 9244969487 ps
CPU time 33.1 seconds
Started Feb 07 03:24:26 PM PST 24
Finished Feb 07 03:24:59 PM PST 24
Peak memory 199084 kb
Host smart-73d75018-fc9d-4cd0-8b29-df85a0570a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396547608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3396547608
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.1662131194
Short name T831
Test name
Test status
Simulation time 4326065760 ps
CPU time 119.69 seconds
Started Feb 07 03:24:26 PM PST 24
Finished Feb 07 03:26:26 PM PST 24
Peak memory 199088 kb
Host smart-0c77882b-4521-4570-8101-6b56e9819d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1662131194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.1662131194
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1635510091
Short name T439
Test name
Test status
Simulation time 120538060333 ps
CPU time 201.76 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:27:55 PM PST 24
Peak memory 199072 kb
Host smart-61b5704a-bdbf-4067-98f6-0f4505c7611a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635510091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1635510091
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3174063046
Short name T712
Test name
Test status
Simulation time 27612965 ps
CPU time 0.64 seconds
Started Feb 07 03:24:31 PM PST 24
Finished Feb 07 03:24:32 PM PST 24
Peak memory 193460 kb
Host smart-c4293a64-23f8-47c7-906d-c1e886bce724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174063046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3174063046
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_smoke.1199662804
Short name T742
Test name
Test status
Simulation time 141773317 ps
CPU time 1.21 seconds
Started Feb 07 03:24:25 PM PST 24
Finished Feb 07 03:24:27 PM PST 24
Peak memory 198296 kb
Host smart-8492bc8a-0e11-49d9-812d-d69cc58d33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199662804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1199662804
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.541573002
Short name T267
Test name
Test status
Simulation time 115021636149 ps
CPU time 430.32 seconds
Started Feb 07 03:24:27 PM PST 24
Finished Feb 07 03:31:38 PM PST 24
Peak memory 199108 kb
Host smart-f8d845ad-dcae-4aa5-b2a6-08a2151e5919
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541573002 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.541573002
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_stress_all_with_rand_reset.1625236158
Short name T441
Test name
Test status
Simulation time 29081148933 ps
CPU time 232.27 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:28:25 PM PST 24
Peak memory 215600 kb
Host smart-21683799-fa92-454d-b537-5f9ad263c3dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625236158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all_with_rand_reset.1625236158
Directory /workspace/4.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1667066755
Short name T530
Test name
Test status
Simulation time 707335162 ps
CPU time 1.2 seconds
Started Feb 07 03:24:25 PM PST 24
Finished Feb 07 03:24:27 PM PST 24
Peak memory 198096 kb
Host smart-7efa1988-b6e4-4c1d-95a4-3629de5b3c66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667066755 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1667066755
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.804999417
Short name T314
Test name
Test status
Simulation time 17569868959 ps
CPU time 372.37 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:30:46 PM PST 24
Peak memory 199160 kb
Host smart-45d6bc58-4367-4b41-b0a0-a69470c1990b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804999417 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.hmac_test_sha_vectors.804999417
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3945842276
Short name T698
Test name
Test status
Simulation time 24517781744 ps
CPU time 85.06 seconds
Started Feb 07 03:24:26 PM PST 24
Finished Feb 07 03:25:52 PM PST 24
Peak memory 199096 kb
Host smart-e20d3476-e0cc-4ea5-a883-bb243f92fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945842276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3945842276
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.946549576
Short name T357
Test name
Test status
Simulation time 11651318 ps
CPU time 0.58 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:30:54 PM PST 24
Peak memory 193468 kb
Host smart-68eaac9f-88da-4955-92b4-4bc2b76ba095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946549576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.946549576
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2154554179
Short name T825
Test name
Test status
Simulation time 1977733081 ps
CPU time 32.34 seconds
Started Feb 07 03:30:29 PM PST 24
Finished Feb 07 03:31:02 PM PST 24
Peak memory 207244 kb
Host smart-58881197-92f0-4f36-9f60-4e1a066057cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154554179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2154554179
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.672560657
Short name T543
Test name
Test status
Simulation time 359526831 ps
CPU time 4.55 seconds
Started Feb 07 03:30:43 PM PST 24
Finished Feb 07 03:30:48 PM PST 24
Peak memory 199040 kb
Host smart-0beb0527-ac3e-4680-9ce6-48103eb5e418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672560657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.672560657
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2217865371
Short name T677
Test name
Test status
Simulation time 1940772948 ps
CPU time 51.1 seconds
Started Feb 07 03:30:31 PM PST 24
Finished Feb 07 03:31:22 PM PST 24
Peak memory 199040 kb
Host smart-dcf864ea-43f4-450a-96bf-2a0f8978881f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217865371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2217865371
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4067097159
Short name T579
Test name
Test status
Simulation time 10545848760 ps
CPU time 68.64 seconds
Started Feb 07 03:30:41 PM PST 24
Finished Feb 07 03:31:50 PM PST 24
Peak memory 199096 kb
Host smart-3649a398-5b0d-4871-a06e-0c968b5b3847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067097159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4067097159
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.3513782565
Short name T456
Test name
Test status
Simulation time 34170065874 ps
CPU time 62.17 seconds
Started Feb 07 03:30:31 PM PST 24
Finished Feb 07 03:31:34 PM PST 24
Peak memory 199100 kb
Host smart-3bb5327c-a662-408c-aa42-be9a28a9f3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513782565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.3513782565
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3403616145
Short name T798
Test name
Test status
Simulation time 848096179 ps
CPU time 2.91 seconds
Started Feb 07 03:30:29 PM PST 24
Finished Feb 07 03:30:32 PM PST 24
Peak memory 198944 kb
Host smart-e5cb2f87-9de2-4d22-84d9-4508a2924dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403616145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3403616145
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1384267648
Short name T757
Test name
Test status
Simulation time 47114007091 ps
CPU time 426.95 seconds
Started Feb 07 03:30:46 PM PST 24
Finished Feb 07 03:37:54 PM PST 24
Peak memory 214536 kb
Host smart-3ee1537c-a5de-4ac8-9308-57b4555d32b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384267648 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1384267648
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_stress_all_with_rand_reset.2119955535
Short name T126
Test name
Test status
Simulation time 132332240335 ps
CPU time 2985.28 seconds
Started Feb 07 03:30:42 PM PST 24
Finished Feb 07 04:20:28 PM PST 24
Peak memory 256528 kb
Host smart-0223e519-4daa-4dd6-b94b-964bf5b33331
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119955535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all_with_rand_reset.2119955535
Directory /workspace/40.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.238713235
Short name T424
Test name
Test status
Simulation time 30933291 ps
CPU time 1.16 seconds
Started Feb 07 03:30:50 PM PST 24
Finished Feb 07 03:30:52 PM PST 24
Peak memory 198404 kb
Host smart-53578a0a-a74f-4a30-8c11-d32cfec0311d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238713235 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.238713235
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.3812468993
Short name T497
Test name
Test status
Simulation time 30226739959 ps
CPU time 418.33 seconds
Started Feb 07 03:30:47 PM PST 24
Finished Feb 07 03:37:46 PM PST 24
Peak memory 199120 kb
Host smart-4b99013b-df41-482f-8d41-abe5331e6d20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812468993 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.3812468993
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2955474624
Short name T207
Test name
Test status
Simulation time 583152142 ps
CPU time 4.09 seconds
Started Feb 07 03:30:46 PM PST 24
Finished Feb 07 03:30:51 PM PST 24
Peak memory 199008 kb
Host smart-e7f14f63-66f0-431d-b057-16d96a5ac222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955474624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2955474624
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2099155683
Short name T695
Test name
Test status
Simulation time 26108974 ps
CPU time 0.54 seconds
Started Feb 07 03:30:51 PM PST 24
Finished Feb 07 03:30:52 PM PST 24
Peak memory 193388 kb
Host smart-45ca82bb-1f3a-453d-a6cf-87889c2e3b69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099155683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2099155683
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2525972027
Short name T750
Test name
Test status
Simulation time 192083625 ps
CPU time 1.77 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:30:55 PM PST 24
Peak memory 198984 kb
Host smart-20203645-498c-4352-b917-c6e2b423503b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2525972027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2525972027
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1085263282
Short name T619
Test name
Test status
Simulation time 1619611629 ps
CPU time 22.76 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:31:17 PM PST 24
Peak memory 199048 kb
Host smart-f9ec4efa-17ef-485f-bfe4-c017c9465f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085263282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1085263282
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3280752050
Short name T653
Test name
Test status
Simulation time 2733600714 ps
CPU time 74.54 seconds
Started Feb 07 03:30:56 PM PST 24
Finished Feb 07 03:32:11 PM PST 24
Peak memory 199104 kb
Host smart-801a1d79-a548-4cc9-993a-e129ed8d5dc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280752050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3280752050
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.4249768488
Short name T639
Test name
Test status
Simulation time 27318334078 ps
CPU time 74.44 seconds
Started Feb 07 03:30:55 PM PST 24
Finished Feb 07 03:32:10 PM PST 24
Peak memory 199052 kb
Host smart-e12369bd-d6ea-4879-8f76-7a90d824bd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249768488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.4249768488
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.4284405684
Short name T607
Test name
Test status
Simulation time 1299039383 ps
CPU time 22.71 seconds
Started Feb 07 03:30:57 PM PST 24
Finished Feb 07 03:31:23 PM PST 24
Peak memory 199008 kb
Host smart-c7cfbd48-9217-45ad-bf8c-e275271e3a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284405684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.4284405684
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1736624444
Short name T609
Test name
Test status
Simulation time 957350450 ps
CPU time 3.54 seconds
Started Feb 07 03:30:54 PM PST 24
Finished Feb 07 03:30:59 PM PST 24
Peak memory 198840 kb
Host smart-ac28dc11-4630-440b-a1a2-8c682c1114ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736624444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1736624444
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2310806061
Short name T243
Test name
Test status
Simulation time 11422506923 ps
CPU time 176.46 seconds
Started Feb 07 03:30:54 PM PST 24
Finished Feb 07 03:33:51 PM PST 24
Peak memory 215596 kb
Host smart-362a0e13-147f-4172-b2dd-527dff4fb25d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310806061 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2310806061
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all_with_rand_reset.2625325576
Short name T800
Test name
Test status
Simulation time 30975943907 ps
CPU time 432.84 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:38:07 PM PST 24
Peak memory 223776 kb
Host smart-4127c759-b8a5-42ca-815f-2229861e7df6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2625325576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all_with_rand_reset.2625325576
Directory /workspace/41.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.33193874
Short name T433
Test name
Test status
Simulation time 269952245 ps
CPU time 1.15 seconds
Started Feb 07 03:30:56 PM PST 24
Finished Feb 07 03:30:57 PM PST 24
Peak memory 197380 kb
Host smart-4258a625-ec35-4561-b084-10e1ac1d1bd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33193874 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_hmac_vectors.33193874
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1532957968
Short name T304
Test name
Test status
Simulation time 7358508273 ps
CPU time 368.19 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:37:01 PM PST 24
Peak memory 198832 kb
Host smart-8f18725f-7a55-4238-ae3e-436b739a23a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532957968 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.1532957968
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.728667196
Short name T129
Test name
Test status
Simulation time 4422951924 ps
CPU time 42.75 seconds
Started Feb 07 03:30:53 PM PST 24
Finished Feb 07 03:31:36 PM PST 24
Peak memory 199108 kb
Host smart-3525c7da-fc7b-44ce-8a16-74db49fa1587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728667196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.728667196
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.3640650670
Short name T628
Test name
Test status
Simulation time 33239211 ps
CPU time 0.58 seconds
Started Feb 07 03:31:05 PM PST 24
Finished Feb 07 03:31:06 PM PST 24
Peak memory 193432 kb
Host smart-2ebc9b71-ed6d-4ac0-a2fc-104a0867de3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640650670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.3640650670
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.216834652
Short name T738
Test name
Test status
Simulation time 1718398859 ps
CPU time 39.25 seconds
Started Feb 07 03:30:56 PM PST 24
Finished Feb 07 03:31:39 PM PST 24
Peak memory 223616 kb
Host smart-49c61cb0-b9d8-4bdf-8c7b-281db629a87f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216834652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.216834652
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2273542031
Short name T362
Test name
Test status
Simulation time 1128682180 ps
CPU time 7.04 seconds
Started Feb 07 03:30:57 PM PST 24
Finished Feb 07 03:31:08 PM PST 24
Peak memory 199040 kb
Host smart-b88b073b-fc1d-4812-a2d3-6945deae0e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273542031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2273542031
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.321171742
Short name T828
Test name
Test status
Simulation time 4231616122 ps
CPU time 65.58 seconds
Started Feb 07 03:30:58 PM PST 24
Finished Feb 07 03:32:06 PM PST 24
Peak memory 199076 kb
Host smart-980614f3-4fe1-4560-9366-5ed4f9e64a6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321171742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.321171742
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3531375708
Short name T648
Test name
Test status
Simulation time 5899161398 ps
CPU time 95.64 seconds
Started Feb 07 03:30:57 PM PST 24
Finished Feb 07 03:32:36 PM PST 24
Peak memory 199112 kb
Host smart-435c040d-259b-4c6c-a075-79bf85245e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531375708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3531375708
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1778198648
Short name T824
Test name
Test status
Simulation time 23604914013 ps
CPU time 104.39 seconds
Started Feb 07 03:30:57 PM PST 24
Finished Feb 07 03:32:45 PM PST 24
Peak memory 199068 kb
Host smart-4a7e0953-cccb-474a-b058-c84ff062e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778198648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1778198648
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.406437488
Short name T444
Test name
Test status
Simulation time 1187621652 ps
CPU time 3.63 seconds
Started Feb 07 03:30:54 PM PST 24
Finished Feb 07 03:30:58 PM PST 24
Peak memory 198824 kb
Host smart-59d5447e-4e8f-4958-aa82-b352c443c019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406437488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.406437488
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1445223747
Short name T841
Test name
Test status
Simulation time 69646717838 ps
CPU time 715.94 seconds
Started Feb 07 03:31:06 PM PST 24
Finished Feb 07 03:43:02 PM PST 24
Peak memory 245564 kb
Host smart-1dfaf9d2-4c46-4421-8b5f-ad6cabd7dcae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445223747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1445223747
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all_with_rand_reset.1508671398
Short name T521
Test name
Test status
Simulation time 58181422454 ps
CPU time 2538.45 seconds
Started Feb 07 03:31:06 PM PST 24
Finished Feb 07 04:13:25 PM PST 24
Peak memory 242748 kb
Host smart-5684303b-7db7-4d3d-b14a-706975ce7882
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508671398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all_with_rand_reset.1508671398
Directory /workspace/42.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2366259944
Short name T40
Test name
Test status
Simulation time 32735599 ps
CPU time 1.17 seconds
Started Feb 07 03:31:09 PM PST 24
Finished Feb 07 03:31:11 PM PST 24
Peak memory 197872 kb
Host smart-fb8e98f9-b1dc-4514-998e-6126b0cea41e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366259944 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2366259944
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2658609703
Short name T269
Test name
Test status
Simulation time 37189923291 ps
CPU time 413.55 seconds
Started Feb 07 03:31:04 PM PST 24
Finished Feb 07 03:37:58 PM PST 24
Peak memory 199080 kb
Host smart-b71f39bb-b585-4700-a0bf-e8e0295b8f0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658609703 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2658609703
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3890479529
Short name T341
Test name
Test status
Simulation time 3959093113 ps
CPU time 71.24 seconds
Started Feb 07 03:30:58 PM PST 24
Finished Feb 07 03:32:12 PM PST 24
Peak memory 199080 kb
Host smart-c9391f85-9301-4cd6-98db-149d9943da32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890479529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3890479529
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.241048346
Short name T417
Test name
Test status
Simulation time 11931123 ps
CPU time 0.58 seconds
Started Feb 07 03:31:14 PM PST 24
Finished Feb 07 03:31:15 PM PST 24
Peak memory 193416 kb
Host smart-127422b9-50ff-46c8-9e2e-65461aec5b70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241048346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.241048346
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3658181117
Short name T794
Test name
Test status
Simulation time 3177391649 ps
CPU time 60.55 seconds
Started Feb 07 03:31:05 PM PST 24
Finished Feb 07 03:32:06 PM PST 24
Peak memory 223612 kb
Host smart-e194f337-2f25-4a52-9fc9-6c415fe9c10d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658181117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3658181117
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1013426935
Short name T655
Test name
Test status
Simulation time 1122487011 ps
CPU time 22.14 seconds
Started Feb 07 03:31:05 PM PST 24
Finished Feb 07 03:31:28 PM PST 24
Peak memory 199036 kb
Host smart-dfdb6fde-2113-47b0-8b90-716fedbd5012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013426935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1013426935
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2876347758
Short name T306
Test name
Test status
Simulation time 1791666945 ps
CPU time 101.78 seconds
Started Feb 07 03:31:05 PM PST 24
Finished Feb 07 03:32:47 PM PST 24
Peak memory 199048 kb
Host smart-25f248bf-efee-4a1d-b34a-852867603e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2876347758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2876347758
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2860172245
Short name T495
Test name
Test status
Simulation time 2898874885 ps
CPU time 50.15 seconds
Started Feb 07 03:31:11 PM PST 24
Finished Feb 07 03:32:02 PM PST 24
Peak memory 199048 kb
Host smart-6d922922-1be8-424d-b5ba-113ed09b2b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860172245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2860172245
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1068501125
Short name T358
Test name
Test status
Simulation time 360409985 ps
CPU time 19.88 seconds
Started Feb 07 03:31:05 PM PST 24
Finished Feb 07 03:31:25 PM PST 24
Peak memory 199068 kb
Host smart-3bb1a8d6-11e3-4db8-a929-55d1dfac3a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068501125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1068501125
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.182095067
Short name T334
Test name
Test status
Simulation time 1459108824 ps
CPU time 4.26 seconds
Started Feb 07 03:31:06 PM PST 24
Finished Feb 07 03:31:10 PM PST 24
Peak memory 198868 kb
Host smart-a537391f-e450-443c-9c7d-77a1c89c0b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182095067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.182095067
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1921358198
Short name T585
Test name
Test status
Simulation time 305848435360 ps
CPU time 1149.55 seconds
Started Feb 07 03:31:15 PM PST 24
Finished Feb 07 03:50:25 PM PST 24
Peak memory 240092 kb
Host smart-814e7faf-fa39-458a-9721-60bac5910455
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921358198 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1921358198
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2993612158
Short name T319
Test name
Test status
Simulation time 170287373861 ps
CPU time 742.2 seconds
Started Feb 07 03:31:19 PM PST 24
Finished Feb 07 03:43:42 PM PST 24
Peak memory 215372 kb
Host smart-49246cfe-4042-4666-be7b-287ccbc35af8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993612158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2993612158
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3524326385
Short name T359
Test name
Test status
Simulation time 58291846 ps
CPU time 1.11 seconds
Started Feb 07 03:31:12 PM PST 24
Finished Feb 07 03:31:14 PM PST 24
Peak memory 197416 kb
Host smart-abe5725b-86a6-42b4-bfe0-00d87e1ccb43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524326385 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3524326385
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3502069922
Short name T795
Test name
Test status
Simulation time 196501487262 ps
CPU time 458.97 seconds
Started Feb 07 03:31:16 PM PST 24
Finished Feb 07 03:38:55 PM PST 24
Peak memory 199108 kb
Host smart-65d90119-8cf3-451b-bf6b-0dc799552f6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502069922 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.3502069922
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.4186879964
Short name T838
Test name
Test status
Simulation time 423716973 ps
CPU time 16.94 seconds
Started Feb 07 03:31:18 PM PST 24
Finished Feb 07 03:31:36 PM PST 24
Peak memory 199052 kb
Host smart-aabd8d1a-bc24-405a-8e6f-57026dce310d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186879964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.4186879964
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1951911261
Short name T48
Test name
Test status
Simulation time 37574191 ps
CPU time 0.59 seconds
Started Feb 07 03:31:29 PM PST 24
Finished Feb 07 03:31:31 PM PST 24
Peak memory 193544 kb
Host smart-e7813f25-c8bc-46b7-b9c3-5583a692979e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951911261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1951911261
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2008730357
Short name T684
Test name
Test status
Simulation time 3871757571 ps
CPU time 33.29 seconds
Started Feb 07 03:31:20 PM PST 24
Finished Feb 07 03:31:54 PM PST 24
Peak memory 220652 kb
Host smart-cb0bae44-8c94-4c43-b23d-85f7cdff3cd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2008730357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2008730357
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3501451264
Short name T270
Test name
Test status
Simulation time 1480537312 ps
CPU time 5.64 seconds
Started Feb 07 03:31:21 PM PST 24
Finished Feb 07 03:31:27 PM PST 24
Peak memory 199008 kb
Host smart-11690ec2-0e64-41f7-959c-f8a60dca64a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501451264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3501451264
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1451132921
Short name T381
Test name
Test status
Simulation time 444841372 ps
CPU time 4.93 seconds
Started Feb 07 03:31:22 PM PST 24
Finished Feb 07 03:31:28 PM PST 24
Peak memory 199064 kb
Host smart-96c4ad0c-7396-4f56-9335-6d65ba20b891
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451132921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1451132921
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1625468184
Short name T1
Test name
Test status
Simulation time 5174667760 ps
CPU time 66.58 seconds
Started Feb 07 03:31:30 PM PST 24
Finished Feb 07 03:32:37 PM PST 24
Peak memory 199088 kb
Host smart-fd473d29-c8ec-4a06-855b-1c3989cfe3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625468184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1625468184
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.238698876
Short name T369
Test name
Test status
Simulation time 12896296144 ps
CPU time 72.56 seconds
Started Feb 07 03:31:20 PM PST 24
Finished Feb 07 03:32:33 PM PST 24
Peak memory 199080 kb
Host smart-e7feb000-2164-4b0b-91af-ebded0aa1c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238698876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.238698876
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4104287543
Short name T782
Test name
Test status
Simulation time 62982669 ps
CPU time 1.09 seconds
Started Feb 07 03:31:13 PM PST 24
Finished Feb 07 03:31:14 PM PST 24
Peak memory 197844 kb
Host smart-40387225-62ce-4e0b-a3ef-0e044c28fe11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104287543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4104287543
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2295799984
Short name T108
Test name
Test status
Simulation time 19930765775 ps
CPU time 380.64 seconds
Started Feb 07 03:31:32 PM PST 24
Finished Feb 07 03:37:53 PM PST 24
Peak memory 229820 kb
Host smart-a8e7b1f0-d392-4dcf-84ac-8a65ff695213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295799984 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2295799984
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_stress_all_with_rand_reset.3173089725
Short name T788
Test name
Test status
Simulation time 988514797396 ps
CPU time 2539.73 seconds
Started Feb 07 03:31:32 PM PST 24
Finished Feb 07 04:13:52 PM PST 24
Peak memory 241216 kb
Host smart-cd0e61ca-17b9-47f9-b35b-25a4ffb99b7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173089725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all_with_rand_reset.3173089725
Directory /workspace/44.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3821822200
Short name T837
Test name
Test status
Simulation time 33853250 ps
CPU time 1.21 seconds
Started Feb 07 03:31:33 PM PST 24
Finished Feb 07 03:31:35 PM PST 24
Peak memory 198068 kb
Host smart-624cdcf2-3eb9-4c62-86d6-a59fab26734a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821822200 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.3821822200
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2421336702
Short name T475
Test name
Test status
Simulation time 7469253233 ps
CPU time 394.87 seconds
Started Feb 07 03:31:32 PM PST 24
Finished Feb 07 03:38:07 PM PST 24
Peak memory 199164 kb
Host smart-95628ee3-4c23-4841-9b87-b129efb81f24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421336702 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.2421336702
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.3943897439
Short name T223
Test name
Test status
Simulation time 1308514590 ps
CPU time 4.9 seconds
Started Feb 07 03:31:28 PM PST 24
Finished Feb 07 03:31:35 PM PST 24
Peak memory 199104 kb
Host smart-b5852d32-5f7a-4928-a6fe-539732205c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943897439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.3943897439
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1657234442
Short name T545
Test name
Test status
Simulation time 38060674 ps
CPU time 0.57 seconds
Started Feb 07 03:31:40 PM PST 24
Finished Feb 07 03:31:41 PM PST 24
Peak memory 194484 kb
Host smart-b2c22b7c-b279-4857-8352-d463d40e185f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657234442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1657234442
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2159313990
Short name T512
Test name
Test status
Simulation time 954914428 ps
CPU time 10.07 seconds
Started Feb 07 03:31:34 PM PST 24
Finished Feb 07 03:31:45 PM PST 24
Peak memory 215424 kb
Host smart-2858e596-3fdd-4625-967a-431311ca4004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159313990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2159313990
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3698896382
Short name T221
Test name
Test status
Simulation time 2141100595 ps
CPU time 24.32 seconds
Started Feb 07 03:31:33 PM PST 24
Finished Feb 07 03:31:58 PM PST 24
Peak memory 199056 kb
Host smart-9e1358f6-b539-4b4c-96bd-e22ecc956912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698896382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3698896382
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3000682343
Short name T752
Test name
Test status
Simulation time 526291250 ps
CPU time 21.1 seconds
Started Feb 07 03:31:34 PM PST 24
Finished Feb 07 03:31:56 PM PST 24
Peak memory 199084 kb
Host smart-19d4ca4f-f688-478c-a3db-3419b3c74b7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000682343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3000682343
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2370789341
Short name T711
Test name
Test status
Simulation time 8975671042 ps
CPU time 143.57 seconds
Started Feb 07 03:31:35 PM PST 24
Finished Feb 07 03:33:59 PM PST 24
Peak memory 199044 kb
Host smart-91bad753-bd79-4144-a9fd-b14249f7a9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370789341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2370789341
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1974614866
Short name T228
Test name
Test status
Simulation time 5657618621 ps
CPU time 25.37 seconds
Started Feb 07 03:31:34 PM PST 24
Finished Feb 07 03:32:00 PM PST 24
Peak memory 199128 kb
Host smart-6abca5a6-d64b-4e26-af39-6d493b36190a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974614866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1974614866
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1525662832
Short name T468
Test name
Test status
Simulation time 61792236 ps
CPU time 1.84 seconds
Started Feb 07 03:31:30 PM PST 24
Finished Feb 07 03:31:32 PM PST 24
Peak memory 198880 kb
Host smart-fba98c9c-acf5-4f91-b26b-a4fd76ef401f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525662832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1525662832
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.4006686365
Short name T676
Test name
Test status
Simulation time 155474976796 ps
CPU time 672.67 seconds
Started Feb 07 03:31:40 PM PST 24
Finished Feb 07 03:42:53 PM PST 24
Peak memory 199104 kb
Host smart-2557bde2-bb53-4694-927e-7e117a540ef4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006686365 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.4006686365
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_stress_all_with_rand_reset.3600041845
Short name T121
Test name
Test status
Simulation time 67938268341 ps
CPU time 2588.61 seconds
Started Feb 07 03:31:39 PM PST 24
Finished Feb 07 04:14:49 PM PST 24
Peak memory 262628 kb
Host smart-e8c1c4b9-2a7e-4aea-b685-42d2f5cce772
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600041845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all_with_rand_reset.3600041845
Directory /workspace/45.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.4192091563
Short name T240
Test name
Test status
Simulation time 85021734 ps
CPU time 0.95 seconds
Started Feb 07 03:31:36 PM PST 24
Finished Feb 07 03:31:37 PM PST 24
Peak memory 196632 kb
Host smart-fec23c9b-22a2-415f-b1ac-785f1e612238
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192091563 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.4192091563
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.4276841396
Short name T517
Test name
Test status
Simulation time 113385390741 ps
CPU time 450.37 seconds
Started Feb 07 03:31:35 PM PST 24
Finished Feb 07 03:39:06 PM PST 24
Peak memory 198996 kb
Host smart-95644768-c8a5-41cf-8746-b8d7e7b064cf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276841396 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_sha_vectors.4276841396
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2821113476
Short name T246
Test name
Test status
Simulation time 1360389122 ps
CPU time 22.82 seconds
Started Feb 07 03:31:34 PM PST 24
Finished Feb 07 03:31:57 PM PST 24
Peak memory 198988 kb
Host smart-c54e5795-f9c8-43f4-b5de-30cf92c68d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821113476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2821113476
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.233341843
Short name T462
Test name
Test status
Simulation time 70288108 ps
CPU time 0.54 seconds
Started Feb 07 03:31:46 PM PST 24
Finished Feb 07 03:31:47 PM PST 24
Peak memory 193232 kb
Host smart-9bc3f50b-1976-4061-87a0-1299d17df8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233341843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.233341843
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1707544458
Short name T258
Test name
Test status
Simulation time 1386312731 ps
CPU time 45.05 seconds
Started Feb 07 03:31:40 PM PST 24
Finished Feb 07 03:32:25 PM PST 24
Peak memory 217480 kb
Host smart-6ecd6faa-7063-44ad-9667-07f15b718c36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1707544458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1707544458
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.126580663
Short name T625
Test name
Test status
Simulation time 518457267 ps
CPU time 22.49 seconds
Started Feb 07 03:31:44 PM PST 24
Finished Feb 07 03:32:07 PM PST 24
Peak memory 198844 kb
Host smart-6282846f-8a49-4567-a65c-4b526236d1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126580663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.126580663
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4184137751
Short name T679
Test name
Test status
Simulation time 1918294753 ps
CPU time 100.34 seconds
Started Feb 07 03:31:38 PM PST 24
Finished Feb 07 03:33:19 PM PST 24
Peak memory 199092 kb
Host smart-6cd8785e-dca3-4412-b045-e286cbe9ed39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4184137751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4184137751
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2013305515
Short name T254
Test name
Test status
Simulation time 942721197 ps
CPU time 48.34 seconds
Started Feb 07 03:31:43 PM PST 24
Finished Feb 07 03:32:32 PM PST 24
Peak memory 199024 kb
Host smart-6f8116fa-8f54-41bf-8b93-b5590d9f0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013305515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2013305515
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4199013463
Short name T208
Test name
Test status
Simulation time 7837856947 ps
CPU time 100.06 seconds
Started Feb 07 03:31:41 PM PST 24
Finished Feb 07 03:33:22 PM PST 24
Peak memory 199092 kb
Host smart-0774a130-ba40-4177-a803-5d521ae840b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199013463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4199013463
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3098172309
Short name T206
Test name
Test status
Simulation time 219770554 ps
CPU time 2.79 seconds
Started Feb 07 03:31:42 PM PST 24
Finished Feb 07 03:31:45 PM PST 24
Peak memory 199028 kb
Host smart-22066b0c-1b19-4378-94e7-1f3e6138a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098172309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3098172309
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.4098299367
Short name T715
Test name
Test status
Simulation time 23054672511 ps
CPU time 487.59 seconds
Started Feb 07 03:31:46 PM PST 24
Finished Feb 07 03:39:54 PM PST 24
Peak memory 239556 kb
Host smart-b8ce4e1b-7d79-4abd-baba-5b009ad34385
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098299367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.4098299367
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_stress_all_with_rand_reset.3556314053
Short name T465
Test name
Test status
Simulation time 52474260196 ps
CPU time 536.97 seconds
Started Feb 07 03:31:47 PM PST 24
Finished Feb 07 03:40:44 PM PST 24
Peak memory 223704 kb
Host smart-46fa4102-72c0-4763-857b-25dd314e9f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556314053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all_with_rand_reset.3556314053
Directory /workspace/46.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3414123468
Short name T802
Test name
Test status
Simulation time 242230331 ps
CPU time 1.17 seconds
Started Feb 07 03:31:43 PM PST 24
Finished Feb 07 03:31:44 PM PST 24
Peak memory 197464 kb
Host smart-c7b544e0-49d3-4562-8568-6be4dd7b7ab1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414123468 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3414123468
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2177186397
Short name T244
Test name
Test status
Simulation time 8039601309 ps
CPU time 376.16 seconds
Started Feb 07 03:31:44 PM PST 24
Finished Feb 07 03:38:00 PM PST 24
Peak memory 198872 kb
Host smart-d2a9fc4b-eb2a-4a84-97c9-c8f311bce8e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177186397 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.2177186397
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1567321401
Short name T390
Test name
Test status
Simulation time 4298708726 ps
CPU time 17.04 seconds
Started Feb 07 03:31:43 PM PST 24
Finished Feb 07 03:32:01 PM PST 24
Peak memory 198916 kb
Host smart-95a8e093-c3d7-49e6-8594-458e91c6df55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567321401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1567321401
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.2743858223
Short name T835
Test name
Test status
Simulation time 13201954 ps
CPU time 0.59 seconds
Started Feb 07 03:32:13 PM PST 24
Finished Feb 07 03:32:14 PM PST 24
Peak memory 194436 kb
Host smart-c262cf11-d3db-40fb-9b03-57a9980a1e24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743858223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.2743858223
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2647359523
Short name T431
Test name
Test status
Simulation time 1091657216 ps
CPU time 16.76 seconds
Started Feb 07 03:31:54 PM PST 24
Finished Feb 07 03:32:12 PM PST 24
Peak memory 223420 kb
Host smart-2c6dde83-4ef7-47a6-bda5-800a6352c6f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2647359523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2647359523
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.860695631
Short name T644
Test name
Test status
Simulation time 1879275271 ps
CPU time 36.74 seconds
Started Feb 07 03:31:54 PM PST 24
Finished Feb 07 03:32:32 PM PST 24
Peak memory 199080 kb
Host smart-5b17c506-e50a-4c16-84e2-9a6e9633c5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860695631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.860695631
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.807276903
Short name T774
Test name
Test status
Simulation time 3932295656 ps
CPU time 60.09 seconds
Started Feb 07 03:31:56 PM PST 24
Finished Feb 07 03:32:56 PM PST 24
Peak memory 199088 kb
Host smart-32ec2f3f-e8e5-46b5-98d7-a3e2bde35695
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807276903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.807276903
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.2176939625
Short name T797
Test name
Test status
Simulation time 11365759441 ps
CPU time 92.76 seconds
Started Feb 07 03:31:56 PM PST 24
Finished Feb 07 03:33:29 PM PST 24
Peak memory 199076 kb
Host smart-e32e1950-c781-4e99-8168-63d61e842c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176939625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.2176939625
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2711189880
Short name T846
Test name
Test status
Simulation time 20569576055 ps
CPU time 63.74 seconds
Started Feb 07 03:31:46 PM PST 24
Finished Feb 07 03:32:50 PM PST 24
Peak memory 199124 kb
Host smart-0515c4a0-4ba7-41f3-a536-93d078c0bf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711189880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2711189880
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.361157717
Short name T689
Test name
Test status
Simulation time 280784849 ps
CPU time 3.55 seconds
Started Feb 07 03:31:45 PM PST 24
Finished Feb 07 03:31:49 PM PST 24
Peak memory 199008 kb
Host smart-f4897b7c-2cb4-4ed7-98e1-66e704e30283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361157717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.361157717
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all_with_rand_reset.4189705446
Short name T380
Test name
Test status
Simulation time 149621478165 ps
CPU time 1206.45 seconds
Started Feb 07 03:32:02 PM PST 24
Finished Feb 07 03:52:09 PM PST 24
Peak memory 242144 kb
Host smart-ba9b5dc7-7d6a-4763-8941-d286dc297ef1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4189705446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all_with_rand_reset.4189705446
Directory /workspace/47.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1881061288
Short name T736
Test name
Test status
Simulation time 27408111 ps
CPU time 0.92 seconds
Started Feb 07 03:32:01 PM PST 24
Finished Feb 07 03:32:03 PM PST 24
Peak memory 196148 kb
Host smart-efdc9e83-f7ad-43bf-8589-7e8cd558b886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881061288 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1881061288
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.2868890340
Short name T266
Test name
Test status
Simulation time 41280275961 ps
CPU time 457.4 seconds
Started Feb 07 03:32:02 PM PST 24
Finished Feb 07 03:39:40 PM PST 24
Peak memory 199096 kb
Host smart-47cacdad-00b1-45a7-be98-bbfb09c83d8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868890340 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.2868890340
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.181997407
Short name T811
Test name
Test status
Simulation time 895250992 ps
CPU time 7.22 seconds
Started Feb 07 03:32:00 PM PST 24
Finished Feb 07 03:32:08 PM PST 24
Peak memory 199004 kb
Host smart-60838b70-b882-44c8-ab1e-d9040d55b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181997407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.181997407
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2959117225
Short name T420
Test name
Test status
Simulation time 31248662 ps
CPU time 0.56 seconds
Started Feb 07 03:32:18 PM PST 24
Finished Feb 07 03:32:19 PM PST 24
Peak memory 193472 kb
Host smart-4a96a115-c40d-4686-bbe9-ca3656a046ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959117225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2959117225
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1555644710
Short name T36
Test name
Test status
Simulation time 235112440 ps
CPU time 7.94 seconds
Started Feb 07 03:32:11 PM PST 24
Finished Feb 07 03:32:20 PM PST 24
Peak memory 214900 kb
Host smart-9d703d84-8069-4281-b30b-74139f1377d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1555644710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1555644710
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3255079990
Short name T265
Test name
Test status
Simulation time 1637999846 ps
CPU time 21.49 seconds
Started Feb 07 03:32:11 PM PST 24
Finished Feb 07 03:32:33 PM PST 24
Peak memory 199024 kb
Host smart-9aea4638-46fa-4fdd-94de-2c78065d8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255079990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3255079990
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.82234751
Short name T343
Test name
Test status
Simulation time 1422679857 ps
CPU time 41.35 seconds
Started Feb 07 03:32:14 PM PST 24
Finished Feb 07 03:32:56 PM PST 24
Peak memory 199072 kb
Host smart-22d0a9af-2ac6-42c5-97d5-dcf75a805545
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82234751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.82234751
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.4065788562
Short name T514
Test name
Test status
Simulation time 28152146 ps
CPU time 0.58 seconds
Started Feb 07 03:32:12 PM PST 24
Finished Feb 07 03:32:13 PM PST 24
Peak memory 193428 kb
Host smart-811eff8a-ce0f-4817-91cf-183774af1b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065788562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.4065788562
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3929356453
Short name T274
Test name
Test status
Simulation time 4563089728 ps
CPU time 57.54 seconds
Started Feb 07 03:32:16 PM PST 24
Finished Feb 07 03:33:14 PM PST 24
Peak memory 199088 kb
Host smart-61c22410-90bb-431f-8310-f1097507ecbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929356453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3929356453
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2523041297
Short name T216
Test name
Test status
Simulation time 589749037 ps
CPU time 3.21 seconds
Started Feb 07 03:32:12 PM PST 24
Finished Feb 07 03:32:15 PM PST 24
Peak memory 199048 kb
Host smart-c9095d17-6c29-4975-abc9-1b0e7e2270a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523041297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2523041297
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.4209409564
Short name T311
Test name
Test status
Simulation time 4238770939 ps
CPU time 164.03 seconds
Started Feb 07 03:32:12 PM PST 24
Finished Feb 07 03:34:57 PM PST 24
Peak memory 215540 kb
Host smart-fe616f87-a7e6-4d29-9aef-695e4174a1c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209409564 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.4209409564
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.327159059
Short name T574
Test name
Test status
Simulation time 362636616 ps
CPU time 0.86 seconds
Started Feb 07 03:32:13 PM PST 24
Finished Feb 07 03:32:14 PM PST 24
Peak memory 196020 kb
Host smart-f79558a9-1175-4e75-9db2-ad957ec0d427
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327159059 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.327159059
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2334298201
Short name T538
Test name
Test status
Simulation time 171621391357 ps
CPU time 461.65 seconds
Started Feb 07 03:32:13 PM PST 24
Finished Feb 07 03:39:56 PM PST 24
Peak memory 199112 kb
Host smart-83e6bde6-ad86-4376-8535-8196f9fa1032
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334298201 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.2334298201
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2237792002
Short name T700
Test name
Test status
Simulation time 1341073153 ps
CPU time 56.76 seconds
Started Feb 07 03:32:12 PM PST 24
Finished Feb 07 03:33:09 PM PST 24
Peak memory 199128 kb
Host smart-e0564078-60c9-400f-88e6-17f4a4bd9605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237792002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2237792002
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1302615658
Short name T328
Test name
Test status
Simulation time 55821262 ps
CPU time 0.58 seconds
Started Feb 07 03:32:18 PM PST 24
Finished Feb 07 03:32:19 PM PST 24
Peak memory 193472 kb
Host smart-21f7f543-8250-4cd8-b1f2-6cd979556f6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302615658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1302615658
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1739982787
Short name T836
Test name
Test status
Simulation time 1617882883 ps
CPU time 50.47 seconds
Started Feb 07 03:32:17 PM PST 24
Finished Feb 07 03:33:08 PM PST 24
Peak memory 209312 kb
Host smart-ec588729-d041-4764-a81f-547f7ecc63f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1739982787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1739982787
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1532985521
Short name T546
Test name
Test status
Simulation time 573485961 ps
CPU time 28.26 seconds
Started Feb 07 03:32:22 PM PST 24
Finished Feb 07 03:32:50 PM PST 24
Peak memory 199068 kb
Host smart-4feefe9f-2a8e-4857-80e0-7bd5e16a64b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532985521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1532985521
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4163869303
Short name T589
Test name
Test status
Simulation time 9595000294 ps
CPU time 136.34 seconds
Started Feb 07 03:32:19 PM PST 24
Finished Feb 07 03:34:36 PM PST 24
Peak memory 199088 kb
Host smart-1b1a6d24-7504-423d-9861-5d69eecfbe36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4163869303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4163869303
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.4019363556
Short name T218
Test name
Test status
Simulation time 35401821302 ps
CPU time 91.06 seconds
Started Feb 07 03:32:23 PM PST 24
Finished Feb 07 03:33:55 PM PST 24
Peak memory 199112 kb
Host smart-9ed53cab-b99e-4879-8adb-512a89618b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019363556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.4019363556
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.667818726
Short name T491
Test name
Test status
Simulation time 33137993206 ps
CPU time 68.71 seconds
Started Feb 07 03:32:16 PM PST 24
Finished Feb 07 03:33:26 PM PST 24
Peak memory 199068 kb
Host smart-e5f87966-0718-45ef-b1c5-f5052e5232b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667818726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.667818726
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.180889722
Short name T457
Test name
Test status
Simulation time 125654765 ps
CPU time 1.74 seconds
Started Feb 07 03:32:18 PM PST 24
Finished Feb 07 03:32:21 PM PST 24
Peak memory 199016 kb
Host smart-ca346114-1419-4694-ac5d-308c99121d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180889722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.180889722
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2014387093
Short name T680
Test name
Test status
Simulation time 30792701074 ps
CPU time 1537.04 seconds
Started Feb 07 03:32:17 PM PST 24
Finished Feb 07 03:57:54 PM PST 24
Peak memory 199140 kb
Host smart-58353d10-774f-40d1-a779-b017df549777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014387093 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2014387093
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_stress_all_with_rand_reset.1310457032
Short name T113
Test name
Test status
Simulation time 93578391176 ps
CPU time 2038.98 seconds
Started Feb 07 03:32:23 PM PST 24
Finished Feb 07 04:06:22 PM PST 24
Peak memory 246456 kb
Host smart-980cdbee-2c4b-4d8c-aa2f-f99d0b86a7fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1310457032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all_with_rand_reset.1310457032
Directory /workspace/49.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.765363487
Short name T810
Test name
Test status
Simulation time 113522175 ps
CPU time 1.18 seconds
Started Feb 07 03:32:21 PM PST 24
Finished Feb 07 03:32:23 PM PST 24
Peak memory 197568 kb
Host smart-9b3ef60a-eda7-4d79-aee9-66cef1427bba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765363487 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.765363487
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1959446702
Short name T361
Test name
Test status
Simulation time 38727425643 ps
CPU time 84.13 seconds
Started Feb 07 03:32:21 PM PST 24
Finished Feb 07 03:33:45 PM PST 24
Peak memory 199084 kb
Host smart-22168a2c-6dc3-417a-8779-6a02876512c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959446702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1959446702
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2944681583
Short name T479
Test name
Test status
Simulation time 40685685 ps
CPU time 0.59 seconds
Started Feb 07 03:24:40 PM PST 24
Finished Feb 07 03:24:41 PM PST 24
Peak memory 194424 kb
Host smart-98c06f44-a62c-4443-aabc-b5b819add98f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944681583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2944681583
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1238236862
Short name T708
Test name
Test status
Simulation time 4626376282 ps
CPU time 42.74 seconds
Started Feb 07 03:24:27 PM PST 24
Finished Feb 07 03:25:10 PM PST 24
Peak memory 226864 kb
Host smart-ba593449-8965-4ea2-80f9-a0395870b68b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1238236862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1238236862
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.126377307
Short name T400
Test name
Test status
Simulation time 2651731622 ps
CPU time 34.18 seconds
Started Feb 07 03:24:30 PM PST 24
Finished Feb 07 03:25:04 PM PST 24
Peak memory 199100 kb
Host smart-201dfd0f-5fba-4546-9ade-b86be77c5b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126377307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.126377307
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1508571401
Short name T235
Test name
Test status
Simulation time 2037537249 ps
CPU time 73.8 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:25:46 PM PST 24
Peak memory 199016 kb
Host smart-23c6d4cc-570a-4086-b97e-970481d198bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1508571401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1508571401
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.340883705
Short name T826
Test name
Test status
Simulation time 3477783716 ps
CPU time 47.09 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:25:20 PM PST 24
Peak memory 199088 kb
Host smart-f7143f90-548f-4ce9-9c11-6533ba861670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340883705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.340883705
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.161189703
Short name T503
Test name
Test status
Simulation time 3332796087 ps
CPU time 45.45 seconds
Started Feb 07 03:24:30 PM PST 24
Finished Feb 07 03:25:16 PM PST 24
Peak memory 199156 kb
Host smart-6b5bc9e5-dd63-41cd-871d-a35871cfa05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161189703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.161189703
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3797171215
Short name T499
Test name
Test status
Simulation time 140941438 ps
CPU time 1.8 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:24:35 PM PST 24
Peak memory 198960 kb
Host smart-75fa7ab5-41a7-4703-ba37-3f1ee380af61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797171215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3797171215
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.937819668
Short name T588
Test name
Test status
Simulation time 20223253520 ps
CPU time 975.48 seconds
Started Feb 07 03:24:33 PM PST 24
Finished Feb 07 03:40:49 PM PST 24
Peak memory 241168 kb
Host smart-ddbb23e4-bf6b-4267-b3ea-6cc21f6f7552
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937819668 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.937819668
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all_with_rand_reset.2491837723
Short name T303
Test name
Test status
Simulation time 117942540438 ps
CPU time 1377.56 seconds
Started Feb 07 03:24:35 PM PST 24
Finished Feb 07 03:47:34 PM PST 24
Peak memory 214972 kb
Host smart-02cc0509-2b1b-4690-9b3f-47aa0131e325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2491837723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all_with_rand_reset.2491837723
Directory /workspace/5.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4264485522
Short name T455
Test name
Test status
Simulation time 85647031 ps
CPU time 0.93 seconds
Started Feb 07 03:24:37 PM PST 24
Finished Feb 07 03:24:38 PM PST 24
Peak memory 195932 kb
Host smart-4343d789-1b91-4ca4-901d-d6c914921639
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264485522 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.4264485522
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2617231332
Short name T220
Test name
Test status
Simulation time 7262605449 ps
CPU time 380.21 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:30:53 PM PST 24
Peak memory 199180 kb
Host smart-aa8c51de-7cb9-4c44-85f5-cdea707d5081
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617231332 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.2617231332
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2450870122
Short name T237
Test name
Test status
Simulation time 1317393373 ps
CPU time 18.41 seconds
Started Feb 07 03:24:32 PM PST 24
Finished Feb 07 03:24:52 PM PST 24
Peak memory 199056 kb
Host smart-a713a43e-d06a-41c7-8fb1-439e1a6650c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450870122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2450870122
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/50.hmac_stress_all_with_rand_reset.1220266427
Short name T756
Test name
Test status
Simulation time 55416381263 ps
CPU time 423.97 seconds
Started Feb 07 03:32:29 PM PST 24
Finished Feb 07 03:39:33 PM PST 24
Peak memory 223764 kb
Host smart-ce72b517-07f3-47f4-bde4-75663df63311
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220266427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.hmac_stress_all_with_rand_reset.1220266427
Directory /workspace/50.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.4077306310
Short name T227
Test name
Test status
Simulation time 88232365056 ps
CPU time 407.94 seconds
Started Feb 07 03:32:27 PM PST 24
Finished Feb 07 03:39:15 PM PST 24
Peak memory 215576 kb
Host smart-67d4fa45-2767-413e-ae9f-6af64526f6f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4077306310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.4077306310
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.hmac_stress_all_with_rand_reset.2299394326
Short name T566
Test name
Test status
Simulation time 48528289322 ps
CPU time 1884.76 seconds
Started Feb 07 03:32:25 PM PST 24
Finished Feb 07 04:03:51 PM PST 24
Peak memory 256476 kb
Host smart-03902aa3-77b0-4b5a-99ae-72b59d813c5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299394326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.hmac_stress_all_with_rand_reset.2299394326
Directory /workspace/52.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2679173312
Short name T559
Test name
Test status
Simulation time 132252195687 ps
CPU time 653.17 seconds
Started Feb 07 03:32:26 PM PST 24
Finished Feb 07 03:43:20 PM PST 24
Peak memory 214716 kb
Host smart-3f64cb7a-5aab-41a3-9911-193c1f7992d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2679173312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2679173312
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.hmac_stress_all_with_rand_reset.791045326
Short name T621
Test name
Test status
Simulation time 56444294174 ps
CPU time 1835.11 seconds
Started Feb 07 03:32:26 PM PST 24
Finished Feb 07 04:03:02 PM PST 24
Peak memory 257384 kb
Host smart-4547e7b3-6c68-4916-9e7f-fdc82960fa56
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=791045326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.hmac_stress_all_with_rand_reset.791045326
Directory /workspace/54.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.hmac_stress_all_with_rand_reset.214627326
Short name T840
Test name
Test status
Simulation time 70889662788 ps
CPU time 301.05 seconds
Started Feb 07 03:32:26 PM PST 24
Finished Feb 07 03:37:27 PM PST 24
Peak memory 207408 kb
Host smart-365e1148-5186-45d4-afec-9df7a3f01b09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=214627326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.hmac_stress_all_with_rand_reset.214627326
Directory /workspace/55.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.hmac_stress_all_with_rand_reset.338336084
Short name T749
Test name
Test status
Simulation time 170499418789 ps
CPU time 441.99 seconds
Started Feb 07 03:32:26 PM PST 24
Finished Feb 07 03:39:48 PM PST 24
Peak memory 247396 kb
Host smart-1ef9988b-c3ac-4e8e-a34c-7a7bac9fa6c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338336084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.hmac_stress_all_with_rand_reset.338336084
Directory /workspace/56.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.2064749975
Short name T114
Test name
Test status
Simulation time 59336067035 ps
CPU time 818.34 seconds
Started Feb 07 03:32:31 PM PST 24
Finished Feb 07 03:46:13 PM PST 24
Peak memory 240116 kb
Host smart-78af2954-2ecc-436c-a1b3-33ab876178bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2064749975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.2064749975
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.hmac_stress_all_with_rand_reset.487124228
Short name T567
Test name
Test status
Simulation time 138659080725 ps
CPU time 4387.28 seconds
Started Feb 07 03:32:33 PM PST 24
Finished Feb 07 04:45:43 PM PST 24
Peak memory 259108 kb
Host smart-cac24ac3-607c-49ba-b223-7a5845071266
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487124228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.hmac_stress_all_with_rand_reset.487124228
Directory /workspace/58.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2812624799
Short name T498
Test name
Test status
Simulation time 12711619 ps
CPU time 0.57 seconds
Started Feb 07 03:24:48 PM PST 24
Finished Feb 07 03:24:49 PM PST 24
Peak memory 193436 kb
Host smart-ad265362-ee43-4ba2-b218-75b5b8a7231f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812624799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2812624799
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3905408647
Short name T542
Test name
Test status
Simulation time 1521336918 ps
CPU time 22.7 seconds
Started Feb 07 03:24:42 PM PST 24
Finished Feb 07 03:25:05 PM PST 24
Peak memory 207176 kb
Host smart-e43ae8f1-60ea-4323-a4e5-91f885b9bb9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3905408647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3905408647
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3615601533
Short name T388
Test name
Test status
Simulation time 499496913 ps
CPU time 23.15 seconds
Started Feb 07 03:24:43 PM PST 24
Finished Feb 07 03:25:06 PM PST 24
Peak memory 198996 kb
Host smart-4fafe8b9-83fc-433f-a03b-ef51c6d3ea6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615601533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3615601533
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.124472953
Short name T809
Test name
Test status
Simulation time 1318024859 ps
CPU time 69.32 seconds
Started Feb 07 03:24:46 PM PST 24
Finished Feb 07 03:25:55 PM PST 24
Peak memory 199004 kb
Host smart-17fe731f-1840-4441-b4eb-af5d59923c0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=124472953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.124472953
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.780497683
Short name T781
Test name
Test status
Simulation time 22161370818 ps
CPU time 92.6 seconds
Started Feb 07 03:24:42 PM PST 24
Finished Feb 07 03:26:16 PM PST 24
Peak memory 199060 kb
Host smart-7536bc58-963e-4197-a01a-c8b1d13f06e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780497683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.780497683
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2713028709
Short name T360
Test name
Test status
Simulation time 15905924233 ps
CPU time 69.17 seconds
Started Feb 07 03:24:46 PM PST 24
Finished Feb 07 03:25:55 PM PST 24
Peak memory 199064 kb
Host smart-b66cc32b-3f05-4494-b596-9c67a81104a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713028709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2713028709
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1927881689
Short name T755
Test name
Test status
Simulation time 56290446 ps
CPU time 1.08 seconds
Started Feb 07 03:24:43 PM PST 24
Finished Feb 07 03:24:45 PM PST 24
Peak memory 198644 kb
Host smart-79272db1-addd-44d4-8864-ea752afcda9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927881689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1927881689
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1608407983
Short name T234
Test name
Test status
Simulation time 28673157956 ps
CPU time 449.05 seconds
Started Feb 07 03:24:49 PM PST 24
Finished Feb 07 03:32:18 PM PST 24
Peak memory 199120 kb
Host smart-ba6fa750-989d-4d70-a22a-2c7e73ab60a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608407983 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1608407983
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2695290407
Short name T780
Test name
Test status
Simulation time 25537024994 ps
CPU time 1087.36 seconds
Started Feb 07 03:24:48 PM PST 24
Finished Feb 07 03:42:56 PM PST 24
Peak memory 246580 kb
Host smart-3ce70a46-d6d2-44f4-9f0f-43982a23cddd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695290407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2695290407
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2010319696
Short name T576
Test name
Test status
Simulation time 67274617 ps
CPU time 1.06 seconds
Started Feb 07 03:24:44 PM PST 24
Finished Feb 07 03:24:46 PM PST 24
Peak memory 196428 kb
Host smart-d875501d-45e6-4a4b-973b-fea5ce381b15
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010319696 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2010319696
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1151132467
Short name T204
Test name
Test status
Simulation time 86355200836 ps
CPU time 509.24 seconds
Started Feb 07 03:24:45 PM PST 24
Finished Feb 07 03:33:15 PM PST 24
Peak memory 199148 kb
Host smart-274a9f04-3914-4f8d-bc9d-1889872e88f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151132467 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.hmac_test_sha_vectors.1151132467
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2885071493
Short name T478
Test name
Test status
Simulation time 17145396046 ps
CPU time 54.22 seconds
Started Feb 07 03:24:36 PM PST 24
Finished Feb 07 03:25:31 PM PST 24
Peak memory 199092 kb
Host smart-46344a21-b2bb-49ad-8cce-db23f345e36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885071493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2885071493
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/60.hmac_stress_all_with_rand_reset.451711139
Short name T99
Test name
Test status
Simulation time 726228240709 ps
CPU time 852.99 seconds
Started Feb 07 03:32:29 PM PST 24
Finished Feb 07 03:46:43 PM PST 24
Peak memory 247944 kb
Host smart-a329e06d-cad7-494d-81ec-0bf9dccf652b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451711139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.hmac_stress_all_with_rand_reset.451711139
Directory /workspace/60.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.hmac_stress_all_with_rand_reset.2762750922
Short name T131
Test name
Test status
Simulation time 178405387882 ps
CPU time 2814.16 seconds
Started Feb 07 03:32:31 PM PST 24
Finished Feb 07 04:19:29 PM PST 24
Peak memory 254736 kb
Host smart-5f76b8cc-20df-45b4-be0e-096d98228175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762750922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.hmac_stress_all_with_rand_reset.2762750922
Directory /workspace/61.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.hmac_stress_all_with_rand_reset.193904746
Short name T295
Test name
Test status
Simulation time 93209995400 ps
CPU time 815.92 seconds
Started Feb 07 03:32:31 PM PST 24
Finished Feb 07 03:46:11 PM PST 24
Peak memory 223720 kb
Host smart-6114369e-ab44-4f2a-af90-fc1bda1429fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193904746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.hmac_stress_all_with_rand_reset.193904746
Directory /workspace/62.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.hmac_stress_all_with_rand_reset.4158466917
Short name T732
Test name
Test status
Simulation time 130151248754 ps
CPU time 614.22 seconds
Started Feb 07 03:32:31 PM PST 24
Finished Feb 07 03:42:49 PM PST 24
Peak memory 223780 kb
Host smart-26f3a090-4ae9-4148-9fa7-71e9aa1255aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158466917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.hmac_stress_all_with_rand_reset.4158466917
Directory /workspace/64.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.hmac_stress_all_with_rand_reset.1116759730
Short name T256
Test name
Test status
Simulation time 15135177903 ps
CPU time 803.55 seconds
Started Feb 07 03:32:41 PM PST 24
Finished Feb 07 03:46:08 PM PST 24
Peak memory 215584 kb
Host smart-e8511a50-526c-40de-8a21-0ecc7ec78fe9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116759730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.hmac_stress_all_with_rand_reset.1116759730
Directory /workspace/65.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.hmac_stress_all_with_rand_reset.3440464278
Short name T804
Test name
Test status
Simulation time 852521793979 ps
CPU time 893.96 seconds
Started Feb 07 03:32:40 PM PST 24
Finished Feb 07 03:47:38 PM PST 24
Peak memory 212940 kb
Host smart-60651621-ec4b-4b78-b31e-82f1352a442c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440464278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.hmac_stress_all_with_rand_reset.3440464278
Directory /workspace/66.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.hmac_stress_all_with_rand_reset.1415032339
Short name T557
Test name
Test status
Simulation time 72985749466 ps
CPU time 1045.73 seconds
Started Feb 07 03:32:37 PM PST 24
Finished Feb 07 03:50:05 PM PST 24
Peak memory 247348 kb
Host smart-816cfc2c-b340-43ea-a95b-6e871e3247c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415032339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.hmac_stress_all_with_rand_reset.1415032339
Directory /workspace/67.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.hmac_stress_all_with_rand_reset.2919445490
Short name T368
Test name
Test status
Simulation time 160852840517 ps
CPU time 3717.57 seconds
Started Feb 07 03:32:38 PM PST 24
Finished Feb 07 04:34:37 PM PST 24
Peak memory 257756 kb
Host smart-33f646c3-fe08-4d56-891f-56e33d2ffe11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919445490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.hmac_stress_all_with_rand_reset.2919445490
Directory /workspace/68.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.2075892906
Short name T731
Test name
Test status
Simulation time 69530479216 ps
CPU time 1367.08 seconds
Started Feb 07 03:32:39 PM PST 24
Finished Feb 07 03:55:27 PM PST 24
Peak memory 246456 kb
Host smart-d9a69297-fcf6-406d-91c7-6dd72e9605d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2075892906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.2075892906
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4100164686
Short name T668
Test name
Test status
Simulation time 14484843 ps
CPU time 0.54 seconds
Started Feb 07 03:25:15 PM PST 24
Finished Feb 07 03:25:16 PM PST 24
Peak memory 193240 kb
Host smart-fa681c5e-2d3d-44ba-9e7b-55611abd9756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100164686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4100164686
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.961413413
Short name T496
Test name
Test status
Simulation time 1873536489 ps
CPU time 30.46 seconds
Started Feb 07 03:24:48 PM PST 24
Finished Feb 07 03:25:19 PM PST 24
Peak memory 214468 kb
Host smart-67814cb1-3a5b-4069-8a92-018722c7a16f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961413413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.961413413
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.740590386
Short name T733
Test name
Test status
Simulation time 398225404 ps
CPU time 18.25 seconds
Started Feb 07 03:24:46 PM PST 24
Finished Feb 07 03:25:05 PM PST 24
Peak memory 199020 kb
Host smart-5cbbe10a-632e-4245-9198-d6199d68d168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740590386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.740590386
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2068936657
Short name T249
Test name
Test status
Simulation time 318439260 ps
CPU time 4.33 seconds
Started Feb 07 03:24:51 PM PST 24
Finished Feb 07 03:24:55 PM PST 24
Peak memory 198980 kb
Host smart-b812bef3-598f-4eef-9bc1-62fd50272b76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068936657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2068936657
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2704044088
Short name T42
Test name
Test status
Simulation time 5059506780 ps
CPU time 23.08 seconds
Started Feb 07 03:25:01 PM PST 24
Finished Feb 07 03:25:24 PM PST 24
Peak memory 199056 kb
Host smart-72164f24-baba-4807-b852-b722f7055114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704044088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2704044088
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.23433854
Short name T784
Test name
Test status
Simulation time 205690875 ps
CPU time 10.94 seconds
Started Feb 07 03:24:43 PM PST 24
Finished Feb 07 03:24:55 PM PST 24
Peak memory 199088 kb
Host smart-de84f9e1-e52b-423e-b94b-da9f7840ccef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23433854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.23433854
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.1590632004
Short name T9
Test name
Test status
Simulation time 837302151 ps
CPU time 2.48 seconds
Started Feb 07 03:24:46 PM PST 24
Finished Feb 07 03:24:49 PM PST 24
Peak memory 199052 kb
Host smart-93c30716-d069-4a04-85c7-dc7dddd8a196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590632004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1590632004
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.249910160
Short name T817
Test name
Test status
Simulation time 214171839211 ps
CPU time 1814.79 seconds
Started Feb 07 03:25:13 PM PST 24
Finished Feb 07 03:55:29 PM PST 24
Peak memory 199112 kb
Host smart-0c5e6c86-87ae-4f22-a92b-14daf4d6f12e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249910160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.249910160
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_stress_all_with_rand_reset.302147318
Short name T789
Test name
Test status
Simulation time 560351007662 ps
CPU time 2691.19 seconds
Started Feb 07 03:25:16 PM PST 24
Finished Feb 07 04:10:07 PM PST 24
Peak memory 227300 kb
Host smart-118bfb09-b0ac-45f2-9c5e-b4f4eb77c9bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302147318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all_with_rand_reset.302147318
Directory /workspace/7.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2594656666
Short name T222
Test name
Test status
Simulation time 607754200 ps
CPU time 0.94 seconds
Started Feb 07 03:25:01 PM PST 24
Finished Feb 07 03:25:03 PM PST 24
Peak memory 196320 kb
Host smart-fbc4308e-db77-4866-aba7-13add74f3313
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594656666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2594656666
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.196760923
Short name T758
Test name
Test status
Simulation time 12891465492 ps
CPU time 400.81 seconds
Started Feb 07 03:25:01 PM PST 24
Finished Feb 07 03:31:42 PM PST 24
Peak memory 199148 kb
Host smart-c092dbb1-3b3f-44d5-9a17-5c6e00de6f59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196760923 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.196760923
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1923470249
Short name T747
Test name
Test status
Simulation time 1068060013 ps
CPU time 26.82 seconds
Started Feb 07 03:25:04 PM PST 24
Finished Feb 07 03:25:31 PM PST 24
Peak memory 199072 kb
Host smart-b7c0f5fd-9e87-4c98-98d8-454605e94f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923470249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1923470249
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.2234031424
Short name T407
Test name
Test status
Simulation time 316845690185 ps
CPU time 2778.67 seconds
Started Feb 07 03:32:40 PM PST 24
Finished Feb 07 04:18:59 PM PST 24
Peak memory 226952 kb
Host smart-5904accd-2770-499b-96ea-4184ddf710d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2234031424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.2234031424
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.hmac_stress_all_with_rand_reset.1761786288
Short name T123
Test name
Test status
Simulation time 229791360087 ps
CPU time 517.71 seconds
Started Feb 07 03:32:40 PM PST 24
Finished Feb 07 03:41:22 PM PST 24
Peak memory 224848 kb
Host smart-2642f49a-af12-4efb-8401-dd90d76eff9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1761786288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.hmac_stress_all_with_rand_reset.1761786288
Directory /workspace/71.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.hmac_stress_all_with_rand_reset.270041620
Short name T791
Test name
Test status
Simulation time 116396836518 ps
CPU time 1382.17 seconds
Started Feb 07 03:32:39 PM PST 24
Finished Feb 07 03:55:42 PM PST 24
Peak memory 248272 kb
Host smart-dee30b6f-0418-49f3-be06-600674282c3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270041620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.hmac_stress_all_with_rand_reset.270041620
Directory /workspace/72.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.hmac_stress_all_with_rand_reset.4006652437
Short name T583
Test name
Test status
Simulation time 100343436122 ps
CPU time 479.98 seconds
Started Feb 07 03:32:38 PM PST 24
Finished Feb 07 03:40:39 PM PST 24
Peak memory 246072 kb
Host smart-1ce884fc-c14f-4cf6-bc92-debc624fead1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4006652437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.hmac_stress_all_with_rand_reset.4006652437
Directory /workspace/73.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.hmac_stress_all_with_rand_reset.1567787890
Short name T486
Test name
Test status
Simulation time 38175697104 ps
CPU time 1698.56 seconds
Started Feb 07 03:32:51 PM PST 24
Finished Feb 07 04:01:11 PM PST 24
Peak memory 240036 kb
Host smart-730cf19b-ee62-4ffb-a0d3-88b1984a8fb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567787890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.hmac_stress_all_with_rand_reset.1567787890
Directory /workspace/74.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.hmac_stress_all_with_rand_reset.2171542621
Short name T613
Test name
Test status
Simulation time 385732487933 ps
CPU time 662.77 seconds
Started Feb 07 03:32:57 PM PST 24
Finished Feb 07 03:44:04 PM PST 24
Peak memory 247728 kb
Host smart-3f7f5e39-d9d9-4039-b9a1-d85d7fdec5b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2171542621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.hmac_stress_all_with_rand_reset.2171542621
Directory /workspace/75.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.hmac_stress_all_with_rand_reset.198992385
Short name T133
Test name
Test status
Simulation time 152135177001 ps
CPU time 1243.89 seconds
Started Feb 07 03:32:54 PM PST 24
Finished Feb 07 03:53:39 PM PST 24
Peak memory 230032 kb
Host smart-a6344bd9-8a72-4481-8ebd-d21283efadbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198992385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.hmac_stress_all_with_rand_reset.198992385
Directory /workspace/76.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.hmac_stress_all_with_rand_reset.3880681070
Short name T347
Test name
Test status
Simulation time 98605925499 ps
CPU time 761.96 seconds
Started Feb 07 03:32:46 PM PST 24
Finished Feb 07 03:45:30 PM PST 24
Peak memory 243944 kb
Host smart-d3babe7f-8f89-44b7-a21f-363d46fd1d84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3880681070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.hmac_stress_all_with_rand_reset.3880681070
Directory /workspace/77.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.hmac_stress_all_with_rand_reset.2003545114
Short name T772
Test name
Test status
Simulation time 71376261340 ps
CPU time 3617.28 seconds
Started Feb 07 03:32:45 PM PST 24
Finished Feb 07 04:33:04 PM PST 24
Peak memory 243220 kb
Host smart-bb8816f0-d56a-4ea4-bbbf-26d54e823e4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003545114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.hmac_stress_all_with_rand_reset.2003545114
Directory /workspace/78.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.1028785566
Short name T445
Test name
Test status
Simulation time 318232487923 ps
CPU time 3558.89 seconds
Started Feb 07 03:32:52 PM PST 24
Finished Feb 07 04:32:12 PM PST 24
Peak memory 264640 kb
Host smart-968707ae-b26b-48a8-90bb-18494ecd4aad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1028785566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.1028785566
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.4279349284
Short name T661
Test name
Test status
Simulation time 96570425 ps
CPU time 0.58 seconds
Started Feb 07 03:25:14 PM PST 24
Finished Feb 07 03:25:15 PM PST 24
Peak memory 193432 kb
Host smart-544c643c-70aa-426c-b1a2-fa5a2bcfb0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279349284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.4279349284
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.3624742936
Short name T317
Test name
Test status
Simulation time 561474962 ps
CPU time 17.21 seconds
Started Feb 07 03:25:15 PM PST 24
Finished Feb 07 03:25:32 PM PST 24
Peak memory 207232 kb
Host smart-00466614-90b0-467a-9444-67dd7e5ba2cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624742936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.3624742936
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.28863830
Short name T290
Test name
Test status
Simulation time 15406596825 ps
CPU time 58.64 seconds
Started Feb 07 03:25:16 PM PST 24
Finished Feb 07 03:26:15 PM PST 24
Peak memory 199096 kb
Host smart-28967829-2eee-4e12-aba7-31fda959862f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28863830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.28863830
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1878338897
Short name T442
Test name
Test status
Simulation time 6105902530 ps
CPU time 75.53 seconds
Started Feb 07 03:25:13 PM PST 24
Finished Feb 07 03:26:30 PM PST 24
Peak memory 199152 kb
Host smart-19d0a197-df8a-4500-a882-38ae0d8e9594
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1878338897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1878338897
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2077183921
Short name T724
Test name
Test status
Simulation time 2124271689 ps
CPU time 109.13 seconds
Started Feb 07 03:25:14 PM PST 24
Finished Feb 07 03:27:04 PM PST 24
Peak memory 199032 kb
Host smart-426ee63a-c049-40fe-aa92-055431c812b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077183921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2077183921
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.564571331
Short name T843
Test name
Test status
Simulation time 1761712670 ps
CPU time 33.52 seconds
Started Feb 07 03:25:15 PM PST 24
Finished Feb 07 03:25:49 PM PST 24
Peak memory 199112 kb
Host smart-2bdbecea-230f-41d0-81f5-bf739798d32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564571331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.564571331
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3947007329
Short name T685
Test name
Test status
Simulation time 94190610 ps
CPU time 1.46 seconds
Started Feb 07 03:25:09 PM PST 24
Finished Feb 07 03:25:11 PM PST 24
Peak memory 199012 kb
Host smart-b7aca428-e93c-4414-bcbd-b701f64623b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947007329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3947007329
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.526581931
Short name T39
Test name
Test status
Simulation time 6632499474 ps
CPU time 285.1 seconds
Started Feb 07 03:25:24 PM PST 24
Finished Feb 07 03:30:10 PM PST 24
Peak memory 239240 kb
Host smart-89126a0b-5a5a-4d2a-b634-de7f1de8a971
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526581931 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.526581931
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_stress_all_with_rand_reset.643045154
Short name T716
Test name
Test status
Simulation time 42548962116 ps
CPU time 911.55 seconds
Started Feb 07 03:25:14 PM PST 24
Finished Feb 07 03:40:26 PM PST 24
Peak memory 235004 kb
Host smart-bda98030-befb-461c-aee6-1637e032479e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643045154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all_with_rand_reset.643045154
Directory /workspace/8.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.641923080
Short name T11
Test name
Test status
Simulation time 34401466 ps
CPU time 1.11 seconds
Started Feb 07 03:25:13 PM PST 24
Finished Feb 07 03:25:15 PM PST 24
Peak memory 197592 kb
Host smart-12bb5789-71ec-47db-8977-6efce7beb8be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641923080 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.641923080
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3652057825
Short name T340
Test name
Test status
Simulation time 39568386105 ps
CPU time 460.84 seconds
Started Feb 07 03:25:14 PM PST 24
Finished Feb 07 03:32:55 PM PST 24
Peak memory 199120 kb
Host smart-ab98845f-788c-4434-a159-dc4be2d9fbf7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652057825 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.3652057825
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1440432975
Short name T773
Test name
Test status
Simulation time 1162953935 ps
CPU time 17.06 seconds
Started Feb 07 03:25:18 PM PST 24
Finished Feb 07 03:25:35 PM PST 24
Peak memory 198976 kb
Host smart-511e8814-15a1-4050-ba16-e935c21b1160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440432975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1440432975
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/80.hmac_stress_all_with_rand_reset.2659491483
Short name T409
Test name
Test status
Simulation time 175162983493 ps
CPU time 842.55 seconds
Started Feb 07 03:32:47 PM PST 24
Finished Feb 07 03:46:50 PM PST 24
Peak memory 223820 kb
Host smart-a7faf76d-ff91-4047-bcad-6c2e89816e32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659491483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.hmac_stress_all_with_rand_reset.2659491483
Directory /workspace/80.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.hmac_stress_all_with_rand_reset.4228664960
Short name T556
Test name
Test status
Simulation time 382759108342 ps
CPU time 6495.48 seconds
Started Feb 07 03:32:47 PM PST 24
Finished Feb 07 05:21:04 PM PST 24
Peak memory 263992 kb
Host smart-c45cfc0b-c898-48f1-87bb-a65d0b22e0a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228664960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.hmac_stress_all_with_rand_reset.4228664960
Directory /workspace/81.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.hmac_stress_all_with_rand_reset.222689887
Short name T682
Test name
Test status
Simulation time 76949787685 ps
CPU time 1154.78 seconds
Started Feb 07 03:33:04 PM PST 24
Finished Feb 07 03:52:21 PM PST 24
Peak memory 256560 kb
Host smart-dc4da256-64b8-47be-9695-457a920ea965
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=222689887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.hmac_stress_all_with_rand_reset.222689887
Directory /workspace/82.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.hmac_stress_all_with_rand_reset.2524225641
Short name T59
Test name
Test status
Simulation time 25915362889 ps
CPU time 510 seconds
Started Feb 07 03:33:00 PM PST 24
Finished Feb 07 03:41:33 PM PST 24
Peak memory 231964 kb
Host smart-e812a808-5d58-40ca-8a8b-7095dc14cb0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524225641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.hmac_stress_all_with_rand_reset.2524225641
Directory /workspace/83.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.hmac_stress_all_with_rand_reset.3283059783
Short name T723
Test name
Test status
Simulation time 48306796101 ps
CPU time 2388.81 seconds
Started Feb 07 03:32:59 PM PST 24
Finished Feb 07 04:12:52 PM PST 24
Peak memory 223736 kb
Host smart-dc374c6d-1775-435b-b2ab-254d3caf7ac6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3283059783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.hmac_stress_all_with_rand_reset.3283059783
Directory /workspace/84.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.hmac_stress_all_with_rand_reset.1150866156
Short name T271
Test name
Test status
Simulation time 124399346422 ps
CPU time 467.84 seconds
Started Feb 07 03:32:58 PM PST 24
Finished Feb 07 03:40:50 PM PST 24
Peak memory 231940 kb
Host smart-c3c5b511-d18a-4d53-8b75-9ea6f8677b7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1150866156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.hmac_stress_all_with_rand_reset.1150866156
Directory /workspace/85.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.hmac_stress_all_with_rand_reset.1729234476
Short name T140
Test name
Test status
Simulation time 26768366067 ps
CPU time 963.73 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 03:49:09 PM PST 24
Peak memory 237256 kb
Host smart-3be40f50-8a49-4535-9e32-d5fcfa75fdeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1729234476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.hmac_stress_all_with_rand_reset.1729234476
Directory /workspace/86.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.hmac_stress_all_with_rand_reset.1975810143
Short name T707
Test name
Test status
Simulation time 118865965910 ps
CPU time 2226.68 seconds
Started Feb 07 03:33:01 PM PST 24
Finished Feb 07 04:10:10 PM PST 24
Peak memory 256532 kb
Host smart-1bc1f6d7-a36b-41b4-8c71-a108b1dfd453
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975810143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.hmac_stress_all_with_rand_reset.1975810143
Directory /workspace/87.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.hmac_stress_all_with_rand_reset.3055193824
Short name T728
Test name
Test status
Simulation time 184223116490 ps
CPU time 334.98 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 03:38:39 PM PST 24
Peak memory 242084 kb
Host smart-fc52c060-da4b-4f82-b5a2-cf236737495e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3055193824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.hmac_stress_all_with_rand_reset.3055193824
Directory /workspace/88.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.3794509100
Short name T748
Test name
Test status
Simulation time 108964044961 ps
CPU time 1521.69 seconds
Started Feb 07 03:33:11 PM PST 24
Finished Feb 07 03:58:34 PM PST 24
Peak memory 247308 kb
Host smart-e768d99c-1fa0-4271-a952-55a137decb28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3794509100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.3794509100
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1984604966
Short name T300
Test name
Test status
Simulation time 14863544 ps
CPU time 0.58 seconds
Started Feb 07 03:25:27 PM PST 24
Finished Feb 07 03:25:28 PM PST 24
Peak memory 193392 kb
Host smart-6e59f877-c7fa-4fc7-a4fa-598572cec072
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984604966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1984604966
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.3730300469
Short name T428
Test name
Test status
Simulation time 2108456862 ps
CPU time 18.18 seconds
Started Feb 07 03:25:16 PM PST 24
Finished Feb 07 03:25:35 PM PST 24
Peak memory 230796 kb
Host smart-cebc6183-f849-4d59-a783-fe4bb412d1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3730300469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.3730300469
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.332255306
Short name T638
Test name
Test status
Simulation time 4052493812 ps
CPU time 46.16 seconds
Started Feb 07 03:25:20 PM PST 24
Finished Feb 07 03:26:07 PM PST 24
Peak memory 199088 kb
Host smart-bf678ae5-e73f-4001-b900-41ee48bfac7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332255306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.332255306
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1633660913
Short name T651
Test name
Test status
Simulation time 9054491881 ps
CPU time 116.34 seconds
Started Feb 07 03:25:19 PM PST 24
Finished Feb 07 03:27:16 PM PST 24
Peak memory 199092 kb
Host smart-75477113-d791-4683-96de-f094fe6531a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1633660913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1633660913
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1055995566
Short name T247
Test name
Test status
Simulation time 3037037514 ps
CPU time 153 seconds
Started Feb 07 03:25:16 PM PST 24
Finished Feb 07 03:27:50 PM PST 24
Peak memory 199088 kb
Host smart-019be6a4-9aea-4034-8393-ee423f8e2508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055995566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1055995566
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3008300027
Short name T657
Test name
Test status
Simulation time 3831898835 ps
CPU time 96.16 seconds
Started Feb 07 03:25:20 PM PST 24
Finished Feb 07 03:26:56 PM PST 24
Peak memory 199112 kb
Host smart-61d60f4d-00db-4202-8455-e0aba2420321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008300027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3008300027
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1624639707
Short name T283
Test name
Test status
Simulation time 1117270248 ps
CPU time 3.73 seconds
Started Feb 07 03:25:20 PM PST 24
Finished Feb 07 03:25:24 PM PST 24
Peak memory 198928 kb
Host smart-410a46f3-558a-4569-87aa-a473d456bd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624639707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1624639707
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2947143397
Short name T819
Test name
Test status
Simulation time 29470019412 ps
CPU time 153.23 seconds
Started Feb 07 03:25:17 PM PST 24
Finished Feb 07 03:27:51 PM PST 24
Peak memory 199168 kb
Host smart-ed800180-631d-43f9-b752-118eb038a398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947143397 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2947143397
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_stress_all_with_rand_reset.1975941989
Short name T432
Test name
Test status
Simulation time 7996284584 ps
CPU time 163.29 seconds
Started Feb 07 03:25:22 PM PST 24
Finished Feb 07 03:28:06 PM PST 24
Peak memory 240128 kb
Host smart-8353a630-a1e8-4bf2-a342-d664db557133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975941989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all_with_rand_reset.1975941989
Directory /workspace/9.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1494265731
Short name T523
Test name
Test status
Simulation time 53325957 ps
CPU time 0.93 seconds
Started Feb 07 03:25:19 PM PST 24
Finished Feb 07 03:25:21 PM PST 24
Peak memory 196544 kb
Host smart-0c841774-3816-4aa9-9cf1-939594a71ad8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494265731 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1494265731
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.274116268
Short name T833
Test name
Test status
Simulation time 37306467890 ps
CPU time 473.15 seconds
Started Feb 07 03:25:18 PM PST 24
Finished Feb 07 03:33:12 PM PST 24
Peak memory 199080 kb
Host smart-a0c652e9-5c8a-4cea-b150-e2a1c4d93187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274116268 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 9.hmac_test_sha_vectors.274116268
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3138465888
Short name T577
Test name
Test status
Simulation time 24660814576 ps
CPU time 79.28 seconds
Started Feb 07 03:25:19 PM PST 24
Finished Feb 07 03:26:38 PM PST 24
Peak memory 199088 kb
Host smart-7b2e6483-2578-4381-b647-e0e427663455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138465888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3138465888
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/90.hmac_stress_all_with_rand_reset.3281953307
Short name T504
Test name
Test status
Simulation time 340562189391 ps
CPU time 1294.31 seconds
Started Feb 07 03:32:58 PM PST 24
Finished Feb 07 03:54:37 PM PST 24
Peak memory 253296 kb
Host smart-a7104489-cc90-430a-9b7f-0f08c3f797fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3281953307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.hmac_stress_all_with_rand_reset.3281953307
Directory /workspace/90.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.hmac_stress_all_with_rand_reset.2813009274
Short name T119
Test name
Test status
Simulation time 39063592804 ps
CPU time 1807.54 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 04:03:12 PM PST 24
Peak memory 251400 kb
Host smart-c45b063e-411e-45ff-b563-ab96f7b4b859
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2813009274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.hmac_stress_all_with_rand_reset.2813009274
Directory /workspace/91.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.hmac_stress_all_with_rand_reset.2427892179
Short name T645
Test name
Test status
Simulation time 35812811831 ps
CPU time 1536.32 seconds
Started Feb 07 03:33:06 PM PST 24
Finished Feb 07 03:58:43 PM PST 24
Peak memory 248276 kb
Host smart-ab23f94e-9ee0-429f-a78e-8f83a03b56eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2427892179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.hmac_stress_all_with_rand_reset.2427892179
Directory /workspace/92.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.hmac_stress_all_with_rand_reset.1194567513
Short name T356
Test name
Test status
Simulation time 848571905475 ps
CPU time 1035.67 seconds
Started Feb 07 03:33:09 PM PST 24
Finished Feb 07 03:50:25 PM PST 24
Peak memory 244028 kb
Host smart-c41e93ea-00d1-43d8-9780-6d9b54223340
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194567513 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.hmac_stress_all_with_rand_reset.1194567513
Directory /workspace/93.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.hmac_stress_all_with_rand_reset.2891911255
Short name T500
Test name
Test status
Simulation time 252486311119 ps
CPU time 1926.44 seconds
Started Feb 07 03:33:06 PM PST 24
Finished Feb 07 04:05:13 PM PST 24
Peak memory 258576 kb
Host smart-399624cc-b3bb-45c4-ab0e-f7bf5c44063b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891911255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.hmac_stress_all_with_rand_reset.2891911255
Directory /workspace/94.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.hmac_stress_all_with_rand_reset.3998880882
Short name T532
Test name
Test status
Simulation time 74118007397 ps
CPU time 3660.94 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 04:34:05 PM PST 24
Peak memory 247936 kb
Host smart-1c1a73b3-a997-4f5b-b323-d577dc252257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998880882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.hmac_stress_all_with_rand_reset.3998880882
Directory /workspace/95.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.3376466575
Short name T372
Test name
Test status
Simulation time 49865045797 ps
CPU time 592.51 seconds
Started Feb 07 03:33:05 PM PST 24
Finished Feb 07 03:42:59 PM PST 24
Peak memory 214580 kb
Host smart-833852c8-af32-466e-9015-99297c8d9ed6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376466575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.3376466575
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.hmac_stress_all_with_rand_reset.1697738612
Short name T687
Test name
Test status
Simulation time 39103436224 ps
CPU time 984.52 seconds
Started Feb 07 03:33:01 PM PST 24
Finished Feb 07 03:49:27 PM PST 24
Peak memory 207384 kb
Host smart-3330dde6-8420-451b-879d-89c443df90cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697738612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.hmac_stress_all_with_rand_reset.1697738612
Directory /workspace/97.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.2790439220
Short name T101
Test name
Test status
Simulation time 38785778343 ps
CPU time 582.98 seconds
Started Feb 07 03:33:06 PM PST 24
Finished Feb 07 03:42:50 PM PST 24
Peak memory 232892 kb
Host smart-e3461bdb-060f-4cd3-9531-5fb802308e35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790439220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.2790439220
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.hmac_stress_all_with_rand_reset.881779656
Short name T65
Test name
Test status
Simulation time 368748909111 ps
CPU time 1755.45 seconds
Started Feb 07 03:33:03 PM PST 24
Finished Feb 07 04:02:20 PM PST 24
Peak memory 261320 kb
Host smart-f3821c4f-6436-4d0f-810b-a25c286bafcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=881779656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.hmac_stress_all_with_rand_reset.881779656
Directory /workspace/99.hmac_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%