Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36036477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36161286

1

T1

30655

T2

7

T3

129

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	29072096	1			T1	27591		T2	1		T3	89
values[0x0]	20110815	1			T1	17946		T2	17		T3	84
values[0x1]	23014852	1			T1	22701		T2	8		T3	84

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26915889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

45281874

1

T1

40818

T2

9

T3

150

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	282877	1			T1	253		T10	5333		T8	266
valid_sources[0x01]	283020	1			T1	228		T10	5225		T8	318
valid_sources[0x02]	268945	1			T1	264		T10	5263		T8	413
valid_sources[0x03]	251406	1			T1	248		T10	5141		T8	254
valid_sources[0x04]	290072	1			T1	249		T10	5351		T8	235
valid_sources[0x05]	263577	1			T1	276		T10	5322		T11	2
valid_sources[0x06]	300471	1			T1	299		T10	5228		T8	341
valid_sources[0x07]	275147	1			T1	270		T10	5337		T8	295
valid_sources[0x08]	274055	1			T1	277		T10	5344		T8	311
valid_sources[0x09]	655795	1			T1	269		T10	5253		T11	84
valid_sources[0x0a]	249500	1			T1	274		T10	5187		T11	44
valid_sources[0x0b]	299170	1			T1	248		T10	5252		T8	304
valid_sources[0x0c]	256886	1			T1	242		T10	5303		T11	3
valid_sources[0x0d]	266459	1			T1	266		T10	5452		T11	9
valid_sources[0x0e]	280555	1			T1	278		T10	5148		T8	256
valid_sources[0x0f]	247270	1			T1	296		T10	5303		T8	270
valid_sources[0x10]	289973	1			T1	281		T10	5311		T8	190
valid_sources[0x11]	252999	1			T1	286		T10	5293		T8	502
valid_sources[0x12]	608376	1			T1	272		T10	5277		T8	185
valid_sources[0x13]	249068	1			T1	256		T10	5301		T8	285
valid_sources[0x14]	270104	1			T1	268		T10	5295		T8	406
valid_sources[0x15]	615501	1			T1	274		T10	5238		T8	273
valid_sources[0x16]	247928	1			T1	230		T10	5220		T8	362
valid_sources[0x17]	264831	1			T1	240		T10	5264		T8	281
valid_sources[0x18]	247866	1			T1	250		T2	1		T10	5194
valid_sources[0x19]	268032	1			T1	244		T10	5165		T8	410
valid_sources[0x1a]	251226	1			T1	280		T10	5233		T8	461
valid_sources[0x1b]	265490	1			T1	248		T10	5359		T8	343
valid_sources[0x1c]	265031	1			T1	270		T10	5292		T8	294
valid_sources[0x1d]	251306	1			T1	294		T10	5357		T8	282
valid_sources[0x1e]	252054	1			T1	241		T10	5359		T11	70
valid_sources[0x1f]	244038	1			T1	262		T10	5376		T8	234
valid_sources[0x20]	278089	1			T1	267		T10	5081		T8	367
valid_sources[0x21]	267821	1			T1	257		T10	5396		T11	8
valid_sources[0x22]	248357	1			T1	256		T10	5146		T8	266
valid_sources[0x23]	237396	1			T1	282		T10	5320		T8	342
valid_sources[0x24]	240886	1			T1	254		T10	5225		T8	365
valid_sources[0x25]	255705	1			T1	312		T10	5311		T8	263
valid_sources[0x26]	270335	1			T1	291		T10	5341		T8	355
valid_sources[0x27]	281179	1			T1	293		T10	5134		T11	20
valid_sources[0x28]	251812	1			T1	273		T10	5200		T8	365
valid_sources[0x29]	270889	1			T1	301		T10	5357		T8	285
valid_sources[0x2a]	255833	1			T1	273		T10	5257		T8	370
valid_sources[0x2b]	269988	1			T1	277		T10	5279		T11	54
valid_sources[0x2c]	263244	1			T1	289		T10	5265		T8	267
valid_sources[0x2d]	238536	1			T1	209		T10	5393		T11	12
valid_sources[0x2e]	272884	1			T1	271		T10	5290		T8	236
valid_sources[0x2f]	244711	1			T1	272		T10	5276		T8	287
valid_sources[0x30]	290250	1			T1	261		T10	5288		T8	221
valid_sources[0x31]	252144	1			T1	262		T10	5321		T8	224
valid_sources[0x32]	250758	1			T1	260		T10	5243		T8	316
valid_sources[0x33]	246558	1			T1	211		T10	5336		T8	249
valid_sources[0x34]	265122	1			T1	278		T2	1		T10	5260
valid_sources[0x35]	310466	1			T1	301		T10	5273		T8	309
valid_sources[0x36]	243264	1			T1	283		T10	5256		T8	302
valid_sources[0x37]	248326	1			T1	214		T10	5166		T8	235
valid_sources[0x38]	255217	1			T1	311		T10	5302		T8	411
valid_sources[0x39]	251523	1			T1	281		T10	5216		T8	353
valid_sources[0x3a]	255434	1			T1	286		T10	5266		T8	359
valid_sources[0x3b]	256323	1			T1	219		T10	5290		T8	300
valid_sources[0x3c]	255847	1			T1	259		T10	5322		T8	319
valid_sources[0x3d]	254197	1			T1	272		T10	5297		T8	278
valid_sources[0x3e]	624082	1			T1	299		T2	1		T10	5322
valid_sources[0x3f]	245165	1			T1	268		T10	5300		T11	14
valid_sources[0x40]	272900	1			T1	240		T10	5281		T11	1
valid_sources[0x41]	301121	1			T1	304		T10	5309		T8	255
valid_sources[0x42]	265744	1			T1	252		T10	5379		T8	404
valid_sources[0x43]	248029	1			T1	247		T10	5444		T8	421
valid_sources[0x44]	278532	1			T1	308		T10	5268		T8	357
valid_sources[0x45]	250760	1			T1	239		T10	5285		T8	344
valid_sources[0x46]	257361	1			T1	243		T10	5277		T8	328
valid_sources[0x47]	244345	1			T1	247		T10	5221		T8	332
valid_sources[0x48]	245102	1			T1	289		T10	5243		T8	332
valid_sources[0x49]	319494	1			T1	232		T2	1		T10	5127
valid_sources[0x4a]	255107	1			T1	248		T3	25		T10	5302
valid_sources[0x4b]	268240	1			T1	235		T10	5346		T8	389
valid_sources[0x4c]	241816	1			T1	250		T10	5314		T8	347
valid_sources[0x4d]	244599	1			T1	254		T10	5144		T8	349
valid_sources[0x4e]	248480	1			T1	253		T10	5459		T11	6
valid_sources[0x4f]	256408	1			T1	226		T10	5408		T8	404
valid_sources[0x50]	266077	1			T1	283		T10	5163		T8	309
valid_sources[0x51]	255219	1			T1	289		T10	5375		T11	15
valid_sources[0x52]	252036	1			T1	330		T10	5436		T11	13
valid_sources[0x53]	259496	1			T1	227		T10	5326		T8	411
valid_sources[0x54]	262318	1			T1	262		T10	5354		T8	275
valid_sources[0x55]	271104	1			T1	278		T10	5196		T11	5
valid_sources[0x56]	255763	1			T1	261		T10	5173		T8	324
valid_sources[0x57]	248499	1			T1	236		T10	5267		T8	350
valid_sources[0x58]	258010	1			T1	239		T10	5273		T8	292
valid_sources[0x59]	246405	1			T1	313		T10	5348		T11	5
valid_sources[0x5a]	266348	1			T1	291		T10	5425		T8	288
valid_sources[0x5b]	248587	1			T1	241		T2	2		T10	5361
valid_sources[0x5c]	261252	1			T1	278		T10	5362		T11	1
valid_sources[0x5d]	243121	1			T1	275		T10	5253		T8	370
valid_sources[0x5e]	249674	1			T1	246		T2	1		T10	5233
valid_sources[0x5f]	264442	1			T1	308		T10	5258		T8	372
valid_sources[0x60]	567418	1			T1	215		T10	5307		T8	231
valid_sources[0x61]	250975	1			T1	224		T10	5350		T8	242
valid_sources[0x62]	236119	1			T1	290		T10	5304		T8	250
valid_sources[0x63]	259877	1			T1	225		T10	5167		T11	1
valid_sources[0x64]	237276	1			T1	251		T10	5317		T8	359
valid_sources[0x65]	258764	1			T1	264		T10	5347		T8	349
valid_sources[0x66]	245107	1			T1	282		T10	5293		T11	8
valid_sources[0x67]	252569	1			T1	286		T10	5346		T11	5
valid_sources[0x68]	249826	1			T1	224		T10	5298		T8	280
valid_sources[0x69]	668033	1			T1	332		T10	5289		T8	371
valid_sources[0x6a]	240454	1			T1	260		T10	5225		T8	322
valid_sources[0x6b]	259680	1			T1	266		T10	5229		T8	440
valid_sources[0x6c]	260169	1			T1	275		T10	5259		T8	282
valid_sources[0x6d]	265197	1			T1	269		T10	5218		T11	8
valid_sources[0x6e]	257194	1			T1	250		T10	5321		T8	366
valid_sources[0x6f]	257468	1			T1	268		T10	5320		T8	288
valid_sources[0x70]	235836	1			T1	280		T10	5295		T8	392
valid_sources[0x71]	296397	1			T1	295		T10	5284		T8	316
valid_sources[0x72]	271431	1			T1	259		T10	5324		T8	268
valid_sources[0x73]	239126	1			T1	244		T10	5229		T8	294
valid_sources[0x74]	270775	1			T1	295		T10	5215		T8	398
valid_sources[0x75]	278288	1			T1	262		T2	2		T10	5256
valid_sources[0x76]	246622	1			T1	272		T10	5260		T8	379
valid_sources[0x77]	241067	1			T1	280		T10	5243		T8	281
valid_sources[0x78]	260687	1			T1	282		T10	5305		T8	360
valid_sources[0x79]	248084	1			T1	277		T10	5260		T8	293
valid_sources[0x7a]	282278	1			T1	237		T10	5312		T8	323
valid_sources[0x7b]	306910	1			T1	273		T3	120		T10	5257
valid_sources[0x7c]	251528	1			T1	220		T10	5337		T8	328
valid_sources[0x7d]	259662	1			T1	254		T10	5378		T8	278
valid_sources[0x7e]	262858	1			T1	293		T10	5283		T8	321
valid_sources[0x7f]	253839	1			T1	252		T2	3		T10	5378
valid_sources[0x80]	621691	1			T1	313		T10	5256		T8	385

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

13958858

1

T1

13700

T3

49

T4

47

values[0x0]

all_enables

biggest_size

11677118

1

T1

8982

T2

6

T3

47

values[0x1]

all_enables

biggest_size

10525310

1

T1

7973

T2

1

T3

33