Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38896493

1

T1

37583

T2

19

T3

128

full_word

36376538

1

T1

30655

T2

7

T3

129

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75272661	1			T1	68238		T2	26		T3	257
auto[TlIntgErrCmd]	123	1			T56	15		T57	6		T58	10
auto[TlIntgErrData]	126	1			T56	5		T57	7		T58	7
auto[TlIntgErrBoth]	121	1			T56	10		T57	7		T58	13

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30212011

1

T1

27591

T2

1

T3

89

auto[1]

45061020

1

T1

40647

T2

25

T3

168

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16166739	1			T1	13891		T2	1		T3	40
auto[TlIntgErrNone]	partial	auto[1]	22729410	1			T1	23692		T2	18		T3	88
auto[TlIntgErrNone]	full_word	auto[0]	14045105	1			T1	13700		T3	49		T4	47
auto[TlIntgErrNone]	full_word	auto[1]	22331407	1			T1	16955		T2	7		T3	80
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T56	5		T57	2		T58	3
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T56	9		T57	3		T58	6
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T129	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T56	1		T57	1		T58	1
auto[TlIntgErrData]	partial	auto[0]	66	1			T56	1		T57	4		T58	4
auto[TlIntgErrData]	partial	auto[1]	50	1			T56	3		T57	2		T58	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T56	1		T57	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T133	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T56	4		T57	3		T58	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T56	5		T57	4		T58	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T129	1		T135	1		T136	2
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T56	1		T58	2		T131	1