Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38346771

1

T1

1562

T2

6630

T3

1362

full_word

36664592

1

T1

1522

T2

24483

T3

8972

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75011013	1			T1	3084		T2	31113		T3	10334
auto[TlIntgErrCmd]	102	1			T53	4		T54	5		T55	1
auto[TlIntgErrData]	123	1			T53	9		T54	2		T55	5
auto[TlIntgErrBoth]	125	1			T53	7		T54	3		T55	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30137175

1

T1

1637

T2

8721

T3

518

auto[1]

44874188

1

T1

1447

T2

22392

T3

9816

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16072587	1			T1	906		T2	6294		T3	323
auto[TlIntgErrNone]	partial	auto[1]	22273859	1			T1	656		T2	336		T3	1039
auto[TlIntgErrNone]	full_word	auto[0]	14064434	1			T1	731		T2	2427		T3	195
auto[TlIntgErrNone]	full_word	auto[1]	22600133	1			T1	791		T2	22056		T3	8777
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T53	2		T54	2		T55	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T53	2		T54	3		T147	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T144	1		T148	1		T149	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T150	1		T151	2		-	-
auto[TlIntgErrData]	partial	auto[0]	61	1			T53	5		T54	1		T55	3
auto[TlIntgErrData]	partial	auto[1]	52	1			T53	4		T54	1		T55	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T55	1		T148	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T147	1		T144	1		T148	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T53	3		T54	2		T55	3
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T53	3		T54	1		T55	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T150	1		T152	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T53	1		T148	1		T153	1