Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.06	100.00	95.31	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	386898892	1365975	0	0
intr_enable_rd_A	386898892	3193	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386898892	1365975	0	0
T4	876725	41044	0	0
T5	0	28329	0	0
T6	0	154996	0	0
T14	0	152616	0	0
T15	0	50419	0	0
T16	0	233785	0	0
T17	0	83713	0	0
T58	0	120376	0	0
T59	0	127795	0	0
T60	0	23327	0	0
T61	11610	0	0	0
T62	273427	0	0	0
T63	7902	0	0	0
T64	151817	0	0	0
T65	141961	0	0	0
T66	140686	0	0	0
T67	33778	0	0	0
T68	1212	0	0	0
T69	180703	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	386898892	3193	0	0
T5	706509	0	0	0
T57	809459	53	0	0
T70	0	112	0	0
T71	0	27	0	0
T72	0	67	0	0
T73	0	39	0	0
T74	0	5	0	0
T75	0	12	0	0
T76	0	4	0	0
T77	0	41	0	0
T78	0	26	0	0
T79	113962	0	0	0
T80	5545	0	0	0
T81	136781	0	0	0
T82	3771	0	0	0
T83	252727	0	0	0
T84	183700	0	0	0
T85	65620	0	0	0
T86	340385	0	0	0