Unified Coverage Report :: Module :: prim_sha2_pad

Module : prim_sha2_pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.34	96.19	92.50		66.67	86.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad	94.44	100.00	100.00		90.00	87.76

---

Module Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	100.00		90.00	87.76

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	100.00		90.00	87.76

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00		100.00	100.00		gen_sha256_logic.u_prim_sha2_256

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
TOTAL		105	101	96.19
CONT_ASSIGN	44	0	0
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
ALWAYS	62	3	3	100.00
ALWAYS	77	13	13	100.00
ALWAYS	166	3	3	100.00
ALWAYS	172	69	65	94.20
ALWAYS	316	6	6	100.00
ALWAYS	330	3	3	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	339	3	3	100.00
CONT_ASSIGN	344	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44		unreachable
47	1	1
51	1	1
57	1	1
62	2	2
63	1	1
77	1	1
79	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
96		unreachable
97		unreachable
98		unreachable
99		unreachable
100		unreachable
101		unreachable
102		unreachable
103		unreachable
104		unreachable
105		unreachable
109		unreachable
113	1	1
117	1	1
124	1	1
135	2	2
			==> MISSING_ELSE
166	2	2
167	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
211	1	1
212	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
227	1	1
228	1	1
229	1	1
233	1	1
234	1	1
235	1	1
237	1	1
238	1	1
267	1	1
268	1	1
270	1	1
271	1	1
272	2	2
273	1	1
275	1	1
280	1	1
281	1	1
283	1	1
284	1	1
285	1	1
287	0	1
288	0	1
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
300	0	1
301	0	1
310	2	2
311	2	2
			MISSING_ELSE
316	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323		unreachable
324		unreachable
			==> MISSING_ELSE
			MISSING_ELSE
330	2	2
331	1	1
334	1	1
339	2	2
340	1	1
344	1	1

---

Cond Coverage for Module : prim_sha2_pad

	Total	Covered	Percent
Conditions	40	37	92.50
Logical	40	37	92.50
Non-Logical	0	0
Event	0	0

 LINE       51
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       51
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 EXPRESSION ((((~sha_en_i)) || hash_start_i || hash_done_o) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       57
 SUB-EXPRESSION (((~sha_en_i)) || hash_start_i || hash_done_o)
                 ------1------    ------2-----    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       57
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       96
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       96
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       182
 EXPRESSION (sha_en_i && hash_start_i)
             ----1---    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION ((((tx_count == message_length_i) & MultimodeEn)) || ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn))))
             ------------------------1-----------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       203
 SUB-EXPRESSION ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn)))
                 ---------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T10
1	-	Covered	T1,T2,T3

 LINE       203
 SUB-EXPRESSION (tx_count[63:0] == message_length_i[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       221
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       227
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       233
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       323
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       323
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       334
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : prim_sha2_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	15	10	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	184	Covered	T1,T2,T3
StIdle	176	Covered	T1,T2,T3
StLenHi	228	Covered	T1,T2,T3
StLenLo	284	Covered	T1,T2,T3
StPad00	234	Covered	T1,T2,T3
StPad80	197	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StFifoReceive->StIdle	176	Covered	T4,T5,T14
StFifoReceive->StPad80	197	Covered	T1,T2,T3
StIdle->StFifoReceive	184	Covered	T1,T2,T3
StLenHi->StFifoReceive	311	Not Covered
StLenHi->StIdle	176	Covered	T15,T16,T17
StLenHi->StLenLo	284	Covered	T1,T2,T3
StLenLo->StFifoReceive	311	Not Covered
StLenLo->StIdle	176	Covered	T1,T2,T3
StPad00->StFifoReceive	311	Not Covered
StPad00->StIdle	176	Covered	T14
StPad00->StLenHi	272	Covered	T1,T2,T3
StPad80->StFifoReceive	311	Not Covered
StPad80->StIdle	176	Not Covered
StPad80->StLenHi	228	Covered	T1,T2,T7
StPad80->StPad00	234	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_sha2_pad

	Line No.	Total	Covered	Percent
Branches		50	43	86.00
TERNARY	57	3	3	100.00
TERNARY	334	3	3	100.00
IF	62	2	2	100.00
CASE	77	10	8	80.00
IF	135	2	1	50.00
IF	166	2	2	100.00
CASE	178	17	14	82.35
IF	310	3	3	100.00
IF	318	4	3	75.00
IF	330	2	2	100.00
IF	339	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	57	((((~sha_en_i) || hash_start_i) || hash_done_o)) ? 
-2-:	57	(hash_process_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	(hash_start_i) ? 
-2-:	334	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	case (sel_data)
-2-:	88	if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)))
-3-:	89	case (message_length_i[4:3])
-4-:	96	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-5-:	97	case (message_length_i[5:3])

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FifoIn	-	-	-	-	Covered	T1,T2,T3
Pad80	1	2'b00	-	-	Covered	T1,T2,T3
Pad80	1	2'b01	-	-	Covered	T1,T2,T3
Pad80	1	2'b10	-	-	Covered	T1,T2,T3
Pad80	1	2'b11	-	-	Covered	T1,T2,T3
Pad80	1	default	-	-	Not Covered
Pad80	0	-	1	3'b000	Unreachable
Pad80	0	-	1	3'b001	Unreachable
Pad80	0	-	1	3'b010	Unreachable
Pad80	0	-	1	3'b011	Unreachable
Pad80	0	-	1	3'b100	Unreachable
Pad80	0	-	1	3'b101	Unreachable
Pad80	0	-	1	3'b110	Unreachable
Pad80	0	-	1	3'b111	Unreachable
Pad80	0	-	1	default	Unreachable
Pad80	0	-	0	-	Unreachable
Pad00	-	-	-	-	Covered	T1,T2,T3
LenHi	-	-	-	-	Covered	T1,T2,T3
LenLo	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	135	if ((!MultimodeEn))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st_q)
-2-:	182	if ((sha_en_i && hash_start_i))
-3-:	192	if ((fifo_partial && fifo_rvalid_i))
-4-:	198	if ((!hash_process_flag_q))
-5-:	203	if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
-6-:	227	if ((shaf_rready_i && txcnt_eq_1a0))
-7-:	233	if ((shaf_rready_i && (!txcnt_eq_1a0)))
-8-:	270	if (shaf_rready_i)
-9-:	272	if (txcnt_eq_1a0)
-10-:	283	if (shaf_rready_i)
-11-:	296	if (shaf_rready_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T2,T3,T10
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T7
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T3
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T7
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T3
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T3
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StLenHi	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StLenLo	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	310	if ((!sha_en_i))
-2-:	311	if (hash_start_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if (hash_start_i)
-2-:	320	if (inc_txcount)
-3-:	321	if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn)))
-4-:	323	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	1	Unreachable
0	1	0	0	Not Covered
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	339	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	44	0	0
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	57	1	1	100.00
ALWAYS	62	3	3	100.00
ALWAYS	77	13	13	100.00
ALWAYS	166	3	3	100.00
ALWAYS	172	65	65	100.00
ALWAYS	316	6	6	100.00
ALWAYS	330	3	3	100.00
CONT_ASSIGN	334	1	1	100.00
ALWAYS	339	3	3	100.00
CONT_ASSIGN	344	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44		unreachable
47	1	1
51	1	1
57	1	1
62	2	2
63	1	1
77	1	1
79	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
96		unreachable
97		unreachable
98		unreachable
99		unreachable
100		unreachable
101		unreachable
102		unreachable
103		unreachable
104		unreachable
105		unreachable
109		unreachable
113	1	1
117	1	1
124	1	1
			Exclude Annotation: VC_COV_UNR
135	2	2
			==> MISSING_ELSE
166	2	2
167	1	1
172	1	1
173	1	1
174	1	1
175	1	1
176	1	1
178	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
191	1	1
192	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
206	1	1
207	1	1
208	1	1
209	1	1
211	1	1
212	1	1
213	1	1
214	1	1
219	1	1
220	1	1
221	1	1
227	1	1
228	1	1
229	1	1
233	1	1
234	1	1
235	1	1
237	1	1
238	1	1
267	1	1
268	1	1
270	1	1
271	1	1
272	2	2
273	1	1
275	1	1
280	1	1
281	1	1
283	1	1
284	1	1
285	1	1
287		excluded
			Exclude Annotation: VC_COV_UNR
288		excluded
			Exclude Annotation: VC_COV_UNR
293	1	1
294	1	1
296	1	1
297	1	1
298	1	1
300		excluded
			Exclude Annotation: VC_COV_UNR
301		excluded
			Exclude Annotation: VC_COV_UNR
			Exclude Annotation: VC_COV_UNR
310	2	2
311	2	2
			MISSING_ELSE
316	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
323		unreachable
324		unreachable
			==> MISSING_ELSE
			MISSING_ELSE
330	2	2
331	1	1
334	1	1
339	2	2
340	1	1
344	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Total	Covered	Percent
Conditions	37	37	100.00
Logical	37	37	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 SUB-EXPRESSION (tx_count[8:0] == 9'h1a0)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       51
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (tx_count[9:0] == 10'h340) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       51
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       51
 SUB-EXPRESSION (tx_count[9:0] == 10'h340)
                -------------1------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       57
 EXPRESSION ((((~sha_en_i)) || hash_start_i || hash_done_o) ? 1'b0 : (hash_process_i ? 1'b1 : hash_process_flag_q))
             -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       57
 SUB-EXPRESSION (((~sha_en_i)) || hash_start_i || hash_done_o)
                 ------1------    ------2-----    -----3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T2,T3

 LINE       57
 SUB-EXPRESSION (hash_process_i ? 1'b1 : hash_process_flag_q)
                 -------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       96
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       96
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       96
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       182
 EXPRESSION (sha_en_i && hash_start_i)
             ----1---    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       192
 EXPRESSION (fifo_partial && fifo_rvalid_i)
             ------1-----    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       203
 EXPRESSION ((((tx_count == message_length_i) & MultimodeEn)) || ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn))))
             ------------------------1-----------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T10
0	1	Covered	T1,T2,T3
1	0	Unreachable

 LINE       203
 SUB-EXPRESSION ((tx_count[63:0] == message_length_i[63:0]) & ((!MultimodeEn)))
                 ---------------------1--------------------   --------2-------

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T10
1	-	Covered	T1,T2,T3

 LINE       203
 SUB-EXPRESSION (tx_count[63:0] == message_length_i[63:0])
                ---------------------1--------------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[4:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       221
 SUB-EXPRESSION (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)) ? (shaf_rready_i && ((|message_length_i[5:3]))) : '0)
                 -----------------------------------1----------------------------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
                 ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       221
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       221
 SUB-EXPRESSION (shaf_rready_i && ((|message_length_i[5:3])))
                 ------1------    -------------2------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Unreachable

 LINE       227
 EXPRESSION (shaf_rready_i && txcnt_eq_1a0)
             ------1------    ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       233
 EXPRESSION (shaf_rready_i && ((!txcnt_eq_1a0)))
             ------1------    --------2--------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T7
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T3

 LINE       323
 EXPRESSION ((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512))
             ----------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Unreachable
0	1	Unreachable
1	0	Unreachable

 LINE       323
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_384)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       323
 SUB-EXPRESSION (digest_mode_flag_q == SHA2_512)
                ----------------1---------------

-1-	Status	Tests
0	Unreachable
1	Unreachable

 LINE       334
 EXPRESSION (hash_start_i ? digest_mode_i : (hash_done_o ? None : digest_mode_flag_q))
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       334
 SUB-EXPRESSION (hash_done_o ? None : digest_mode_flag_q)
                 -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION (hash_process_flag_q && (st_q == StIdle))
             ---------1---------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       344
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

Summary for FSM :: st_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	10	9	90.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StFifoReceive	184	Covered	T1,T2,T3
StIdle	176	Covered	T1,T2,T3
StLenHi	228	Covered	T1,T2,T3
StLenLo	284	Covered	T1,T2,T3
StPad00	234	Covered	T1,T2,T3
StPad80	197	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests	Exclude Annotation
StFifoReceive->StIdle	176	Covered	T4,T5,T14
StFifoReceive->StPad80	197	Covered	T1,T2,T3
StIdle->StFifoReceive	184	Covered	T1,T2,T3
StLenHi->StFifoReceive	311	Excluded		VC_COV_UNR
StLenHi->StIdle	176	Excluded	T15,T16,T17	VC_COV_UNR
StLenHi->StLenLo	284	Covered	T1,T2,T3
StLenLo->StFifoReceive	311	Excluded		VC_COV_UNR
StLenLo->StIdle	176	Covered	T1,T2,T3
StPad00->StFifoReceive	311	Excluded		VC_COV_UNR
StPad00->StIdle	176	Covered	T14
StPad00->StLenHi	272	Covered	T1,T2,T3
StPad80->StFifoReceive	311	Excluded		VC_COV_UNR
StPad80->StIdle	176	Not Covered
StPad80->StLenHi	228	Covered	T1,T2,T7
StPad80->StPad00	234	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_prim_sha2_256.gen_sha256_logic.u_prim_sha2_256.u_pad

	Line No.	Total	Covered	Percent
Branches		49	43	87.76
TERNARY	57	3	3	100.00
TERNARY	334	3	3	100.00
IF	62	2	2	100.00
CASE	77	10	8	80.00
IF	135	1	1	100.00
IF	166	2	2	100.00
CASE	178	17	14	82.35
IF	310	3	3	100.00
IF	318	4	3	75.00
IF	330	2	2	100.00
IF	339	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv' or '../src/lowrisc_prim_sha2_0/rtl/prim_sha2_pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	57	((((~sha_en_i) || hash_start_i) || hash_done_o)) ? 
-2-:	57	(hash_process_i) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	334	(hash_start_i) ? 
-2-:	334	(hash_done_o) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	case (sel_data)
-2-:	88	if (((digest_mode_flag_q == SHA2_256) || (~MultimodeEn)))
-3-:	89	case (message_length_i[4:3])
-4-:	96	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))
-5-:	97	case (message_length_i[5:3])

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
FifoIn	-	-	-	-	Covered	T1,T2,T3
Pad80	1	2'b00	-	-	Covered	T1,T2,T3
Pad80	1	2'b01	-	-	Covered	T1,T2,T3
Pad80	1	2'b10	-	-	Covered	T1,T2,T3
Pad80	1	2'b11	-	-	Covered	T1,T2,T3
Pad80	1	default	-	-	Not Covered
Pad80	0	-	1	3'b000	Unreachable
Pad80	0	-	1	3'b001	Unreachable
Pad80	0	-	1	3'b010	Unreachable
Pad80	0	-	1	3'b011	Unreachable
Pad80	0	-	1	3'b100	Unreachable
Pad80	0	-	1	3'b101	Unreachable
Pad80	0	-	1	3'b110	Unreachable
Pad80	0	-	1	3'b111	Unreachable
Pad80	0	-	1	default	Unreachable
Pad80	0	-	0	-	Unreachable
Pad00	-	-	-	-	Covered	T1,T2,T3
LenHi	-	-	-	-	Covered	T1,T2,T3
LenLo	-	-	-	-	Covered	T1,T2,T3
default	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	135	if ((!MultimodeEn))

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	166	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	178	case (st_q)
-2-:	182	if ((sha_en_i && hash_start_i))
-3-:	192	if ((fifo_partial && fifo_rvalid_i))
-4-:	198	if ((!hash_process_flag_q))
-5-:	203	if ((((tx_count == message_length_i) & MultimodeEn) || ((tx_count[63:0] == message_length_i[63:0]) & (!MultimodeEn))))
-6-:	227	if ((shaf_rready_i && txcnt_eq_1a0))
-7-:	233	if ((shaf_rready_i && (!txcnt_eq_1a0)))
-8-:	270	if (shaf_rready_i)
-9-:	272	if (txcnt_eq_1a0)
-10-:	283	if (shaf_rready_i)
-11-:	296	if (shaf_rready_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	0	1	-	-	-	-	-	-	Covered	T1,T2,T3
StFifoReceive	-	0	0	0	-	-	-	-	-	-	Covered	T2,T3,T10
StPad80	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T7
StPad80	-	-	-	-	0	1	-	-	-	-	Covered	T1,T2,T3
StPad80	-	-	-	-	0	0	-	-	-	-	Covered	T1,T2,T7
StPad00	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T3
StPad00	-	-	-	-	-	-	1	0	-	-	Covered	T1,T2,T3
StPad00	-	-	-	-	-	-	0	-	-	-	Covered	T1,T2,T3
StLenHi	-	-	-	-	-	-	-	-	1	-	Covered	T1,T2,T3
StLenHi	-	-	-	-	-	-	-	-	0	-	Not Covered
StLenLo	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StLenLo	-	-	-	-	-	-	-	-	-	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	310	if ((!sha_en_i))
-2-:	311	if (hash_start_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	318	if (hash_start_i)
-2-:	320	if (inc_txcount)
-3-:	321	if (((digest_mode_flag_q == SHA2_256) || (!MultimodeEn)))
-4-:	323	if (((digest_mode_flag_q == SHA2_384) || (digest_mode_flag_q == SHA2_512)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	1	Unreachable
0	1	0	0	Not Covered
0	0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	330	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	339	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3