Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13225392	1			T1	11678		T2	15502		T3	9696
all_values[1]	13225392	1			T1	11678		T2	15502		T3	9696
all_values[2]	13225392	1			T1	11678		T2	15502		T3	9696

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113397

1

T1

255

T2

1497

T7

1016

auto[1]

39562779

1

T1

34779

T2

45009

T3

29088

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28146666

1

T1

25880

T2

40872

T3

25495

auto[1]

11529510

1

T1

9154

T2

5634

T3

3593

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	39191	1			T7	4		T11	1284		T77	386
all_values[0]	auto[0]	auto[1]	449	1			T11	2		T77	2		T97	2
all_values[0]	auto[1]	auto[0]	13140212	1			T1	11620		T2	15468		T3	9622
all_values[0]	auto[1]	auto[1]	45540	1			T1	58		T2	34		T3	74
all_values[1]	auto[0]	auto[0]	19400	1			T1	59		T2	991		T7	168
all_values[1]	auto[0]	auto[1]	19299	1			T1	196		T2	506		T7	840
all_values[1]	auto[1]	auto[0]	6942257	1			T1	2523		T2	8911		T3	6229
all_values[1]	auto[1]	auto[1]	6244436	1			T1	8900		T2	5094		T3	3467
all_values[2]	auto[0]	auto[0]	29701	1			T7	3		T14	8		T22	2
all_values[2]	auto[0]	auto[1]	5357	1			T7	1		T98	632		T140	648
all_values[2]	auto[1]	auto[0]	7975905	1			T1	11678		T2	15502		T3	9644
all_values[2]	auto[1]	auto[1]	5214429	1			T3	52		T7	54921		T8	19286