| | | | | | | | |
tb |
98.74 |
99.55 |
98.65 |
100.00 |
96.30 |
98.47 |
99.49 |
dut |
98.74 |
99.55 |
98.65 |
100.00 |
96.30 |
98.47 |
99.49 |
| gen_alert_tx[0].u_prim_alert_sender |
100.00 |
|
|
100.00 |
|
|
|
| hmac_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
| intr_hw_fifo_empty |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_hmac_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| intr_hw_hmac_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| tlul_assert_device |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
| u_hmac |
100.00 |
100.00 |
100.00 |
|
100.00 |
100.00 |
|
| u_msg_fifo |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_packer |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_prim_sha2_256 |
97.36 |
100.00 |
100.00 |
|
94.74 |
94.69 |
|
| gen_sha256_logic.u_prim_sha2_256 |
97.36 |
100.00 |
100.00 |
|
94.74 |
94.69 |
|
| u_pad |
94.44 |
100.00 |
100.00 |
|
90.00 |
87.76 |
|
| u_reg |
99.48 |
99.44 |
97.94 |
100.00 |
|
100.00 |
100.00 |
| u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
| u_cfg_digest_swap |
100.00 |
100.00 |
|
|
|
|
|
| u_cfg_endian_swap |
100.00 |
100.00 |
|
|
|
|
|
| u_cfg_hmac_en |
100.00 |
100.00 |
|
|
|
|
|
| u_cfg_sha_en |
100.00 |
100.00 |
|
|
|
|
|
| u_chk |
100.00 |
100.00 |
|
100.00 |
|
|
100.00 |
| u_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
| u_cmd_hash_process |
100.00 |
100.00 |
|
|
|
|
|
| u_cmd_hash_start |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_0 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_1 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_2 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_3 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_4 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_5 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_6 |
100.00 |
100.00 |
|
|
|
|
|
| u_digest_7 |
100.00 |
100.00 |
|
|
|
|
|
| u_err_code |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
|
|
|
|
|
| u_intr_enable_fifo_empty |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable_hmac_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_enable_hmac_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| u_intr_state_fifo_empty |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_state_hmac_done |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_state_hmac_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
| u_intr_test_fifo_empty |
100.00 |
100.00 |
|
|
|
|
|
| u_intr_test_hmac_done |
100.00 |
100.00 |
|
|
|
|
|
| u_intr_test_hmac_err |
100.00 |
100.00 |
|
|
|
|
|
| u_key_0 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_1 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_2 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_3 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_4 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_5 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_6 |
100.00 |
100.00 |
|
|
|
|
|
| u_key_7 |
100.00 |
100.00 |
|
|
|
|
|
| u_msg_length_lower |
95.83 |
87.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
| u_msg_length_upper |
95.83 |
87.50 |
100.00 |
|
|
100.00 |
|
| wr_en_data_arb |
50.00 |
50.00 |
|
|
|
|
|
| u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
| u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
| gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
| u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
| u_reg_if |
99.69 |
100.00 |
98.75 |
|
|
100.00 |
100.00 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
| u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
| gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
| u_socket |
99.69 |
98.75 |
100.00 |
|
|
100.00 |
100.00 |
| fifo_h |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_dfifo[0].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| gen_dfifo[1].fifo_d |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| reqfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| rspfifo |
100.00 |
100.00 |
|
|
|
|
100.00 |
| u_status_fifo_depth |
100.00 |
100.00 |
|
|
|
|
|
| u_status_fifo_empty |
100.00 |
100.00 |
|
|
|
|
|
| u_status_fifo_full |
100.00 |
100.00 |
|
|
|
|
|
| u_wipe_secret |
100.00 |
100.00 |
|
|
|
|
|
| u_tlul_adapter |
97.46 |
98.54 |
100.00 |
|
|
98.44 |
92.86 |
| u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| u_reqfifo |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
| u_rspfifo |
97.20 |
97.14 |
100.00 |
|
|
91.67 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|
| u_sram_byte |
100.00 |
100.00 |
|
|
|
|
|
| u_sramreqfifo |
99.26 |
97.06 |
100.00 |
|
|
100.00 |
100.00 |
| gen_normal_fifo.u_fifo_cnt |
100.00 |
100.00 |
|
|
|
100.00 |
|