Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6435920

1

T1

6078

T2

12048

T3

12507

auto[1]

2573167

1

T1

5391

T2

2878

T3

17149

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2581909

1

T1

5616

T2

3853

T3

7676

auto[1]

6427178

1

T1

5853

T2

11073

T3

21980

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5757948

1

T1

5044

T3

10066

T7

63429

auto[1]

3251139

1

T1

6425

T2

14926

T3

19590

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	5807147	1			T1	9955		T2	5047		T3	3414
fifo_depth[1]	441873	1			T1	655		T2	1077		T3	743
fifo_depth[2]	368823	1			T1	463		T2	1118		T3	1104
fifo_depth[3]	300104	1			T1	253		T2	1131		T3	1100
fifo_depth[4]	278586	1			T1	101		T2	1124		T3	1257
fifo_depth[5]	239386	1			T1	28		T2	1077		T3	1185
fifo_depth[6]	239779	1			T1	10		T2	1075		T3	1375
fifo_depth[7]	208098	1			T1	3		T2	984		T3	1249
fifo_depth[8]	230092	1			T1	1		T2	839		T3	3004
fifo_depth[9]	142648	1			T2	603		T3	1074		T8	39
fifo_depth[10]	130074	1			T2	412		T3	1718		T8	20
fifo_depth[11]	82803	1			T2	253		T3	945		T8	22
fifo_depth[12]	127673	1			T2	119		T3	2922		T8	6
fifo_depth[13]	57203	1			T2	40		T3	785		T8	6
fifo_depth[14]	89013	1			T2	17		T3	1538		T8	1
fifo_depth[15]	51075	1			T2	8		T3	657		T10	3
fifo_depth[16]	214710	1			T2	2		T3	5586		T10	5

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3201940

1

T1

1514

T2

9879

T3

26242

auto[1]

5807147

1

T1

9955

T2

5047

T3

3414

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8794377

1

T1

11469

T2

14924

T3

24070

auto[1]

214710

1

T2

2

T3

5586

T10

5

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

234969

1

T1

168

T3

528

T7

445

auto[0]

auto[0]

auto[0]

auto[1]

224375

1

T1

120

T3

2595

T7

547

auto[0]

auto[0]

auto[1]

auto[0]

935133

1

T1

217

T3

3900

T7

1640

auto[0]

auto[0]

auto[1]

auto[1]

233937

1

T1

151

T3

702

T7

273

auto[0]

auto[1]

auto[0]

auto[0]

374129

1

T1

250

T2

2195

T3

759

auto[0]

auto[1]

auto[0]

auto[1]

407659

1

T1

192

T2

357

T3

2191

auto[0]

auto[1]

auto[1]

auto[0]

406683

1

T1

158

T2

5782

T3

6009

auto[0]

auto[1]

auto[1]

auto[1]

385055

1

T1

258

T2

1545

T3

9558

auto[1]

auto[0]

auto[0]

auto[0]

261216

1

T1

1230

T3

310

T7

6838

auto[1]

auto[0]

auto[0]

auto[1]

243569

1

T1

769

T3

1115

T7

6561

auto[1]

auto[0]

auto[1]

auto[0]

3397143

1

T1

1429

T3

525

T7

43687

auto[1]

auto[0]

auto[1]

auto[1]

227606

1

T1

960

T3

391

T7

3438

auto[1]

auto[1]

auto[0]

auto[0]

413742

1

T1

1596

T2

1111

T3

41

auto[1]

auto[1]

auto[0]

auto[1]

422250

1

T1

1291

T2

190

T3

137

auto[1]

auto[1]

auto[1]

auto[0]

412905

1

T1

1030

T2

2960

T3

435

auto[1]

auto[1]

auto[1]

auto[1]

428716

1

T1

1650

T2

786

T3

460

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

466242

1

T1

1398

T3

838

T7

7283

auto[0]

auto[0]

auto[0]

auto[1]

442904

1

T1

889

T3

3659

T7

7108

auto[0]

auto[0]

auto[1]

auto[0]

4303493

1

T1

1646

T3

2516

T7

45327

auto[0]

auto[0]

auto[1]

auto[1]

442342

1

T1

1111

T3

1093

T7

3711

auto[0]

auto[1]

auto[0]

auto[0]

762438

1

T1

1846

T2

3304

T3

308

auto[0]

auto[1]

auto[0]

auto[1]

802262

1

T1

1483

T2

547

T3

1363

auto[0]

auto[1]

auto[1]

auto[0]

787549

1

T1

1188

T2

8742

T3

5664

auto[0]

auto[1]

auto[1]

auto[1]

787147

1

T1

1908

T2

2331

T3

8629

auto[1]

auto[0]

auto[0]

auto[0]

29943

1

T27

1

T20

1

T100

1650

auto[1]

auto[0]

auto[0]

auto[1]

25040

1

T3

51

T27

1

T20

1

auto[1]

auto[0]

auto[1]

auto[0]

28783

1

T3

1909

T20

1

T22

2

auto[1]

auto[0]

auto[1]

auto[1]

19201

1

T26

1

T123

2

T151

1

auto[1]

auto[1]

auto[0]

auto[0]

25433

1

T2

2

T3

492

T11

3

auto[1]

auto[1]

auto[0]

auto[1]

27647

1

T3

965

T10

2

T20

2

auto[1]

auto[1]

auto[1]

auto[0]

32039

1

T3

780

T10

3

T11

1

auto[1]

auto[1]

auto[1]

auto[1]

26624

1

T3

1389

T27

2

T29

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	261216	1			T1	1230		T3	310		T7	6838
fifo_depth[0]	auto[0]	auto[0]	auto[1]	243569	1			T1	769		T3	1115		T7	6561
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3397143	1			T1	1429		T3	525		T7	43687
fifo_depth[0]	auto[0]	auto[1]	auto[1]	227606	1			T1	960		T3	391		T7	3438
fifo_depth[0]	auto[1]	auto[0]	auto[0]	413742	1			T1	1596		T2	1111		T3	41
fifo_depth[0]	auto[1]	auto[0]	auto[1]	422250	1			T1	1291		T2	190		T3	137
fifo_depth[0]	auto[1]	auto[1]	auto[0]	412905	1			T1	1030		T2	2960		T3	435
fifo_depth[0]	auto[1]	auto[1]	auto[1]	428716	1			T1	1650		T2	786		T3	460
fifo_depth[1]	auto[0]	auto[0]	auto[0]	21818	1			T1	81		T3	70		T7	265
fifo_depth[1]	auto[0]	auto[0]	auto[1]	20600	1			T1	46		T3	193		T7	354
fifo_depth[1]	auto[0]	auto[1]	auto[0]	202559	1			T1	103		T3	98		T7	1143
fifo_depth[1]	auto[0]	auto[1]	auto[1]	20847	1			T1	75		T3	85		T7	120
fifo_depth[1]	auto[1]	auto[0]	auto[0]	42715	1			T1	104		T2	235		T3	13
fifo_depth[1]	auto[1]	auto[0]	auto[1]	44892	1			T1	82		T2	42		T3	20
fifo_depth[1]	auto[1]	auto[1]	auto[0]	44168	1			T1	68		T2	635		T3	89
fifo_depth[1]	auto[1]	auto[1]	auto[1]	44274	1			T1	96		T2	165		T3	175
fifo_depth[2]	auto[0]	auto[0]	auto[0]	19304	1			T1	54		T3	58		T7	117
fifo_depth[2]	auto[0]	auto[0]	auto[1]	18473	1			T1	37		T3	221		T7	130
fifo_depth[2]	auto[0]	auto[1]	auto[0]	154414	1			T1	70		T3	90		T7	374
fifo_depth[2]	auto[0]	auto[1]	auto[1]	19213	1			T1	40		T3	88		T7	96
fifo_depth[2]	auto[1]	auto[0]	auto[0]	38121	1			T1	77		T2	264		T3	22
fifo_depth[2]	auto[1]	auto[0]	auto[1]	40231	1			T1	54		T2	38		T3	49
fifo_depth[2]	auto[1]	auto[1]	auto[0]	39636	1			T1	56		T2	649		T3	197
fifo_depth[2]	auto[1]	auto[1]	auto[1]	39431	1			T1	75		T2	167		T3	379
fifo_depth[3]	auto[0]	auto[0]	auto[0]	15756	1			T1	25		T3	63		T7	37
fifo_depth[3]	auto[0]	auto[0]	auto[1]	15379	1			T1	24		T3	214		T7	40
fifo_depth[3]	auto[0]	auto[1]	auto[0]	116500	1			T1	29		T3	105		T7	93
fifo_depth[3]	auto[0]	auto[1]	auto[1]	16236	1			T1	22		T3	71		T7	18
fifo_depth[3]	auto[1]	auto[0]	auto[0]	32909	1			T1	44		T2	245		T3	16
fifo_depth[3]	auto[1]	auto[0]	auto[1]	35169	1			T1	32		T2	39		T3	28
fifo_depth[3]	auto[1]	auto[1]	auto[0]	34206	1			T1	23		T2	673		T3	149
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33949	1			T1	54		T2	174		T3	454
fifo_depth[4]	auto[0]	auto[0]	auto[0]	17919	1			T1	7		T3	52		T7	18
fifo_depth[4]	auto[0]	auto[0]	auto[1]	16801	1			T1	7		T3	200		T7	18
fifo_depth[4]	auto[0]	auto[1]	auto[0]	88481	1			T1	10		T3	176		T7	25
fifo_depth[4]	auto[0]	auto[1]	auto[1]	18647	1			T1	12		T3	82		T7	36
fifo_depth[4]	auto[1]	auto[0]	auto[0]	33012	1			T1	16		T2	248		T3	24
fifo_depth[4]	auto[1]	auto[0]	auto[1]	35469	1			T1	15		T2	29		T3	41
fifo_depth[4]	auto[1]	auto[1]	auto[0]	34687	1			T1	8		T2	663		T3	191
fifo_depth[4]	auto[1]	auto[1]	auto[1]	33570	1			T1	26		T2	184		T3	491
fifo_depth[5]	auto[0]	auto[0]	auto[0]	14251	1			T3	61		T7	4		T8	78
fifo_depth[5]	auto[0]	auto[0]	auto[1]	13937	1			T1	3		T3	234		T7	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	72981	1			T1	5		T3	119		T7	4
fifo_depth[5]	auto[0]	auto[1]	auto[1]	15751	1			T1	2		T3	70		T7	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	29190	1			T1	4		T2	224		T3	14
fifo_depth[5]	auto[1]	auto[0]	auto[1]	31977	1			T1	6		T2	42		T3	25
fifo_depth[5]	auto[1]	auto[1]	auto[0]	30688	1			T1	2		T2	635		T3	198
fifo_depth[5]	auto[1]	auto[1]	auto[1]	30611	1			T1	6		T2	176		T3	464
fifo_depth[6]	auto[0]	auto[0]	auto[0]	16420	1			T1	1		T3	55		T7	4
fifo_depth[6]	auto[0]	auto[0]	auto[1]	15684	1			T1	2		T3	239		T7	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	65319	1			T3	135		T7	1		T8	38
fifo_depth[6]	auto[0]	auto[1]	auto[1]	16994	1			T3	81		T7	1		T10	146
fifo_depth[6]	auto[1]	auto[0]	auto[0]	29806	1			T1	3		T2	254		T3	23
fifo_depth[6]	auto[1]	auto[0]	auto[1]	32301	1			T1	2		T2	37		T3	34
fifo_depth[6]	auto[1]	auto[1]	auto[0]	31936	1			T1	1		T2	635		T3	267
fifo_depth[6]	auto[1]	auto[1]	auto[1]	31319	1			T1	1		T2	149		T3	541
fifo_depth[7]	auto[0]	auto[0]	auto[0]	13480	1			T3	64		T8	56		T10	248
fifo_depth[7]	auto[0]	auto[0]	auto[1]	13575	1			T1	1		T3	203		T7	1
fifo_depth[7]	auto[0]	auto[1]	auto[0]	52426	1			T3	103		T8	27		T10	63
fifo_depth[7]	auto[0]	auto[1]	auto[1]	15374	1			T3	74		T10	146		T27	35
fifo_depth[7]	auto[1]	auto[0]	auto[0]	27425	1			T1	2		T2	196		T3	14
fifo_depth[7]	auto[1]	auto[0]	auto[1]	29399	1			T2	39		T3	42		T8	9
fifo_depth[7]	auto[1]	auto[1]	auto[0]	28487	1			T2	577		T3	220		T10	206
fifo_depth[7]	auto[1]	auto[1]	auto[1]	27932	1			T2	172		T3	529		T10	93
fifo_depth[8]	auto[0]	auto[0]	auto[0]	18250	1			T3	36		T8	55		T10	202
fifo_depth[8]	auto[0]	auto[0]	auto[1]	17874	1			T3	274		T7	1		T10	144
fifo_depth[8]	auto[0]	auto[1]	auto[0]	47777	1			T3	205		T8	9		T10	45
fifo_depth[8]	auto[0]	auto[1]	auto[1]	20247	1			T3	65		T7	1		T10	113
fifo_depth[8]	auto[1]	auto[0]	auto[0]	29737	1			T2	192		T3	24		T10	14
fifo_depth[8]	auto[1]	auto[0]	auto[1]	32734	1			T1	1		T2	35		T3	106
fifo_depth[8]	auto[1]	auto[1]	auto[0]	32788	1			T2	485		T3	852		T10	154
fifo_depth[8]	auto[1]	auto[1]	auto[1]	30685	1			T2	127		T3	1442		T10	82
fifo_depth[9]	auto[0]	auto[0]	auto[0]	10962	1			T3	30		T8	36		T10	135
fifo_depth[9]	auto[0]	auto[0]	auto[1]	10335	1			T3	148		T10	96		T27	81
fifo_depth[9]	auto[0]	auto[1]	auto[0]	29053	1			T3	74		T8	3		T10	42
fifo_depth[9]	auto[0]	auto[1]	auto[1]	11956	1			T3	33		T10	83		T27	32
fifo_depth[9]	auto[1]	auto[0]	auto[0]	18973	1			T2	129		T3	14		T10	9
fifo_depth[9]	auto[1]	auto[0]	auto[1]	21117	1			T2	24		T3	47		T10	96
fifo_depth[9]	auto[1]	auto[1]	auto[0]	20446	1			T2	346		T3	288		T10	109
fifo_depth[9]	auto[1]	auto[1]	auto[1]	19806	1			T2	104		T3	440		T10	57
fifo_depth[10]	auto[0]	auto[0]	auto[0]	12718	1			T3	19		T8	20		T10	92
fifo_depth[10]	auto[0]	auto[0]	auto[1]	11745	1			T3	214		T10	74		T27	51
fifo_depth[10]	auto[0]	auto[1]	auto[0]	21141	1			T3	52		T10	17		T21	1
fifo_depth[10]	auto[0]	auto[1]	auto[1]	13016	1			T3	26		T10	49		T27	22
fifo_depth[10]	auto[1]	auto[0]	auto[0]	15741	1			T2	102		T3	22		T10	2
fifo_depth[10]	auto[1]	auto[0]	auto[1]	18630	1			T2	12		T3	77		T10	62
fifo_depth[10]	auto[1]	auto[1]	auto[0]	19787	1			T2	235		T3	808		T10	75
fifo_depth[10]	auto[1]	auto[1]	auto[1]	17296	1			T2	63		T3	500		T10	37
fifo_depth[11]	auto[0]	auto[0]	auto[0]	8183	1			T3	8		T8	21		T10	56
fifo_depth[11]	auto[0]	auto[0]	auto[1]	7700	1			T3	93		T10	38		T27	26
fifo_depth[11]	auto[0]	auto[1]	auto[0]	13131	1			T3	103		T8	1		T10	16
fifo_depth[11]	auto[0]	auto[1]	auto[1]	8738	1			T3	11		T10	26		T27	9
fifo_depth[11]	auto[1]	auto[0]	auto[0]	10028	1			T2	53		T3	14		T10	1
fifo_depth[11]	auto[1]	auto[0]	auto[1]	12068	1			T2	12		T3	47		T10	34
fifo_depth[11]	auto[1]	auto[1]	auto[0]	12050	1			T2	154		T3	199		T10	45
fifo_depth[11]	auto[1]	auto[1]	auto[1]	10905	1			T2	34		T3	470		T10	29
fifo_depth[12]	auto[0]	auto[0]	auto[0]	13105	1			T3	10		T8	6		T10	23
fifo_depth[12]	auto[0]	auto[0]	auto[1]	13320	1			T3	136		T10	24		T27	16
fifo_depth[12]	auto[0]	auto[1]	auto[0]	18558	1			T3	289		T10	6		T20	1
fifo_depth[12]	auto[0]	auto[1]	auto[1]	14599	1			T3	10		T10	13		T27	7
fifo_depth[12]	auto[1]	auto[0]	auto[0]	16685	1			T2	34		T3	22		T10	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	17822	1			T2	3		T3	378		T10	17
fifo_depth[12]	auto[1]	auto[1]	auto[0]	18101	1			T2	66		T3	837		T10	30
fifo_depth[12]	auto[1]	auto[1]	auto[1]	15483	1			T2	16		T3	1240		T10	17
fifo_depth[13]	auto[0]	auto[0]	auto[0]	6784	1			T3	2		T8	6		T10	17
fifo_depth[13]	auto[0]	auto[0]	auto[1]	6917	1			T3	54		T10	11		T27	6
fifo_depth[13]	auto[0]	auto[1]	auto[0]	6760	1			T3	154		T10	3		T23	1
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6826	1			T3	2		T10	1		T27	5
fifo_depth[13]	auto[1]	auto[0]	auto[0]	6423	1			T2	11		T3	12		T10	3
fifo_depth[13]	auto[1]	auto[0]	auto[1]	8291	1			T2	3		T3	35		T10	7
fifo_depth[13]	auto[1]	auto[1]	auto[0]	8074	1			T2	21		T3	154		T10	17
fifo_depth[13]	auto[1]	auto[1]	auto[1]	7128	1			T2	5		T3	372		T10	6
fifo_depth[14]	auto[0]	auto[0]	auto[0]	10219	1			T8	1		T10	8		T27	5
fifo_depth[14]	auto[0]	auto[0]	auto[1]	10662	1			T3	92		T10	4		T27	1
fifo_depth[14]	auto[0]	auto[1]	auto[0]	11006	1			T3	139		T152	9		T30	5
fifo_depth[14]	auto[0]	auto[1]	auto[1]	10741	1			T3	4		T151	6		T100	256
fifo_depth[14]	auto[1]	auto[0]	auto[0]	11404	1			T2	3		T3	21		T11	9
fifo_depth[14]	auto[1]	auto[0]	auto[1]	12346	1			T2	2		T3	268		T10	3
fifo_depth[14]	auto[1]	auto[1]	auto[0]	12429	1			T2	6		T3	655		T10	3
fifo_depth[14]	auto[1]	auto[1]	auto[1]	10206	1			T2	6		T3	359		T10	2
fifo_depth[15]	auto[0]	auto[0]	auto[0]	5857	1			T10	1		T21	1		T151	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	6333	1			T3	29		T100	168		T101	371
fifo_depth[15]	auto[0]	auto[1]	auto[0]	6244	1			T3	149		T20	1		T22	1
fifo_depth[15]	auto[0]	auto[1]	auto[1]	5551	1			T151	1		T100	170		T101	315
fifo_depth[15]	auto[1]	auto[0]	auto[0]	6527	1			T2	3		T3	12		T11	2
fifo_depth[15]	auto[1]	auto[0]	auto[1]	7566	1			T3	29		T10	1		T11	1
fifo_depth[15]	auto[1]	auto[1]	auto[0]	7161	1			T2	2		T3	125		T10	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	5836	1			T2	3		T3	313		T11	1
fifo_depth[16]	auto[0]	auto[0]	auto[0]	29943	1			T27	1		T20	1		T100	1650
fifo_depth[16]	auto[0]	auto[0]	auto[1]	25040	1			T3	51		T27	1		T20	1
fifo_depth[16]	auto[0]	auto[1]	auto[0]	28783	1			T3	1909		T20	1		T22	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	19201	1			T26	1		T123	2		T151	1
fifo_depth[16]	auto[1]	auto[0]	auto[0]	25433	1			T2	2		T3	492		T11	3
fifo_depth[16]	auto[1]	auto[0]	auto[1]	27647	1			T3	965		T10	2		T20	2
fifo_depth[16]	auto[1]	auto[1]	auto[0]	32039	1			T3	780		T10	3		T11	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	26624	1			T3	1389		T27	2		T29	1