Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13225392	1			T1	11678		T2	15502		T3	9696
all_pins[1]	13225392	1			T1	11678		T2	15502		T3	9696
all_pins[2]	13225392	1			T1	11678		T2	15502		T3	9696

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	28108786	1			T1	26046		T2	41253		T3	25408
values[0x1]	11567390	1			T1	8988		T2	5253		T3	3680
transitions[0x0=>0x1]	10086275	1			T1	8947		T2	5217		T3	3611
transitions[0x1=>0x0]	10086292	1			T1	8947		T2	5217		T3	3611

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13178785	1			T1	11619		T2	15465		T3	9619
all_pins[0]	values[0x1]	46607	1			T1	59		T2	37		T3	77
all_pins[0]	transitions[0x0=>0x1]	46553	1			T1	59		T2	37		T3	77
all_pins[0]	transitions[0x1=>0x0]	5214392	1			T3	52		T7	54921		T8	19286
all_pins[1]	values[0x0]	6919038	1			T1	2749		T2	10286		T3	6145
all_pins[1]	values[0x1]	6306354	1			T1	8929		T2	5216		T3	3551
all_pins[1]	transitions[0x0=>0x1]	6269728	1			T1	8888		T2	5180		T3	3493
all_pins[1]	transitions[0x1=>0x0]	9981	1			T1	18		T2	1		T3	19
all_pins[2]	values[0x0]	8010963	1			T1	11678		T2	15502		T3	9644
all_pins[2]	values[0x1]	5214429	1			T3	52		T7	54921		T8	19286
all_pins[2]	transitions[0x0=>0x1]	3769994	1			T3	41		T7	39502		T8	17643
all_pins[2]	transitions[0x1=>0x0]	4861919	1			T1	8929		T2	5216		T3	3540