Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 941 1 T7 4 T54 7 T4 14
all_values[1] 941 1 T7 4 T54 7 T4 14
all_values[2] 941 1 T7 4 T54 7 T4 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1393 1 T7 5 T54 10 T4 20
auto[1] 1430 1 T7 7 T54 11 T4 22


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1070 1 T7 4 T54 6 T4 17
auto[1] 1753 1 T7 8 T54 15 T4 25


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1632 1 T7 5 T54 9 T4 26
auto[1] 1191 1 T7 7 T54 12 T4 16


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 182 1 T7 2 T54 1 T4 1
all_values[0] auto[0] auto[0] auto[1] 85 1 T54 1 T4 1 T68 1
all_values[0] auto[0] auto[1] auto[0] 197 1 T7 1 T54 2 T4 7
all_values[0] auto[0] auto[1] auto[1] 77 1 T4 1 T140 1 T68 1
all_values[0] auto[1] auto[0] auto[1] 190 1 T54 1 T4 4 T68 3
all_values[0] auto[1] auto[1] auto[1] 210 1 T7 1 T54 2 T140 1
all_values[1] auto[0] auto[0] auto[0] 151 1 T4 3 T140 2 T68 1
all_values[1] auto[0] auto[0] auto[1] 125 1 T54 1 T4 3 T68 1
all_values[1] auto[0] auto[1] auto[0] 164 1 T4 2 T140 1 T68 1
all_values[1] auto[0] auto[1] auto[1] 93 1 T7 1 T54 1 T4 1
all_values[1] auto[1] auto[0] auto[1] 195 1 T7 1 T54 2 T4 3
all_values[1] auto[1] auto[1] auto[1] 213 1 T7 2 T54 3 T4 2
all_values[2] auto[0] auto[0] auto[0] 190 1 T7 1 T54 2 T4 3
all_values[2] auto[0] auto[0] auto[1] 85 1 T140 1 T69 1 T108 1
all_values[2] auto[0] auto[1] auto[0] 186 1 T54 1 T4 1 T140 2
all_values[2] auto[0] auto[1] auto[1] 97 1 T4 3 T70 2 T113 1
all_values[2] auto[1] auto[0] auto[1] 190 1 T7 1 T54 2 T4 2
all_values[2] auto[1] auto[1] auto[1] 193 1 T7 2 T54 2 T4 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%