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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.80 99.55 98.65 100.00 96.30 98.47 99.49 99.17


Total test records in report: 728
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T536 /workspace/coverage/default/40.hmac_datapath_stress.1299906519 Feb 25 02:34:11 PM PST 24 Feb 25 02:36:30 PM PST 24 10436163209 ps
T537 /workspace/coverage/default/5.hmac_error.3250527707 Feb 25 02:31:32 PM PST 24 Feb 25 02:34:26 PM PST 24 3333142997 ps
T58 /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.3106670838 Feb 25 02:35:46 PM PST 24 Feb 25 03:04:30 PM PST 24 298479460471 ps
T538 /workspace/coverage/default/45.hmac_datapath_stress.462336126 Feb 25 02:34:25 PM PST 24 Feb 25 02:35:14 PM PST 24 1082919683 ps
T539 /workspace/coverage/default/22.hmac_wipe_secret.233008670 Feb 25 02:32:57 PM PST 24 Feb 25 02:33:54 PM PST 24 4301036901 ps
T17 /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.615786576 Feb 25 02:35:25 PM PST 24 Feb 25 02:38:36 PM PST 24 4094425605 ps
T540 /workspace/coverage/default/10.hmac_test_hmac_vectors.2548068078 Feb 25 02:31:59 PM PST 24 Feb 25 02:32:00 PM PST 24 80057912 ps
T541 /workspace/coverage/default/12.hmac_stress_all.1610134705 Feb 25 02:32:12 PM PST 24 Feb 25 02:32:13 PM PST 24 61818056 ps
T542 /workspace/coverage/default/49.hmac_wipe_secret.156906230 Feb 25 02:34:55 PM PST 24 Feb 25 02:35:03 PM PST 24 651227577 ps
T543 /workspace/coverage/default/26.hmac_datapath_stress.4208977107 Feb 25 02:33:17 PM PST 24 Feb 25 02:34:41 PM PST 24 3218288637 ps
T544 /workspace/coverage/default/32.hmac_burst_wr.554106317 Feb 25 02:33:34 PM PST 24 Feb 25 02:33:44 PM PST 24 9664836617 ps
T545 /workspace/coverage/default/14.hmac_alert_test.1222431224 Feb 25 02:32:18 PM PST 24 Feb 25 02:32:20 PM PST 24 73719885 ps
T546 /workspace/coverage/default/41.hmac_burst_wr.1824370224 Feb 25 02:34:11 PM PST 24 Feb 25 02:35:01 PM PST 24 2756356587 ps
T547 /workspace/coverage/default/36.hmac_wipe_secret.3234747797 Feb 25 02:33:53 PM PST 24 Feb 25 02:35:14 PM PST 24 25990085518 ps
T16 /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2208119961 Feb 25 02:33:08 PM PST 24 Feb 25 02:56:57 PM PST 24 149469697099 ps
T548 /workspace/coverage/default/16.hmac_datapath_stress.2877706721 Feb 25 02:32:18 PM PST 24 Feb 25 02:32:19 PM PST 24 18467552 ps
T549 /workspace/coverage/default/10.hmac_error.1994287974 Feb 25 02:32:01 PM PST 24 Feb 25 02:33:45 PM PST 24 25437645249 ps
T550 /workspace/coverage/default/22.hmac_long_msg.3129205092 Feb 25 02:32:51 PM PST 24 Feb 25 02:33:20 PM PST 24 8718751767 ps
T551 /workspace/coverage/default/19.hmac_long_msg.52947638 Feb 25 02:32:51 PM PST 24 Feb 25 02:33:57 PM PST 24 4870350372 ps
T552 /workspace/coverage/default/22.hmac_alert_test.2725347484 Feb 25 02:32:58 PM PST 24 Feb 25 02:32:59 PM PST 24 40185546 ps
T553 /workspace/coverage/default/8.hmac_smoke.558862812 Feb 25 02:31:51 PM PST 24 Feb 25 02:31:55 PM PST 24 3154176607 ps
T554 /workspace/coverage/default/25.hmac_stress_all.1766705107 Feb 25 02:33:11 PM PST 24 Feb 25 02:41:33 PM PST 24 38295232876 ps
T555 /workspace/coverage/default/37.hmac_long_msg.3466228125 Feb 25 02:34:00 PM PST 24 Feb 25 02:34:17 PM PST 24 1802937337 ps
T556 /workspace/coverage/default/34.hmac_smoke.1601923038 Feb 25 02:33:40 PM PST 24 Feb 25 02:33:41 PM PST 24 355421903 ps
T557 /workspace/coverage/default/48.hmac_stress_all.3882379536 Feb 25 02:34:48 PM PST 24 Feb 25 02:48:49 PM PST 24 65443843541 ps
T558 /workspace/coverage/default/13.hmac_test_hmac_vectors.2865226346 Feb 25 02:32:20 PM PST 24 Feb 25 02:32:21 PM PST 24 29181878 ps
T559 /workspace/coverage/default/44.hmac_back_pressure.2793299209 Feb 25 02:34:28 PM PST 24 Feb 25 02:35:22 PM PST 24 2699386062 ps
T560 /workspace/coverage/default/43.hmac_alert_test.3282448653 Feb 25 02:34:26 PM PST 24 Feb 25 02:34:27 PM PST 24 13784713 ps
T561 /workspace/coverage/default/25.hmac_smoke.2601985818 Feb 25 02:33:06 PM PST 24 Feb 25 02:33:09 PM PST 24 2213709720 ps
T562 /workspace/coverage/default/1.hmac_datapath_stress.2276843571 Feb 25 02:31:14 PM PST 24 Feb 25 02:32:52 PM PST 24 3758749975 ps
T563 /workspace/coverage/default/20.hmac_stress_all.607008386 Feb 25 02:32:46 PM PST 24 Feb 25 03:06:39 PM PST 24 117105323075 ps
T564 /workspace/coverage/default/34.hmac_error.1417103781 Feb 25 02:33:40 PM PST 24 Feb 25 02:34:40 PM PST 24 2583550375 ps
T565 /workspace/coverage/default/47.hmac_back_pressure.2654914755 Feb 25 02:34:34 PM PST 24 Feb 25 02:35:35 PM PST 24 10227911324 ps
T566 /workspace/coverage/default/19.hmac_datapath_stress.325331901 Feb 25 02:32:48 PM PST 24 Feb 25 02:34:05 PM PST 24 1380391756 ps
T567 /workspace/coverage/default/1.hmac_back_pressure.2261279031 Feb 25 02:31:16 PM PST 24 Feb 25 02:32:04 PM PST 24 2804533264 ps
T18 /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.4261141585 Feb 25 02:35:08 PM PST 24 Feb 25 02:44:59 PM PST 24 56768864546 ps
T568 /workspace/coverage/default/48.hmac_alert_test.2116548691 Feb 25 02:34:51 PM PST 24 Feb 25 02:34:52 PM PST 24 44091047 ps
T569 /workspace/coverage/default/4.hmac_burst_wr.3797086972 Feb 25 02:31:32 PM PST 24 Feb 25 02:31:57 PM PST 24 1754548461 ps
T570 /workspace/coverage/default/25.hmac_long_msg.420710575 Feb 25 02:33:09 PM PST 24 Feb 25 02:34:11 PM PST 24 1113171501 ps
T571 /workspace/coverage/default/32.hmac_error.1681836847 Feb 25 02:33:36 PM PST 24 Feb 25 02:34:19 PM PST 24 1610386097 ps
T572 /workspace/coverage/default/19.hmac_stress_all.1830678092 Feb 25 02:32:46 PM PST 24 Feb 25 02:49:37 PM PST 24 56905084474 ps
T573 /workspace/coverage/default/30.hmac_stress_all.3802179182 Feb 25 02:33:38 PM PST 24 Feb 25 03:01:47 PM PST 24 66699755519 ps
T574 /workspace/coverage/default/47.hmac_stress_all.3785496373 Feb 25 02:34:35 PM PST 24 Feb 25 02:35:47 PM PST 24 7869138790 ps
T575 /workspace/coverage/default/18.hmac_alert_test.1478108239 Feb 25 02:32:48 PM PST 24 Feb 25 02:32:49 PM PST 24 36127784 ps
T576 /workspace/coverage/default/30.hmac_burst_wr.771393109 Feb 25 02:33:31 PM PST 24 Feb 25 02:34:05 PM PST 24 3692578373 ps
T577 /workspace/coverage/default/8.hmac_test_hmac_vectors.383459514 Feb 25 02:31:50 PM PST 24 Feb 25 02:31:51 PM PST 24 52160147 ps
T578 /workspace/coverage/default/27.hmac_burst_wr.1400444355 Feb 25 02:33:10 PM PST 24 Feb 25 02:33:39 PM PST 24 615473417 ps
T579 /workspace/coverage/default/15.hmac_datapath_stress.2286521255 Feb 25 02:32:27 PM PST 24 Feb 25 02:33:43 PM PST 24 5745140563 ps
T580 /workspace/coverage/default/11.hmac_smoke.3836793466 Feb 25 02:32:02 PM PST 24 Feb 25 02:32:05 PM PST 24 305686595 ps
T581 /workspace/coverage/default/23.hmac_wipe_secret.1326935456 Feb 25 02:32:55 PM PST 24 Feb 25 02:32:58 PM PST 24 94260164 ps
T582 /workspace/coverage/default/34.hmac_alert_test.3973044535 Feb 25 02:33:44 PM PST 24 Feb 25 02:33:45 PM PST 24 12909690 ps
T583 /workspace/coverage/default/21.hmac_back_pressure.2089768842 Feb 25 02:32:53 PM PST 24 Feb 25 02:33:19 PM PST 24 3998072795 ps
T584 /workspace/coverage/default/6.hmac_burst_wr.2195646657 Feb 25 02:31:47 PM PST 24 Feb 25 02:31:59 PM PST 24 543628996 ps
T585 /workspace/coverage/default/18.hmac_error.4267638983 Feb 25 02:32:48 PM PST 24 Feb 25 02:34:10 PM PST 24 12953900017 ps
T586 /workspace/coverage/default/28.hmac_test_hmac_vectors.1822195241 Feb 25 02:33:23 PM PST 24 Feb 25 02:33:24 PM PST 24 44615123 ps
T587 /workspace/coverage/default/19.hmac_test_sha_vectors.2729773253 Feb 25 02:32:48 PM PST 24 Feb 25 02:40:42 PM PST 24 44421119144 ps
T588 /workspace/coverage/default/30.hmac_alert_test.1874327367 Feb 25 02:33:31 PM PST 24 Feb 25 02:33:32 PM PST 24 11558819 ps
T589 /workspace/coverage/default/3.hmac_smoke.4216295144 Feb 25 02:31:28 PM PST 24 Feb 25 02:31:29 PM PST 24 113669432 ps
T590 /workspace/coverage/default/7.hmac_long_msg.2337612961 Feb 25 02:31:51 PM PST 24 Feb 25 02:33:25 PM PST 24 13971375731 ps
T591 /workspace/coverage/default/45.hmac_test_sha_vectors.749852480 Feb 25 02:34:35 PM PST 24 Feb 25 02:41:35 PM PST 24 120062858344 ps
T592 /workspace/coverage/default/6.hmac_smoke.1951826176 Feb 25 02:31:45 PM PST 24 Feb 25 02:31:49 PM PST 24 400050408 ps
T593 /workspace/coverage/default/7.hmac_wipe_secret.1770594244 Feb 25 02:32:03 PM PST 24 Feb 25 02:32:56 PM PST 24 17926582146 ps
T594 /workspace/coverage/default/39.hmac_long_msg.335711603 Feb 25 02:34:11 PM PST 24 Feb 25 02:35:08 PM PST 24 17520763613 ps
T595 /workspace/coverage/cover_reg_top/32.hmac_intr_test.329060858 Feb 25 01:18:08 PM PST 24 Feb 25 01:18:09 PM PST 24 41201960 ps
T596 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2025363913 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:15 PM PST 24 27384001 ps
T597 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4284934979 Feb 25 01:17:47 PM PST 24 Feb 25 01:17:48 PM PST 24 12391325 ps
T598 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2720697956 Feb 25 01:18:00 PM PST 24 Feb 25 01:18:02 PM PST 24 54320837 ps
T599 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4169532380 Feb 25 01:18:16 PM PST 24 Feb 25 01:18:17 PM PST 24 29253348 ps
T600 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3945396717 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:03 PM PST 24 31217923 ps
T601 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3846236085 Feb 25 01:17:54 PM PST 24 Feb 25 01:20:32 PM PST 24 41593757232 ps
T602 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3691804117 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:15 PM PST 24 60608299 ps
T51 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.861117934 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:58 PM PST 24 624521605 ps
T603 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2645641711 Feb 25 01:18:07 PM PST 24 Feb 25 01:18:10 PM PST 24 261802984 ps
T604 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.624804369 Feb 25 01:18:16 PM PST 24 Feb 25 01:18:17 PM PST 24 17881948 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.837760423 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:56 PM PST 24 17615576 ps
T606 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1351605322 Feb 25 01:18:00 PM PST 24 Feb 25 01:18:02 PM PST 24 84565086 ps
T607 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.453967445 Feb 25 01:18:15 PM PST 24 Feb 25 01:26:45 PM PST 24 62009133172 ps
T608 /workspace/coverage/cover_reg_top/49.hmac_intr_test.1466326728 Feb 25 01:18:17 PM PST 24 Feb 25 01:18:18 PM PST 24 41852925 ps
T609 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3914275826 Feb 25 01:18:01 PM PST 24 Feb 25 01:21:04 PM PST 24 43064748490 ps
T79 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.273457951 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:57 PM PST 24 36802458 ps
T610 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2702931029 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:12 PM PST 24 12101316 ps
T611 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2746736370 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:04 PM PST 24 170931216 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4237616755 Feb 25 01:17:56 PM PST 24 Feb 25 01:18:03 PM PST 24 1664056085 ps
T612 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1723943263 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:03 PM PST 24 38267933 ps
T613 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2331845487 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:59 PM PST 24 150854334 ps
T614 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1240643927 Feb 25 01:18:12 PM PST 24 Feb 25 01:26:43 PM PST 24 52525261960 ps
T615 /workspace/coverage/cover_reg_top/27.hmac_intr_test.2064151730 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:12 PM PST 24 35829966 ps
T89 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4031810133 Feb 25 01:17:52 PM PST 24 Feb 25 01:17:59 PM PST 24 1311386994 ps
T616 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2357400986 Feb 25 01:18:18 PM PST 24 Feb 25 01:18:19 PM PST 24 93686695 ps
T617 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.119713121 Feb 25 01:17:57 PM PST 24 Feb 25 01:17:58 PM PST 24 58434003 ps
T52 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.840103020 Feb 25 01:18:08 PM PST 24 Feb 25 01:18:10 PM PST 24 65705844 ps
T618 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.384014121 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:18 PM PST 24 53298081 ps
T53 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3654721007 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:08 PM PST 24 107338651 ps
T81 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1669479024 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 71354569 ps
T619 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1867418312 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:14 PM PST 24 82493746 ps
T620 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3151256499 Feb 25 01:17:54 PM PST 24 Feb 25 01:17:55 PM PST 24 18853101 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.824321845 Feb 25 01:17:49 PM PST 24 Feb 25 01:17:51 PM PST 24 18066967 ps
T622 /workspace/coverage/cover_reg_top/21.hmac_intr_test.1786207816 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:14 PM PST 24 11374975 ps
T623 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.474949979 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:13 PM PST 24 372880511 ps
T624 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3249552492 Feb 25 01:17:47 PM PST 24 Feb 25 01:17:49 PM PST 24 115808423 ps
T625 /workspace/coverage/cover_reg_top/31.hmac_intr_test.178219726 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:16 PM PST 24 52678778 ps
T626 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1650819290 Feb 25 01:18:24 PM PST 24 Feb 25 01:18:25 PM PST 24 34033420 ps
T627 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3175894974 Feb 25 01:18:16 PM PST 24 Feb 25 01:18:17 PM PST 24 37235575 ps
T628 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2173947061 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:05 PM PST 24 115371376 ps
T629 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1215312433 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:04 PM PST 24 532375323 ps
T630 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2994964768 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:07 PM PST 24 209352353 ps
T631 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3401712121 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:13 PM PST 24 63311768 ps
T632 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1937092031 Feb 25 01:17:57 PM PST 24 Feb 25 01:17:59 PM PST 24 74192716 ps
T633 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2395456205 Feb 25 01:17:56 PM PST 24 Feb 25 01:17:59 PM PST 24 51103619 ps
T634 /workspace/coverage/cover_reg_top/3.hmac_intr_test.129913511 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 24373326 ps
T635 /workspace/coverage/cover_reg_top/13.hmac_intr_test.2981488767 Feb 25 01:18:04 PM PST 24 Feb 25 01:18:05 PM PST 24 18387257 ps
T82 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.796999245 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 82919231 ps
T636 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1877195550 Feb 25 01:18:16 PM PST 24 Feb 25 01:18:17 PM PST 24 50942848 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1146914132 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:06 PM PST 24 538304983 ps
T638 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.29066283 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:07 PM PST 24 62397369 ps
T639 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2447810919 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:05 PM PST 24 143492567 ps
T640 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2722509049 Feb 25 01:18:21 PM PST 24 Feb 25 01:18:22 PM PST 24 15303721 ps
T83 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1547507739 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:11 PM PST 24 66027575 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1654983345 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:18 PM PST 24 86449832 ps
T642 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2518364781 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:06 PM PST 24 22360953 ps
T643 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4264851569 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:12 PM PST 24 55151036 ps
T644 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1784583999 Feb 25 01:18:17 PM PST 24 Feb 25 01:18:18 PM PST 24 10655345 ps
T645 /workspace/coverage/cover_reg_top/17.hmac_intr_test.302883164 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:11 PM PST 24 56024409 ps
T646 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.291661806 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:03 PM PST 24 37655269 ps
T647 /workspace/coverage/cover_reg_top/2.hmac_intr_test.4247102251 Feb 25 01:17:57 PM PST 24 Feb 25 01:17:58 PM PST 24 48298934 ps
T648 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1749573713 Feb 25 01:17:54 PM PST 24 Feb 25 01:17:55 PM PST 24 269680161 ps
T649 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1934889525 Feb 25 01:18:00 PM PST 24 Feb 25 01:18:00 PM PST 24 29645519 ps
T650 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3990142349 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:04 PM PST 24 46106124 ps
T84 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.554157953 Feb 25 01:17:56 PM PST 24 Feb 25 01:17:57 PM PST 24 261696300 ps
T651 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1609202602 Feb 25 01:17:54 PM PST 24 Feb 25 01:17:56 PM PST 24 357347096 ps
T85 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3228378909 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:53 PM PST 24 83632999 ps
T652 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2851329111 Feb 25 01:18:17 PM PST 24 Feb 25 01:18:18 PM PST 24 27929660 ps
T653 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.523080581 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:15 PM PST 24 117223990 ps
T654 /workspace/coverage/cover_reg_top/10.hmac_intr_test.4022034545 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:03 PM PST 24 36695530 ps
T90 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1406130967 Feb 25 01:17:41 PM PST 24 Feb 25 01:17:48 PM PST 24 2493958025 ps
T655 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1289949973 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:03 PM PST 24 17146899 ps
T656 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1988847361 Feb 25 01:17:47 PM PST 24 Feb 25 01:17:48 PM PST 24 19482451 ps
T657 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1994134650 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:15 PM PST 24 15616301 ps
T658 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1848848628 Feb 25 01:18:20 PM PST 24 Feb 25 01:18:21 PM PST 24 14164590 ps
T141 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2550938209 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:05 PM PST 24 234032307 ps
T659 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3812553593 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:56 PM PST 24 78109849 ps
T91 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1102373741 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:57 PM PST 24 327065743 ps
T86 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1507635507 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:03 PM PST 24 46290297 ps
T660 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4285237825 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:02 PM PST 24 17733621 ps
T661 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2420989628 Feb 25 01:17:54 PM PST 24 Feb 25 01:17:55 PM PST 24 14455531 ps
T662 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3647255690 Feb 25 01:17:42 PM PST 24 Feb 25 01:17:43 PM PST 24 159018104 ps
T663 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2197162905 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:16 PM PST 24 25601937 ps
T664 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2782041681 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 101789327 ps
T665 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3280565936 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:58 PM PST 24 86253561 ps
T144 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3810756217 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:05 PM PST 24 76486604 ps
T87 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.86973651 Feb 25 01:17:47 PM PST 24 Feb 25 01:17:49 PM PST 24 217429485 ps
T147 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2065740284 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:58 PM PST 24 1595063106 ps
T666 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.115058948 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:17 PM PST 24 122445357 ps
T667 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2714143014 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:11 PM PST 24 17007178 ps
T668 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1333210481 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:06 PM PST 24 63232534 ps
T142 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.233319056 Feb 25 01:17:44 PM PST 24 Feb 25 01:17:46 PM PST 24 403643028 ps
T88 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3754146680 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 102008630 ps
T669 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2127165468 Feb 25 01:17:48 PM PST 24 Feb 25 01:17:49 PM PST 24 35709079 ps
T670 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1142642012 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 163510724 ps
T671 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1852310190 Feb 25 01:18:17 PM PST 24 Feb 25 01:18:18 PM PST 24 18972155 ps
T672 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2211486144 Feb 25 01:18:04 PM PST 24 Feb 25 01:18:06 PM PST 24 233061382 ps
T673 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1310383692 Feb 25 01:17:42 PM PST 24 Feb 25 01:17:43 PM PST 24 247090174 ps
T674 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.117406816 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:56 PM PST 24 44529125 ps
T675 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2800907021 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:03 PM PST 24 10983740 ps
T676 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2895790746 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:15 PM PST 24 427025540 ps
T677 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3282433156 Feb 25 01:18:19 PM PST 24 Feb 25 01:18:20 PM PST 24 24027045 ps
T92 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2377796985 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 13027841 ps
T678 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2062318512 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:13 PM PST 24 12427070 ps
T679 /workspace/coverage/cover_reg_top/42.hmac_intr_test.828927382 Feb 25 01:18:20 PM PST 24 Feb 25 01:18:21 PM PST 24 11974298 ps
T94 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2608740220 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:14 PM PST 24 15037934 ps
T680 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.138861666 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 24618055 ps
T681 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2963955969 Feb 25 01:18:18 PM PST 24 Feb 25 01:18:19 PM PST 24 16354260 ps
T682 /workspace/coverage/cover_reg_top/28.hmac_intr_test.338134554 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:15 PM PST 24 15972056 ps
T683 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3591894443 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:13 PM PST 24 233884304 ps
T684 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1505587825 Feb 25 01:17:57 PM PST 24 Feb 25 01:17:59 PM PST 24 101390416 ps
T685 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2525625157 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:15 PM PST 24 53124669 ps
T686 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2080297288 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:14 PM PST 24 22279907 ps
T687 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.667287496 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:14 PM PST 24 49781640 ps
T688 /workspace/coverage/cover_reg_top/4.hmac_intr_test.428666974 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:55 PM PST 24 44282545 ps
T689 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2298710049 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:11 PM PST 24 46067048 ps
T690 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.798745794 Feb 25 01:18:04 PM PST 24 Feb 25 01:18:07 PM PST 24 228626600 ps
T691 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4275823657 Feb 25 01:17:54 PM PST 24 Feb 25 01:17:55 PM PST 24 82485646 ps
T692 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1407255944 Feb 25 01:18:09 PM PST 24 Feb 25 01:18:10 PM PST 24 24746764 ps
T146 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2642286032 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:13 PM PST 24 57690495 ps
T143 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2961394943 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:04 PM PST 24 115663892 ps
T693 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1152278616 Feb 25 01:18:02 PM PST 24 Feb 25 01:18:05 PM PST 24 232196683 ps
T148 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1997936637 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:11 PM PST 24 105786680 ps
T694 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2172254622 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:18 PM PST 24 630635007 ps
T695 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1421749368 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:57 PM PST 24 111367495 ps
T696 /workspace/coverage/cover_reg_top/14.hmac_intr_test.154462422 Feb 25 01:18:12 PM PST 24 Feb 25 01:18:13 PM PST 24 43380230 ps
T697 /workspace/coverage/cover_reg_top/11.hmac_intr_test.482185267 Feb 25 01:18:01 PM PST 24 Feb 25 01:18:02 PM PST 24 41437306 ps
T698 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4077167945 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:05 PM PST 24 240930112 ps
T699 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2992816429 Feb 25 01:18:00 PM PST 24 Feb 25 01:18:03 PM PST 24 14826644 ps
T700 /workspace/coverage/cover_reg_top/46.hmac_intr_test.798800314 Feb 25 01:18:19 PM PST 24 Feb 25 01:18:20 PM PST 24 59256964 ps
T149 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.904578332 Feb 25 01:18:07 PM PST 24 Feb 25 01:18:09 PM PST 24 461251548 ps
T701 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3054045576 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:16 PM PST 24 89709641 ps
T93 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.596924567 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:16 PM PST 24 99152580 ps
T702 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.745760029 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:08 PM PST 24 511746627 ps
T703 /workspace/coverage/cover_reg_top/16.hmac_intr_test.170450334 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:13 PM PST 24 14468828 ps
T150 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2226596311 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:13 PM PST 24 663662627 ps
T704 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2673763877 Feb 25 01:18:05 PM PST 24 Feb 25 01:18:07 PM PST 24 327639326 ps
T145 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.152819415 Feb 25 01:17:57 PM PST 24 Feb 25 01:17:58 PM PST 24 119474462 ps
T705 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2636852773 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:15 PM PST 24 15046116 ps
T706 /workspace/coverage/cover_reg_top/0.hmac_intr_test.288726220 Feb 25 01:17:44 PM PST 24 Feb 25 01:17:44 PM PST 24 28377021 ps
T707 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1266544342 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:57 PM PST 24 160122407 ps
T708 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.407197279 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 19026461 ps
T95 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3190099854 Feb 25 01:17:41 PM PST 24 Feb 25 01:17:43 PM PST 24 136869826 ps
T709 /workspace/coverage/cover_reg_top/8.hmac_intr_test.1516434363 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 26993587 ps
T710 /workspace/coverage/cover_reg_top/41.hmac_intr_test.2898380515 Feb 25 01:18:21 PM PST 24 Feb 25 01:18:22 PM PST 24 42731145 ps
T711 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2606824925 Feb 25 01:18:13 PM PST 24 Feb 25 01:18:14 PM PST 24 513278733 ps
T712 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.341705510 Feb 25 01:17:55 PM PST 24 Feb 25 01:17:56 PM PST 24 58373934 ps
T96 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.909177639 Feb 25 01:18:07 PM PST 24 Feb 25 01:18:07 PM PST 24 41886605 ps
T713 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3205519445 Feb 25 01:17:52 PM PST 24 Feb 25 01:17:55 PM PST 24 1597726227 ps
T714 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.840343948 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:16 PM PST 24 325514883 ps
T715 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4200843630 Feb 25 01:18:15 PM PST 24 Feb 25 01:18:16 PM PST 24 271108949 ps
T716 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1480136673 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:06 PM PST 24 134388597 ps
T717 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2997976493 Feb 25 01:17:45 PM PST 24 Feb 25 01:17:47 PM PST 24 210157263 ps
T718 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2904588550 Feb 25 01:17:53 PM PST 24 Feb 25 01:17:54 PM PST 24 22753217 ps
T719 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2589945639 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:16 PM PST 24 179674934 ps
T720 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3723032164 Feb 25 01:17:49 PM PST 24 Feb 25 01:17:53 PM PST 24 2615962753 ps
T721 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.984859189 Feb 25 01:18:03 PM PST 24 Feb 25 01:18:04 PM PST 24 16776146 ps
T722 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.692376592 Feb 25 01:18:14 PM PST 24 Feb 25 01:18:16 PM PST 24 402546437 ps
T723 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1054410503 Feb 25 01:17:54 PM PST 24 Feb 25 01:25:14 PM PST 24 45673370893 ps
T724 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1886307849 Feb 25 01:18:20 PM PST 24 Feb 25 01:18:21 PM PST 24 104151274 ps
T725 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2207226548 Feb 25 01:18:11 PM PST 24 Feb 25 01:18:13 PM PST 24 922988827 ps
T726 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.884365098 Feb 25 01:17:43 PM PST 24 Feb 25 01:26:18 PM PST 24 109559293545 ps
T727 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2809693501 Feb 25 01:18:09 PM PST 24 Feb 25 01:18:10 PM PST 24 12103763 ps
T728 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.765434558 Feb 25 01:18:10 PM PST 24 Feb 25 01:18:10 PM PST 24 57229813 ps

Test location /workspace/coverage/default/0.hmac_stress_all.78427143
Short name T3
Test name
Test status
Simulation time 2004017083 ps
CPU time 93.29 seconds
Started Feb 25 02:31:18 PM PST 24
Finished Feb 25 02:32:52 PM PST 24
Peak memory 199556 kb
Host smart-33fa93bd-d810-4ec7-8b9e-6573a8541572
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78427143 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.78427143
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_error.2572356281
Short name T8
Test name
Test status
Simulation time 3151216689 ps
CPU time 115.95 seconds
Started Feb 25 02:31:23 PM PST 24
Finished Feb 25 02:33:19 PM PST 24
Peak memory 199680 kb
Host smart-9da8679b-c8f1-4d26-b5c9-36237a5e1df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572356281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.2572356281
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/96.hmac_stress_all_with_rand_reset.2173401715
Short name T4
Test name
Test status
Simulation time 21769780359 ps
CPU time 618.42 seconds
Started Feb 25 02:35:04 PM PST 24
Finished Feb 25 02:45:25 PM PST 24
Peak memory 245788 kb
Host smart-c5e580ba-ebc3-4cd4-8494-c8e498e39bb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173401715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.hmac_stress_all_with_rand_reset.2173401715
Directory /workspace/96.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3654721007
Short name T53
Test name
Test status
Simulation time 107338651 ps
CPU time 2.4 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:08 PM PST 24
Peak memory 198752 kb
Host smart-cbbb6374-37f6-40f1-a933-37dcdc31124c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654721007 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3654721007
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/20.hmac_stress_all_with_rand_reset.4225003188
Short name T5
Test name
Test status
Simulation time 259797328253 ps
CPU time 2076.55 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 03:07:24 PM PST 24
Peak memory 257440 kb
Host smart-4b03eec8-7e2e-4d5a-8e24-be19f622f80d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225003188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all_with_rand_reset.4225003188
Directory /workspace/20.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3137363737
Short name T100
Test name
Test status
Simulation time 19059121758 ps
CPU time 878.31 seconds
Started Feb 25 02:34:52 PM PST 24
Finished Feb 25 02:49:32 PM PST 24
Peak memory 215988 kb
Host smart-48ff25f8-574c-43a8-bfd5-c9c9efa3dfe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137363737 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3137363737
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.501706227
Short name T37
Test name
Test status
Simulation time 62608131 ps
CPU time 0.88 seconds
Started Feb 25 02:31:26 PM PST 24
Finished Feb 25 02:31:27 PM PST 24
Peak memory 216544 kb
Host smart-f6100339-4026-4744-8df8-7bb8eba9e9d3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501706227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.501706227
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/17.hmac_stress_all.333335511
Short name T7
Test name
Test status
Simulation time 85882112465 ps
CPU time 1039.61 seconds
Started Feb 25 02:32:40 PM PST 24
Finished Feb 25 02:50:00 PM PST 24
Peak memory 199672 kb
Host smart-17506122-a1df-4054-9720-ade8ed8541f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333335511 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.333335511
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1669479024
Short name T81
Test name
Test status
Simulation time 71354569 ps
CPU time 0.64 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 194540 kb
Host smart-0b6c29f8-d6ca-4678-81e3-22219526212f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669479024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1669479024
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3343110005
Short name T25
Test name
Test status
Simulation time 3465843376 ps
CPU time 177.54 seconds
Started Feb 25 02:33:56 PM PST 24
Finished Feb 25 02:36:54 PM PST 24
Peak memory 199652 kb
Host smart-77161db2-72e2-40ba-a9fd-9967dcaa825f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3343110005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3343110005
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2670180254
Short name T102
Test name
Test status
Simulation time 77973090010 ps
CPU time 926.61 seconds
Started Feb 25 02:34:26 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 223024 kb
Host smart-683c9f47-3f15-4569-84e5-0e2fec6d8a7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670180254 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2670180254
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2806683129
Short name T20
Test name
Test status
Simulation time 1615759486 ps
CPU time 59.67 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:33:03 PM PST 24
Peak memory 232312 kb
Host smart-f466b692-0643-4bf8-8346-da037499a674
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806683129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2806683129
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_alert_test.1627648867
Short name T209
Test name
Test status
Simulation time 28314678 ps
CPU time 0.59 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:12 PM PST 24
Peak memory 194972 kb
Host smart-4d10ac47-93d5-47b4-b535-0b997d24a085
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627648867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.1627648867
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3778609035
Short name T104
Test name
Test status
Simulation time 56258438676 ps
CPU time 730.95 seconds
Started Feb 25 02:33:26 PM PST 24
Finished Feb 25 02:45:37 PM PST 24
Peak memory 216084 kb
Host smart-aa01da06-02cc-4949-809e-b9c3e48d74c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778609035 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3778609035
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_stress_all.3500352584
Short name T70
Test name
Test status
Simulation time 806872649022 ps
CPU time 1818.63 seconds
Started Feb 25 02:31:36 PM PST 24
Finished Feb 25 03:01:55 PM PST 24
Peak memory 232440 kb
Host smart-b540e3a9-365f-4913-bf35-7177c07c033c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500352584 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.3500352584
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_long_msg.264761776
Short name T115
Test name
Test status
Simulation time 26094423206 ps
CPU time 97.7 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:35:47 PM PST 24
Peak memory 199632 kb
Host smart-a6c69b64-0201-4076-bb02-6642c1c94a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264761776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.264761776
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.233319056
Short name T142
Test name
Test status
Simulation time 403643028 ps
CPU time 2.37 seconds
Started Feb 25 01:17:44 PM PST 24
Finished Feb 25 01:17:46 PM PST 24
Peak memory 198948 kb
Host smart-68b82a91-ba2f-4e8d-add6-85a19aa29bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233319056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.233319056
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2480743516
Short name T59
Test name
Test status
Simulation time 2491728278 ps
CPU time 43.01 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:34:52 PM PST 24
Peak memory 226028 kb
Host smart-35c895c7-2b44-4ea3-a01c-c7605fc3472b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2480743516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2480743516
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.861117934
Short name T51
Test name
Test status
Simulation time 624521605 ps
CPU time 2.58 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 198764 kb
Host smart-8eb79570-5520-4e5b-8743-8ee0d5cf0c35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861117934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.861117934
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.2997976493
Short name T717
Test name
Test status
Simulation time 210157263 ps
CPU time 1.29 seconds
Started Feb 25 01:17:45 PM PST 24
Finished Feb 25 01:17:47 PM PST 24
Peak memory 198384 kb
Host smart-762e3de7-3b25-4c5f-a298-23c1213d994f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997976493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.2997976493
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.904578332
Short name T149
Test name
Test status
Simulation time 461251548 ps
CPU time 1.91 seconds
Started Feb 25 01:18:07 PM PST 24
Finished Feb 25 01:18:09 PM PST 24
Peak memory 198712 kb
Host smart-e1a4015b-22d8-4ff0-a0ed-bbfe72435e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904578332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.904578332
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/126.hmac_stress_all_with_rand_reset.3868276638
Short name T55
Test name
Test status
Simulation time 68359869118 ps
CPU time 2227.31 seconds
Started Feb 25 02:35:13 PM PST 24
Finished Feb 25 03:12:21 PM PST 24
Peak memory 240784 kb
Host smart-8dc5905b-1e27-4b87-97de-9db15a3ccc1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868276638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.hmac_stress_all_with_rand_reset.3868276638
Directory /workspace/126.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2151576421
Short name T132
Test name
Test status
Simulation time 5227576328 ps
CPU time 69.64 seconds
Started Feb 25 02:33:21 PM PST 24
Finished Feb 25 02:34:31 PM PST 24
Peak memory 199628 kb
Host smart-317db870-190b-4cca-8108-29457798c06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151576421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2151576421
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1445894412
Short name T119
Test name
Test status
Simulation time 1783723057 ps
CPU time 71.23 seconds
Started Feb 25 02:34:21 PM PST 24
Finished Feb 25 02:35:32 PM PST 24
Peak memory 199512 kb
Host smart-f74214de-e7ec-4e95-b2bf-6d2b8525f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445894412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1445894412
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/89.hmac_stress_all_with_rand_reset.4261141585
Short name T18
Test name
Test status
Simulation time 56768864546 ps
CPU time 589.93 seconds
Started Feb 25 02:35:08 PM PST 24
Finished Feb 25 02:44:59 PM PST 24
Peak memory 247972 kb
Host smart-ddd98c64-c623-4ed9-b2e9-1390e673eafe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4261141585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.hmac_stress_all_with_rand_reset.4261141585
Directory /workspace/89.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.3190099854
Short name T95
Test name
Test status
Simulation time 136869826 ps
CPU time 2.51 seconds
Started Feb 25 01:17:41 PM PST 24
Finished Feb 25 01:17:43 PM PST 24
Peak memory 192680 kb
Host smart-31c382ec-c1a5-4a79-83c3-86c5b656ca57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190099854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.3190099854
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1406130967
Short name T90
Test name
Test status
Simulation time 2493958025 ps
CPU time 6.84 seconds
Started Feb 25 01:17:41 PM PST 24
Finished Feb 25 01:17:48 PM PST 24
Peak memory 192720 kb
Host smart-8afca589-06ab-43d2-9038-b997a2283274
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406130967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1406130967
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1988847361
Short name T656
Test name
Test status
Simulation time 19482451 ps
CPU time 0.73 seconds
Started Feb 25 01:17:47 PM PST 24
Finished Feb 25 01:17:48 PM PST 24
Peak memory 194932 kb
Host smart-ad0e3433-ed4c-4666-bd62-76a16be9c982
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988847361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1988847361
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.884365098
Short name T726
Test name
Test status
Simulation time 109559293545 ps
CPU time 513.94 seconds
Started Feb 25 01:17:43 PM PST 24
Finished Feb 25 01:26:18 PM PST 24
Peak memory 204568 kb
Host smart-ec219703-2b62-4cbd-b98a-0f0be41440c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884365098 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.884365098
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.824321845
Short name T621
Test name
Test status
Simulation time 18066967 ps
CPU time 0.61 seconds
Started Feb 25 01:17:49 PM PST 24
Finished Feb 25 01:17:51 PM PST 24
Peak memory 194472 kb
Host smart-a8dcee8f-b951-43ed-9a9d-914a50f91dc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824321845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.824321845
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.288726220
Short name T706
Test name
Test status
Simulation time 28377021 ps
CPU time 0.58 seconds
Started Feb 25 01:17:44 PM PST 24
Finished Feb 25 01:17:44 PM PST 24
Peak memory 184168 kb
Host smart-dffd61e1-f91d-4a33-a593-397f88761eb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288726220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.288726220
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.3249552492
Short name T624
Test name
Test status
Simulation time 115808423 ps
CPU time 1.4 seconds
Started Feb 25 01:17:47 PM PST 24
Finished Feb 25 01:17:49 PM PST 24
Peak memory 192684 kb
Host smart-486d2280-9fe9-471c-a6bd-0279e5c5e730
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249552492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.3249552492
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1310383692
Short name T673
Test name
Test status
Simulation time 247090174 ps
CPU time 1.66 seconds
Started Feb 25 01:17:42 PM PST 24
Finished Feb 25 01:17:43 PM PST 24
Peak memory 199036 kb
Host smart-2cf97da0-dd00-4527-9738-b45892e1ddfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310383692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1310383692
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.86973651
Short name T87
Test name
Test status
Simulation time 217429485 ps
CPU time 1.94 seconds
Started Feb 25 01:17:47 PM PST 24
Finished Feb 25 01:17:49 PM PST 24
Peak memory 192628 kb
Host smart-8466d11d-6be1-4bf5-b389-3f6eb8670865
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86973651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.86973651
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.3723032164
Short name T720
Test name
Test status
Simulation time 2615962753 ps
CPU time 3.43 seconds
Started Feb 25 01:17:49 PM PST 24
Finished Feb 25 01:17:53 PM PST 24
Peak memory 192672 kb
Host smart-7cdad69f-c73f-492b-aa6a-56bd49b9119e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723032164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.3723032164
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3228378909
Short name T85
Test name
Test status
Simulation time 83632999 ps
CPU time 0.71 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:53 PM PST 24
Peak memory 194684 kb
Host smart-910079f9-0913-44e2-9a39-06f506013b0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228378909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3228378909
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.1146914132
Short name T637
Test name
Test status
Simulation time 538304983 ps
CPU time 3.2 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:06 PM PST 24
Peak memory 199112 kb
Host smart-a24f716a-250f-4ee0-9577-9f43f83d6f06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146914132 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.1146914132
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.4284934979
Short name T597
Test name
Test status
Simulation time 12391325 ps
CPU time 0.62 seconds
Started Feb 25 01:17:47 PM PST 24
Finished Feb 25 01:17:48 PM PST 24
Peak memory 194068 kb
Host smart-6b9e73a9-730f-4404-a752-b32fcbd66147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284934979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.4284934979
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2127165468
Short name T669
Test name
Test status
Simulation time 35709079 ps
CPU time 0.58 seconds
Started Feb 25 01:17:48 PM PST 24
Finished Feb 25 01:17:49 PM PST 24
Peak memory 184104 kb
Host smart-888f413f-eff3-429e-880f-83e972728271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127165468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2127165468
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3647255690
Short name T662
Test name
Test status
Simulation time 159018104 ps
CPU time 1.07 seconds
Started Feb 25 01:17:42 PM PST 24
Finished Feb 25 01:17:43 PM PST 24
Peak memory 197060 kb
Host smart-796e8b9b-93aa-491c-b52b-989cc1cc40dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647255690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3647255690
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.1505587825
Short name T684
Test name
Test status
Simulation time 101390416 ps
CPU time 1.58 seconds
Started Feb 25 01:17:57 PM PST 24
Finished Feb 25 01:17:59 PM PST 24
Peak memory 199068 kb
Host smart-274cb077-3088-4999-bcd5-1747ab5aae40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505587825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.1505587825
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.29066283
Short name T638
Test name
Test status
Simulation time 62397369 ps
CPU time 1.68 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:07 PM PST 24
Peak memory 199096 kb
Host smart-41cd4341-a2b8-4f47-8a30-3e7aa243f9cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29066283 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.29066283
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.984859189
Short name T721
Test name
Test status
Simulation time 16776146 ps
CPU time 0.62 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 194548 kb
Host smart-585c2c73-10b1-4459-9c29-3b4ab60015eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984859189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.984859189
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.4022034545
Short name T654
Test name
Test status
Simulation time 36695530 ps
CPU time 0.57 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 184300 kb
Host smart-0512b842-00cb-4b9d-9a8b-93fac20ebd5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022034545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.4022034545
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1215312433
Short name T629
Test name
Test status
Simulation time 532375323 ps
CPU time 1.38 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 192632 kb
Host smart-afb4da25-6e3d-49b6-aef3-56dd417cac5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215312433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1215312433
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2746736370
Short name T611
Test name
Test status
Simulation time 170931216 ps
CPU time 2.36 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 199076 kb
Host smart-b889bd0a-0e5f-4ec3-8281-352862009e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746736370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2746736370
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.2518364781
Short name T642
Test name
Test status
Simulation time 22360953 ps
CPU time 1.21 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:06 PM PST 24
Peak memory 198892 kb
Host smart-ca043e01-920f-4705-a38e-8aaecb4fad02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518364781 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.2518364781
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.138861666
Short name T680
Test name
Test status
Simulation time 24618055 ps
CPU time 0.7 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 194844 kb
Host smart-74f573d5-804e-4da0-89a6-d831db1ec815
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138861666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.138861666
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.482185267
Short name T697
Test name
Test status
Simulation time 41437306 ps
CPU time 0.59 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:02 PM PST 24
Peak memory 184168 kb
Host smart-90e61efa-ff38-4d38-8821-1621b986d631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482185267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.482185267
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1289949973
Short name T655
Test name
Test status
Simulation time 17146899 ps
CPU time 0.8 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 192476 kb
Host smart-c209a416-24de-4cbf-bc89-abc699e9cce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289949973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1289949973
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2447810919
Short name T639
Test name
Test status
Simulation time 143492567 ps
CPU time 3.09 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 199004 kb
Host smart-4be3a554-0233-4670-9247-ca0d0c61fd81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447810919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2447810919
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3914275826
Short name T609
Test name
Test status
Simulation time 43064748490 ps
CPU time 181.99 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:21:04 PM PST 24
Peak memory 199144 kb
Host smart-345271a0-4063-4e17-a1dd-4a7a86c68ba9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914275826 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3914275826
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2800907021
Short name T675
Test name
Test status
Simulation time 10983740 ps
CPU time 0.58 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 184176 kb
Host smart-8e4b26db-ef9d-400e-a6f0-15f85b66d98b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800907021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2800907021
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.1351605322
Short name T606
Test name
Test status
Simulation time 84565086 ps
CPU time 1.13 seconds
Started Feb 25 01:18:00 PM PST 24
Finished Feb 25 01:18:02 PM PST 24
Peak memory 197396 kb
Host smart-28d5c75b-51a9-424e-b529-8d3bbe9e427f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351605322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.1351605322
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.1480136673
Short name T716
Test name
Test status
Simulation time 134388597 ps
CPU time 2.85 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:06 PM PST 24
Peak memory 199128 kb
Host smart-0f2e72f7-3bc4-49c0-9e2d-9d502fb010f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480136673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.1480136673
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3810756217
Short name T144
Test name
Test status
Simulation time 76486604 ps
CPU time 1.69 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 198788 kb
Host smart-9665f13d-7bcc-4b57-950c-5f9a00aff248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810756217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3810756217
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.384014121
Short name T618
Test name
Test status
Simulation time 53298081 ps
CPU time 3.38 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 199008 kb
Host smart-4737a962-0471-497d-87dc-cf9e10931020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384014121 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.384014121
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2782041681
Short name T664
Test name
Test status
Simulation time 101789327 ps
CPU time 0.78 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 195240 kb
Host smart-cf2536bf-ae26-4ab6-9f98-b9688a1e6be1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782041681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2782041681
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.2981488767
Short name T635
Test name
Test status
Simulation time 18387257 ps
CPU time 0.55 seconds
Started Feb 25 01:18:04 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 184164 kb
Host smart-c7e8ff3c-7fd6-47ae-99e5-8c853c13e3a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981488767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.2981488767
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1867418312
Short name T619
Test name
Test status
Simulation time 82493746 ps
CPU time 1.05 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 197016 kb
Host smart-0d0c3286-d896-4976-bc24-d46864486e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867418312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1867418312
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2211486144
Short name T672
Test name
Test status
Simulation time 233061382 ps
CPU time 1.49 seconds
Started Feb 25 01:18:04 PM PST 24
Finished Feb 25 01:18:06 PM PST 24
Peak memory 198964 kb
Host smart-d542b177-41e6-47e3-bbef-13730df4f719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211486144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2211486144
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2550938209
Short name T141
Test name
Test status
Simulation time 234032307 ps
CPU time 2.39 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 198840 kb
Host smart-7d941769-108a-4b1b-bc56-c34036138447
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550938209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2550938209
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.453967445
Short name T607
Test name
Test status
Simulation time 62009133172 ps
CPU time 509.42 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:26:45 PM PST 24
Peak memory 202316 kb
Host smart-f240d445-f770-46bd-abd3-8b27f943d5d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453967445 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.453967445
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.765434558
Short name T728
Test name
Test status
Simulation time 57229813 ps
CPU time 0.6 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:10 PM PST 24
Peak memory 194320 kb
Host smart-74878079-722f-4026-b323-6eb286a5d719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765434558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.765434558
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.154462422
Short name T696
Test name
Test status
Simulation time 43380230 ps
CPU time 0.58 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 184144 kb
Host smart-47c27d56-68fa-4406-a0d0-351abc1aaf1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154462422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.154462422
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.840343948
Short name T714
Test name
Test status
Simulation time 325514883 ps
CPU time 1.36 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 192660 kb
Host smart-b4c537e9-8588-41eb-9103-543933935c6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840343948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_csr
_outstanding.840343948
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.2197162905
Short name T663
Test name
Test status
Simulation time 25601937 ps
CPU time 1.32 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 198336 kb
Host smart-2287caae-11dc-4c8b-a442-68a85cb93910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197162905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.2197162905
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1877195550
Short name T636
Test name
Test status
Simulation time 50942848 ps
CPU time 1.2 seconds
Started Feb 25 01:18:16 PM PST 24
Finished Feb 25 01:18:17 PM PST 24
Peak memory 198464 kb
Host smart-a32c671b-86c7-47c7-86ee-8bd4f3fdceee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877195550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1877195550
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2172254622
Short name T694
Test name
Test status
Simulation time 630635007 ps
CPU time 3.66 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 199028 kb
Host smart-84207db3-4d68-408d-8886-a1eb1dbdf334
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172254622 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2172254622
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2080297288
Short name T686
Test name
Test status
Simulation time 22279907 ps
CPU time 0.73 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 194736 kb
Host smart-6b957f29-f7fd-479f-b83c-39315de28b9b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080297288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2080297288
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4264851569
Short name T643
Test name
Test status
Simulation time 55151036 ps
CPU time 0.63 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:12 PM PST 24
Peak memory 184168 kb
Host smart-3a9410e0-7241-45fd-a2c7-0325a731d3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264851569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4264851569
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3591894443
Short name T683
Test name
Test status
Simulation time 233884304 ps
CPU time 1.26 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 192680 kb
Host smart-b7d53a0f-02a7-4af5-833a-fb97e3a81334
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591894443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3591894443
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.115058948
Short name T666
Test name
Test status
Simulation time 122445357 ps
CPU time 2.93 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:17 PM PST 24
Peak memory 199080 kb
Host smart-bfce4e02-cdc2-4c12-a77d-bebb1fe8dc83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115058948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.115058948
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2207226548
Short name T725
Test name
Test status
Simulation time 922988827 ps
CPU time 1.72 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 198848 kb
Host smart-2f883ea9-bcb5-410d-91e5-716fb9bf3f39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207226548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2207226548
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3054045576
Short name T701
Test name
Test status
Simulation time 89709641 ps
CPU time 1.8 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 199084 kb
Host smart-2fbbd38f-91cc-43db-94a1-87216d389daa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054045576 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3054045576
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.2608740220
Short name T94
Test name
Test status
Simulation time 15037934 ps
CPU time 0.74 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 195200 kb
Host smart-352bac9f-ef14-4a92-b02a-1577cc96ac6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608740220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.2608740220
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.170450334
Short name T703
Test name
Test status
Simulation time 14468828 ps
CPU time 0.56 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 184108 kb
Host smart-dcd9227a-a5c0-446d-b81d-1803c2a921b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170450334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.170450334
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.624804369
Short name T604
Test name
Test status
Simulation time 17881948 ps
CPU time 0.85 seconds
Started Feb 25 01:18:16 PM PST 24
Finished Feb 25 01:18:17 PM PST 24
Peak memory 192396 kb
Host smart-dda4a2ea-eb5c-40f0-ae27-fa50aaba6ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624804369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.624804369
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.523080581
Short name T653
Test name
Test status
Simulation time 117223990 ps
CPU time 3.33 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 199064 kb
Host smart-a8791bad-3702-469a-a685-17aa454320e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523080581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.523080581
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2226596311
Short name T150
Test name
Test status
Simulation time 663662627 ps
CPU time 2.22 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 198812 kb
Host smart-f50e997a-792a-4ed6-a226-eb0332cef1f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226596311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2226596311
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1654983345
Short name T641
Test name
Test status
Simulation time 86449832 ps
CPU time 2.74 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 199024 kb
Host smart-07a09f89-ec63-49d2-adf6-66c929f297de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654983345 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1654983345
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.596924567
Short name T93
Test name
Test status
Simulation time 99152580 ps
CPU time 0.72 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 194656 kb
Host smart-f992578a-e138-40cb-b75f-66263dbae9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596924567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.596924567
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.302883164
Short name T645
Test name
Test status
Simulation time 56024409 ps
CPU time 0.58 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:11 PM PST 24
Peak memory 184180 kb
Host smart-f93488be-89ee-4e93-ab3e-a9e16961b362
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302883164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.302883164
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2606824925
Short name T711
Test name
Test status
Simulation time 513278733 ps
CPU time 1.35 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 192696 kb
Host smart-8fed117d-7736-475a-9c72-e019c645f1b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606824925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2606824925
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2895790746
Short name T676
Test name
Test status
Simulation time 427025540 ps
CPU time 2.23 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 198964 kb
Host smart-14b68319-eddb-4b23-a5ad-71be01d761a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895790746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2895790746
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.840103020
Short name T52
Test name
Test status
Simulation time 65705844 ps
CPU time 1.25 seconds
Started Feb 25 01:18:08 PM PST 24
Finished Feb 25 01:18:10 PM PST 24
Peak memory 198612 kb
Host smart-92d0f5fd-617c-4ca6-ae6f-f584b0c5a082
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840103020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.840103020
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2589945639
Short name T719
Test name
Test status
Simulation time 179674934 ps
CPU time 1.27 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 198904 kb
Host smart-024a89c0-fe63-453c-9ef1-05f3b91da1ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589945639 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2589945639
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1547507739
Short name T83
Test name
Test status
Simulation time 66027575 ps
CPU time 0.69 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:11 PM PST 24
Peak memory 194684 kb
Host smart-96166c81-bd8e-4ef5-8f43-971853d51fc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547507739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1547507739
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2714143014
Short name T667
Test name
Test status
Simulation time 17007178 ps
CPU time 0.61 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:11 PM PST 24
Peak memory 184120 kb
Host smart-2265189b-66d3-4222-a729-040a8f6450fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714143014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2714143014
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.474949979
Short name T623
Test name
Test status
Simulation time 372880511 ps
CPU time 1.03 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 192588 kb
Host smart-d109cbbe-bc26-4d80-a708-c63b55eb5443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474949979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.474949979
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.692376592
Short name T722
Test name
Test status
Simulation time 402546437 ps
CPU time 2.08 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 199028 kb
Host smart-f0b688e0-2067-40d1-9745-af61243f7a76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692376592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.692376592
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.2642286032
Short name T146
Test name
Test status
Simulation time 57690495 ps
CPU time 1.21 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 198456 kb
Host smart-63c43a7a-64a5-4360-87ff-2861b20c443c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642286032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.2642286032
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1240643927
Short name T614
Test name
Test status
Simulation time 52525261960 ps
CPU time 510.91 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:26:43 PM PST 24
Peak memory 210976 kb
Host smart-50149522-5593-433b-8d13-20f88f72d534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240643927 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1240643927
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.667287496
Short name T687
Test name
Test status
Simulation time 49781640 ps
CPU time 0.63 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 194776 kb
Host smart-1df30513-03a4-4304-a1dd-0cd4cf1c56d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667287496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.667287496
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2525625157
Short name T685
Test name
Test status
Simulation time 53124669 ps
CPU time 0.61 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 184116 kb
Host smart-695bd5b5-1fc6-401b-9266-ef52267c0431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525625157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2525625157
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4200843630
Short name T715
Test name
Test status
Simulation time 271108949 ps
CPU time 1.44 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 192708 kb
Host smart-4acb6747-a3c6-4728-b176-1f9369549565
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200843630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4200843630
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3691804117
Short name T602
Test name
Test status
Simulation time 60608299 ps
CPU time 1.84 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 199004 kb
Host smart-261b2de2-a114-4308-afda-5224f00fbf36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691804117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3691804117
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1997936637
Short name T148
Test name
Test status
Simulation time 105786680 ps
CPU time 1.24 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:11 PM PST 24
Peak memory 198504 kb
Host smart-756a2523-a457-40ca-b9a9-e468fdf4d612
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997936637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1997936637
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.554157953
Short name T84
Test name
Test status
Simulation time 261696300 ps
CPU time 1.25 seconds
Started Feb 25 01:17:56 PM PST 24
Finished Feb 25 01:17:57 PM PST 24
Peak memory 192564 kb
Host smart-5d9728b3-988e-4732-b698-07010b3c9d78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554157953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.554157953
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4031810133
Short name T89
Test name
Test status
Simulation time 1311386994 ps
CPU time 6.64 seconds
Started Feb 25 01:17:52 PM PST 24
Finished Feb 25 01:17:59 PM PST 24
Peak memory 192668 kb
Host smart-b445d14b-d6fc-4a4f-bd8e-e034e5ad51a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031810133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4031810133
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.796999245
Short name T82
Test name
Test status
Simulation time 82919231 ps
CPU time 0.64 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 194480 kb
Host smart-5ed465e6-f136-409a-92b2-0d9e9a707e22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796999245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.796999245
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2331845487
Short name T613
Test name
Test status
Simulation time 150854334 ps
CPU time 3.34 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:59 PM PST 24
Peak memory 199068 kb
Host smart-e6839801-a459-440c-b526-2b7e019afbbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331845487 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2331845487
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1723943263
Short name T612
Test name
Test status
Simulation time 38267933 ps
CPU time 0.64 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 194268 kb
Host smart-d316d6cd-5fd8-4087-8b6d-8cd7ec36b8fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723943263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1723943263
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.4247102251
Short name T647
Test name
Test status
Simulation time 48298934 ps
CPU time 0.58 seconds
Started Feb 25 01:17:57 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 184156 kb
Host smart-dd2fa5ea-d451-4d9b-b0b6-20f93fd65a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247102251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.4247102251
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.119713121
Short name T617
Test name
Test status
Simulation time 58434003 ps
CPU time 0.85 seconds
Started Feb 25 01:17:57 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 192448 kb
Host smart-152dc10e-7a2d-4804-9f84-d8e38b6c1358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119713121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr_
outstanding.119713121
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2395456205
Short name T633
Test name
Test status
Simulation time 51103619 ps
CPU time 2.63 seconds
Started Feb 25 01:17:56 PM PST 24
Finished Feb 25 01:17:59 PM PST 24
Peak memory 199120 kb
Host smart-aa563ced-7036-4171-b935-53227d394f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395456205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2395456205
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.152819415
Short name T145
Test name
Test status
Simulation time 119474462 ps
CPU time 1.22 seconds
Started Feb 25 01:17:57 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 198320 kb
Host smart-0cee1517-a1c3-406f-b90b-da246763c38e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152819415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.152819415
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2062318512
Short name T678
Test name
Test status
Simulation time 12427070 ps
CPU time 0.57 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 184116 kb
Host smart-5f05710b-9191-480a-8d29-3091b0245311
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062318512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2062318512
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.1786207816
Short name T622
Test name
Test status
Simulation time 11374975 ps
CPU time 0.58 seconds
Started Feb 25 01:18:13 PM PST 24
Finished Feb 25 01:18:14 PM PST 24
Peak memory 184184 kb
Host smart-b82ca600-9bc4-41aa-9b43-dd2c4bcaa38c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786207816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.1786207816
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3401712121
Short name T631
Test name
Test status
Simulation time 63311768 ps
CPU time 0.58 seconds
Started Feb 25 01:18:12 PM PST 24
Finished Feb 25 01:18:13 PM PST 24
Peak memory 184168 kb
Host smart-3c220340-d94a-4fde-aa7e-33abcc2c88d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401712121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3401712121
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2636852773
Short name T705
Test name
Test status
Simulation time 15046116 ps
CPU time 0.59 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 184116 kb
Host smart-9b0be6fe-e977-41ae-a34e-828595d27b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636852773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2636852773
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2809693501
Short name T727
Test name
Test status
Simulation time 12103763 ps
CPU time 0.55 seconds
Started Feb 25 01:18:09 PM PST 24
Finished Feb 25 01:18:10 PM PST 24
Peak memory 184160 kb
Host smart-7a429acb-a6c5-4987-a0f3-418caf694b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809693501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2809693501
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2025363913
Short name T596
Test name
Test status
Simulation time 27384001 ps
CPU time 0.6 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 183672 kb
Host smart-c32e0161-508d-4770-aaa1-10031c4f745f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025363913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2025363913
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1994134650
Short name T657
Test name
Test status
Simulation time 15616301 ps
CPU time 0.59 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 184180 kb
Host smart-3798b902-dc95-4ab1-9cd5-b38b52a433b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994134650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1994134650
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.2064151730
Short name T615
Test name
Test status
Simulation time 35829966 ps
CPU time 0.58 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:12 PM PST 24
Peak memory 184188 kb
Host smart-ce7fec38-9556-491a-95c7-3003c31cbc42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064151730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.2064151730
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.338134554
Short name T682
Test name
Test status
Simulation time 15972056 ps
CPU time 0.58 seconds
Started Feb 25 01:18:14 PM PST 24
Finished Feb 25 01:18:15 PM PST 24
Peak memory 184008 kb
Host smart-31df0ac3-60ec-4186-8c47-2decb9404154
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338134554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.338134554
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1848848628
Short name T658
Test name
Test status
Simulation time 14164590 ps
CPU time 0.62 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:21 PM PST 24
Peak memory 184104 kb
Host smart-a4716618-cd06-4644-a787-82b203cf0068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848848628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1848848628
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.273457951
Short name T79
Test name
Test status
Simulation time 36802458 ps
CPU time 1.78 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:57 PM PST 24
Peak memory 192676 kb
Host smart-21baf5f8-9453-444b-8a9a-10c8195be732
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273457951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.273457951
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1102373741
Short name T91
Test name
Test status
Simulation time 327065743 ps
CPU time 3.73 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:57 PM PST 24
Peak memory 192612 kb
Host smart-e66d8c66-a7ee-4a00-b279-9e8e466f59bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102373741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1102373741
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.341705510
Short name T712
Test name
Test status
Simulation time 58373934 ps
CPU time 0.71 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:56 PM PST 24
Peak memory 194692 kb
Host smart-8d82bf6b-a568-4e7d-b262-e18f10ee8993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341705510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.341705510
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.2904588550
Short name T718
Test name
Test status
Simulation time 22753217 ps
CPU time 1.21 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 198888 kb
Host smart-a36e17e4-a840-46ba-b09b-b91cb8bb3960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904588550 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.2904588550
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.291661806
Short name T646
Test name
Test status
Simulation time 37655269 ps
CPU time 0.61 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 194636 kb
Host smart-5378e084-693a-474e-a39d-24ca4f8129c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291661806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.291661806
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.129913511
Short name T634
Test name
Test status
Simulation time 24373326 ps
CPU time 0.63 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 184172 kb
Host smart-e9a35cfd-cc1e-45d2-9743-46db68a100db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129913511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.129913511
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3812553593
Short name T659
Test name
Test status
Simulation time 78109849 ps
CPU time 0.96 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:56 PM PST 24
Peak memory 192644 kb
Host smart-8769dd0b-6bc8-4bf4-9046-dcd76665607f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812553593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3812553593
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4275823657
Short name T691
Test name
Test status
Simulation time 82485646 ps
CPU time 1.23 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 199072 kb
Host smart-a0de2d97-9cb2-4a94-b9dc-ba505292c048
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275823657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4275823657
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2702931029
Short name T610
Test name
Test status
Simulation time 12101316 ps
CPU time 0.61 seconds
Started Feb 25 01:18:11 PM PST 24
Finished Feb 25 01:18:12 PM PST 24
Peak memory 184160 kb
Host smart-f6d2b74a-1986-4530-8d28-28d9be758164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702931029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2702931029
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.178219726
Short name T625
Test name
Test status
Simulation time 52678778 ps
CPU time 0.62 seconds
Started Feb 25 01:18:15 PM PST 24
Finished Feb 25 01:18:16 PM PST 24
Peak memory 184100 kb
Host smart-704488ca-4e67-41a5-b202-1c8f4984416d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178219726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.178219726
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.329060858
Short name T595
Test name
Test status
Simulation time 41201960 ps
CPU time 0.56 seconds
Started Feb 25 01:18:08 PM PST 24
Finished Feb 25 01:18:09 PM PST 24
Peak memory 184172 kb
Host smart-5640dd20-05d3-41a5-ae99-933f05e60f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329060858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.329060858
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2298710049
Short name T689
Test name
Test status
Simulation time 46067048 ps
CPU time 0.58 seconds
Started Feb 25 01:18:10 PM PST 24
Finished Feb 25 01:18:11 PM PST 24
Peak memory 184100 kb
Host smart-59d4e72a-84b3-4d7b-b65f-b32c2cb3ec2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298710049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2298710049
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1407255944
Short name T692
Test name
Test status
Simulation time 24746764 ps
CPU time 0.58 seconds
Started Feb 25 01:18:09 PM PST 24
Finished Feb 25 01:18:10 PM PST 24
Peak memory 184176 kb
Host smart-15221677-7caa-4bde-8ad3-b8b28d81dcdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407255944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1407255944
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1784583999
Short name T644
Test name
Test status
Simulation time 10655345 ps
CPU time 0.57 seconds
Started Feb 25 01:18:17 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 184100 kb
Host smart-95c97177-a75b-4236-9636-9ba0c09d890a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784583999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1784583999
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1886307849
Short name T724
Test name
Test status
Simulation time 104151274 ps
CPU time 0.58 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:21 PM PST 24
Peak memory 184104 kb
Host smart-0506018e-049a-4288-80eb-2fbabb8c74cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886307849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1886307849
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2722509049
Short name T640
Test name
Test status
Simulation time 15303721 ps
CPU time 0.59 seconds
Started Feb 25 01:18:21 PM PST 24
Finished Feb 25 01:18:22 PM PST 24
Peak memory 184172 kb
Host smart-456e145b-ae83-463e-a928-c820787c2a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722509049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2722509049
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3175894974
Short name T627
Test name
Test status
Simulation time 37235575 ps
CPU time 0.58 seconds
Started Feb 25 01:18:16 PM PST 24
Finished Feb 25 01:18:17 PM PST 24
Peak memory 184172 kb
Host smart-c26f7ad2-7590-4f17-8cc0-c1e0f16e5bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175894974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3175894974
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4169532380
Short name T599
Test name
Test status
Simulation time 29253348 ps
CPU time 0.63 seconds
Started Feb 25 01:18:16 PM PST 24
Finished Feb 25 01:18:17 PM PST 24
Peak memory 184048 kb
Host smart-22024047-19c0-4bc3-b5fc-a27942940c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169532380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4169532380
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1609202602
Short name T651
Test name
Test status
Simulation time 357347096 ps
CPU time 1.92 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:17:56 PM PST 24
Peak memory 196256 kb
Host smart-f7b7aea0-4c22-4f08-9100-9a20a9a00c28
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609202602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1609202602
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.4237616755
Short name T80
Test name
Test status
Simulation time 1664056085 ps
CPU time 6.15 seconds
Started Feb 25 01:17:56 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 192608 kb
Host smart-7c20dacf-cc0b-472b-9af2-ca10ad50f138
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237616755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.4237616755
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2992816429
Short name T699
Test name
Test status
Simulation time 14826644 ps
CPU time 0.68 seconds
Started Feb 25 01:18:00 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 194612 kb
Host smart-27ff532f-9fcc-403d-8cf7-c3a7a9802f00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992816429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2992816429
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3846236085
Short name T601
Test name
Test status
Simulation time 41593757232 ps
CPU time 157.93 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:20:32 PM PST 24
Peak memory 199264 kb
Host smart-bcfb97ec-0490-422e-9379-88f8605621a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846236085 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3846236085
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.3754146680
Short name T88
Test name
Test status
Simulation time 102008630 ps
CPU time 0.67 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 195036 kb
Host smart-b73252ab-9269-437a-b6f3-39f45922e317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754146680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.3754146680
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.428666974
Short name T688
Test name
Test status
Simulation time 44282545 ps
CPU time 0.59 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 184112 kb
Host smart-70fa43b9-78cf-40ba-8536-49d46e5673e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428666974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.428666974
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.837760423
Short name T605
Test name
Test status
Simulation time 17615576 ps
CPU time 0.85 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:56 PM PST 24
Peak memory 196104 kb
Host smart-fe06f96a-9891-4823-ac4a-0080f54066fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837760423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr_
outstanding.837760423
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3280565936
Short name T665
Test name
Test status
Simulation time 86253561 ps
CPU time 2.32 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 199116 kb
Host smart-15811901-2abd-4df6-bfb4-2badd7ad553b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280565936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3280565936
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1421749368
Short name T695
Test name
Test status
Simulation time 111367495 ps
CPU time 1.76 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:57 PM PST 24
Peak memory 198676 kb
Host smart-5153d3ff-c293-4327-99eb-b521ecdba226
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421749368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1421749368
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2357400986
Short name T616
Test name
Test status
Simulation time 93686695 ps
CPU time 0.56 seconds
Started Feb 25 01:18:18 PM PST 24
Finished Feb 25 01:18:19 PM PST 24
Peak memory 184112 kb
Host smart-e911dc11-b425-4b75-99cc-50d9f200a3d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357400986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2357400986
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2898380515
Short name T710
Test name
Test status
Simulation time 42731145 ps
CPU time 0.58 seconds
Started Feb 25 01:18:21 PM PST 24
Finished Feb 25 01:18:22 PM PST 24
Peak memory 184164 kb
Host smart-c9c18e37-6d73-45e0-8054-c9ff0867eec6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898380515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2898380515
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.828927382
Short name T679
Test name
Test status
Simulation time 11974298 ps
CPU time 0.59 seconds
Started Feb 25 01:18:20 PM PST 24
Finished Feb 25 01:18:21 PM PST 24
Peak memory 184196 kb
Host smart-406a6576-740e-4544-b55a-ed0f87558b1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828927382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.828927382
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2851329111
Short name T652
Test name
Test status
Simulation time 27929660 ps
CPU time 0.6 seconds
Started Feb 25 01:18:17 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 184176 kb
Host smart-4680f5d6-e698-465a-942f-b68ed35ec609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851329111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2851329111
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3282433156
Short name T677
Test name
Test status
Simulation time 24027045 ps
CPU time 0.6 seconds
Started Feb 25 01:18:19 PM PST 24
Finished Feb 25 01:18:20 PM PST 24
Peak memory 184160 kb
Host smart-32e46ff7-0cce-407f-af1e-8eb89bcf9f63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282433156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3282433156
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2963955969
Short name T681
Test name
Test status
Simulation time 16354260 ps
CPU time 0.58 seconds
Started Feb 25 01:18:18 PM PST 24
Finished Feb 25 01:18:19 PM PST 24
Peak memory 184176 kb
Host smart-dd72f418-caf5-4127-9cee-07978b4f6daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963955969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2963955969
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.798800314
Short name T700
Test name
Test status
Simulation time 59256964 ps
CPU time 0.59 seconds
Started Feb 25 01:18:19 PM PST 24
Finished Feb 25 01:18:20 PM PST 24
Peak memory 184188 kb
Host smart-a0984baa-bdef-4972-8e28-bd3a648eb2e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798800314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.798800314
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1650819290
Short name T626
Test name
Test status
Simulation time 34033420 ps
CPU time 0.55 seconds
Started Feb 25 01:18:24 PM PST 24
Finished Feb 25 01:18:25 PM PST 24
Peak memory 184104 kb
Host smart-104d4b2f-b4f6-423f-8aa6-63ba8b9d8458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650819290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1650819290
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1852310190
Short name T671
Test name
Test status
Simulation time 18972155 ps
CPU time 0.58 seconds
Started Feb 25 01:18:17 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 184188 kb
Host smart-59a23711-eb16-403e-a732-eaf9a71ae48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852310190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1852310190
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.1466326728
Short name T608
Test name
Test status
Simulation time 41852925 ps
CPU time 0.6 seconds
Started Feb 25 01:18:17 PM PST 24
Finished Feb 25 01:18:18 PM PST 24
Peak memory 184168 kb
Host smart-de28c7d7-76ef-4b3c-86bc-76fa6e98b3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466326728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.1466326728
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1054410503
Short name T723
Test name
Test status
Simulation time 45673370893 ps
CPU time 439.8 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:25:14 PM PST 24
Peak memory 199904 kb
Host smart-14cc9e7c-d735-4a89-87ff-dd96e2edf436
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054410503 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1054410503
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2377796985
Short name T92
Test name
Test status
Simulation time 13027841 ps
CPU time 0.69 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 194908 kb
Host smart-13e5d08d-ab50-46bd-b729-9858a62ce59b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377796985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2377796985
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3151256499
Short name T620
Test name
Test status
Simulation time 18853101 ps
CPU time 0.63 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 184108 kb
Host smart-7ff5f2a3-b422-4955-a787-21baa3bc28e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151256499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3151256499
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1142642012
Short name T670
Test name
Test status
Simulation time 163510724 ps
CPU time 1.32 seconds
Started Feb 25 01:17:53 PM PST 24
Finished Feb 25 01:17:54 PM PST 24
Peak memory 192644 kb
Host smart-ccc55332-db52-4be6-98e3-3a96af98de13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142642012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1142642012
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1937092031
Short name T632
Test name
Test status
Simulation time 74192716 ps
CPU time 1.89 seconds
Started Feb 25 01:17:57 PM PST 24
Finished Feb 25 01:17:59 PM PST 24
Peak memory 198964 kb
Host smart-b4a5f078-dc5a-47ee-9cc0-6885c14b97a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937092031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1937092031
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1749573713
Short name T648
Test name
Test status
Simulation time 269680161 ps
CPU time 1.37 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 198432 kb
Host smart-ba31f0d6-b705-4b16-ac48-08b06ae2a459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749573713 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1749573713
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3990142349
Short name T650
Test name
Test status
Simulation time 46106124 ps
CPU time 1.63 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 199064 kb
Host smart-91694148-97d4-4a76-ab43-63e44ddf6496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990142349 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3990142349
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.117406816
Short name T674
Test name
Test status
Simulation time 44529125 ps
CPU time 0.62 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:56 PM PST 24
Peak memory 194152 kb
Host smart-a54ff4f0-3fda-48b0-8353-002de868b66e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117406816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.117406816
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2420989628
Short name T661
Test name
Test status
Simulation time 14455531 ps
CPU time 0.63 seconds
Started Feb 25 01:17:54 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 184080 kb
Host smart-46ac42e5-64f4-406a-9e33-2da3b39c57f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420989628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2420989628
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1266544342
Short name T707
Test name
Test status
Simulation time 160122407 ps
CPU time 1.33 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:57 PM PST 24
Peak memory 192592 kb
Host smart-06826e3e-11c5-4da3-ab25-99e142d7243a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266544342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1266544342
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3205519445
Short name T713
Test name
Test status
Simulation time 1597726227 ps
CPU time 3.14 seconds
Started Feb 25 01:17:52 PM PST 24
Finished Feb 25 01:17:55 PM PST 24
Peak memory 199104 kb
Host smart-cf9d9548-94e5-4070-a60a-14d298dea1e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205519445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3205519445
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2065740284
Short name T147
Test name
Test status
Simulation time 1595063106 ps
CPU time 2.4 seconds
Started Feb 25 01:17:55 PM PST 24
Finished Feb 25 01:17:58 PM PST 24
Peak memory 198752 kb
Host smart-389ea2c9-adb8-4d9f-82bd-49d1e103b727
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065740284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2065740284
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.4077167945
Short name T698
Test name
Test status
Simulation time 240930112 ps
CPU time 2.15 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 199064 kb
Host smart-2095b87c-8d04-43f5-a9f2-3dfbfb090025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077167945 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.4077167945
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.1507635507
Short name T86
Test name
Test status
Simulation time 46290297 ps
CPU time 0.67 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 195060 kb
Host smart-1f064f49-2ac2-4608-b6eb-b5a13568e8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507635507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.1507635507
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1934889525
Short name T649
Test name
Test status
Simulation time 29645519 ps
CPU time 0.58 seconds
Started Feb 25 01:18:00 PM PST 24
Finished Feb 25 01:18:00 PM PST 24
Peak memory 184180 kb
Host smart-c7b43647-da1e-4480-aa5a-db70a90403b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934889525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1934889525
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.4285237825
Short name T660
Test name
Test status
Simulation time 17733621 ps
CPU time 0.82 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:02 PM PST 24
Peak memory 192468 kb
Host smart-ed319acb-5f10-4ef2-9e89-24f9c5cc564e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285237825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.4285237825
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.2994964768
Short name T630
Test name
Test status
Simulation time 209352353 ps
CPU time 3.72 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:07 PM PST 24
Peak memory 199108 kb
Host smart-16544b34-da2d-4e0e-9f61-82ed4f977734
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994964768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.2994964768
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1152278616
Short name T693
Test name
Test status
Simulation time 232196683 ps
CPU time 1.22 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 198620 kb
Host smart-cb477bc1-683c-4c47-a18a-29a04640be98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152278616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1152278616
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.745760029
Short name T702
Test name
Test status
Simulation time 511746627 ps
CPU time 2.02 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:08 PM PST 24
Peak memory 198964 kb
Host smart-fba360e7-a999-4d66-954c-b294904c6996
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745760029 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.745760029
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.909177639
Short name T96
Test name
Test status
Simulation time 41886605 ps
CPU time 0.71 seconds
Started Feb 25 01:18:07 PM PST 24
Finished Feb 25 01:18:07 PM PST 24
Peak memory 195116 kb
Host smart-e6bb54c0-c00f-4aad-8ab7-bacf35fad353
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909177639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.909177639
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.1516434363
Short name T709
Test name
Test status
Simulation time 26993587 ps
CPU time 0.62 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 184108 kb
Host smart-3e4bb298-9d04-4df9-aa6c-a5eaaefc384e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516434363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.1516434363
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2173947061
Short name T628
Test name
Test status
Simulation time 115371376 ps
CPU time 1.31 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:05 PM PST 24
Peak memory 192676 kb
Host smart-e737f2d2-12a1-4d18-a349-d35fdfedceb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173947061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2173947061
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.798745794
Short name T690
Test name
Test status
Simulation time 228626600 ps
CPU time 3.01 seconds
Started Feb 25 01:18:04 PM PST 24
Finished Feb 25 01:18:07 PM PST 24
Peak memory 199068 kb
Host smart-99d392b8-d811-4434-92d4-165472461e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798745794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.798745794
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2961394943
Short name T143
Test name
Test status
Simulation time 115663892 ps
CPU time 2.3 seconds
Started Feb 25 01:18:02 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 198696 kb
Host smart-dd6509d0-ab02-4982-8498-dfa145dcd0a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961394943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2961394943
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.2645641711
Short name T603
Test name
Test status
Simulation time 261802984 ps
CPU time 3.58 seconds
Started Feb 25 01:18:07 PM PST 24
Finished Feb 25 01:18:10 PM PST 24
Peak memory 199064 kb
Host smart-efb549fc-730d-4adc-8438-b39175b19391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645641711 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.2645641711
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.407197279
Short name T708
Test name
Test status
Simulation time 19026461 ps
CPU time 0.64 seconds
Started Feb 25 01:18:03 PM PST 24
Finished Feb 25 01:18:04 PM PST 24
Peak memory 194388 kb
Host smart-02a40edd-8fec-48c4-8e2b-5587f5ca65ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407197279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.407197279
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2720697956
Short name T598
Test name
Test status
Simulation time 54320837 ps
CPU time 0.61 seconds
Started Feb 25 01:18:00 PM PST 24
Finished Feb 25 01:18:02 PM PST 24
Peak memory 184164 kb
Host smart-e77a059b-16b6-4475-a887-81edf6645e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720697956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2720697956
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3945396717
Short name T600
Test name
Test status
Simulation time 31217923 ps
CPU time 1.28 seconds
Started Feb 25 01:18:01 PM PST 24
Finished Feb 25 01:18:03 PM PST 24
Peak memory 192652 kb
Host smart-6c22f9ab-0060-414d-8a2f-6aad63b7cb3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945396717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3945396717
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2673763877
Short name T704
Test name
Test status
Simulation time 327639326 ps
CPU time 1.67 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:07 PM PST 24
Peak memory 199000 kb
Host smart-f2774e79-52c0-4101-b0d5-d7ee07cec99c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673763877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2673763877
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1333210481
Short name T668
Test name
Test status
Simulation time 63232534 ps
CPU time 1.24 seconds
Started Feb 25 01:18:05 PM PST 24
Finished Feb 25 01:18:06 PM PST 24
Peak memory 198500 kb
Host smart-4121258e-5d36-480a-a371-8b619c9de0d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333210481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1333210481
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3118677477
Short name T394
Test name
Test status
Simulation time 54492295 ps
CPU time 0.57 seconds
Started Feb 25 02:31:16 PM PST 24
Finished Feb 25 02:31:16 PM PST 24
Peak memory 193740 kb
Host smart-ece12ad6-c23a-47b8-9bb1-2dde158271e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118677477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3118677477
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2455758108
Short name T374
Test name
Test status
Simulation time 5412371874 ps
CPU time 42.55 seconds
Started Feb 25 02:31:18 PM PST 24
Finished Feb 25 02:32:01 PM PST 24
Peak memory 224212 kb
Host smart-0f22bc30-f58f-4948-a33e-b18b2b19a1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2455758108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2455758108
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3958916765
Short name T480
Test name
Test status
Simulation time 13178276163 ps
CPU time 46.21 seconds
Started Feb 25 02:31:17 PM PST 24
Finished Feb 25 02:32:04 PM PST 24
Peak memory 199628 kb
Host smart-de570f97-c89c-4e3c-acc9-2df0cc0d2d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958916765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3958916765
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2493651679
Short name T246
Test name
Test status
Simulation time 3718579212 ps
CPU time 98.07 seconds
Started Feb 25 02:31:16 PM PST 24
Finished Feb 25 02:32:54 PM PST 24
Peak memory 199632 kb
Host smart-4ecc0353-9f1d-4809-871b-264d4fc0ff80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493651679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2493651679
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.171730978
Short name T523
Test name
Test status
Simulation time 10118232114 ps
CPU time 39.04 seconds
Started Feb 25 02:31:13 PM PST 24
Finished Feb 25 02:31:53 PM PST 24
Peak memory 199692 kb
Host smart-b8f1b034-f2a1-4207-a166-96f58b1da6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171730978 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.171730978
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1233342057
Short name T29
Test name
Test status
Simulation time 1497901389 ps
CPU time 38.74 seconds
Started Feb 25 02:31:17 PM PST 24
Finished Feb 25 02:31:57 PM PST 24
Peak memory 199512 kb
Host smart-2c2dce0c-9e6b-43ad-876b-5e57ea9f4496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233342057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1233342057
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4035158274
Short name T41
Test name
Test status
Simulation time 375912228 ps
CPU time 0.98 seconds
Started Feb 25 02:31:18 PM PST 24
Finished Feb 25 02:31:20 PM PST 24
Peak memory 217700 kb
Host smart-ddb5485c-9b04-4cb9-b996-0126bb900735
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035158274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4035158274
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.3779875784
Short name T403
Test name
Test status
Simulation time 81397892 ps
CPU time 1.46 seconds
Started Feb 25 02:31:20 PM PST 24
Finished Feb 25 02:31:22 PM PST 24
Peak memory 199208 kb
Host smart-d4a587b2-b128-4037-825f-f5e37b893b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779875784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.3779875784
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1019170308
Short name T384
Test name
Test status
Simulation time 51680740 ps
CPU time 1.08 seconds
Started Feb 25 02:31:14 PM PST 24
Finished Feb 25 02:31:15 PM PST 24
Peak memory 198368 kb
Host smart-c010a4a9-e62a-42c8-83f4-6d62c2123b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019170308 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1019170308
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.1341414313
Short name T323
Test name
Test status
Simulation time 145380537296 ps
CPU time 503.89 seconds
Started Feb 25 02:31:16 PM PST 24
Finished Feb 25 02:39:40 PM PST 24
Peak memory 199540 kb
Host smart-f0e6d3fa-a354-46d0-9252-912a9f4b31f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341414313 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.1341414313
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3363927145
Short name T381
Test name
Test status
Simulation time 42078087273 ps
CPU time 74.8 seconds
Started Feb 25 02:31:17 PM PST 24
Finished Feb 25 02:32:32 PM PST 24
Peak memory 199516 kb
Host smart-734eec94-3f6c-4908-8548-3b58bffa448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363927145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3363927145
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.3436727632
Short name T339
Test name
Test status
Simulation time 14783441 ps
CPU time 0.57 seconds
Started Feb 25 02:31:27 PM PST 24
Finished Feb 25 02:31:28 PM PST 24
Peak memory 193744 kb
Host smart-81ebd582-511e-42f2-b254-e222e81b6b2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436727632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.3436727632
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2261279031
Short name T567
Test name
Test status
Simulation time 2804533264 ps
CPU time 47.52 seconds
Started Feb 25 02:31:16 PM PST 24
Finished Feb 25 02:32:04 PM PST 24
Peak memory 215820 kb
Host smart-10addec8-52e5-4b97-a406-37567348670b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261279031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2261279031
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.1685852385
Short name T130
Test name
Test status
Simulation time 3793183609 ps
CPU time 17.19 seconds
Started Feb 25 02:31:15 PM PST 24
Finished Feb 25 02:31:32 PM PST 24
Peak memory 199636 kb
Host smart-77c6d0a8-8779-4b3d-a806-524738eed758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685852385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.1685852385
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2276843571
Short name T562
Test name
Test status
Simulation time 3758749975 ps
CPU time 97.87 seconds
Started Feb 25 02:31:14 PM PST 24
Finished Feb 25 02:32:52 PM PST 24
Peak memory 199664 kb
Host smart-f1038cfe-25e5-4b5c-85e3-a87ad9b2a79e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276843571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2276843571
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1835490391
Short name T389
Test name
Test status
Simulation time 1139102787 ps
CPU time 55.25 seconds
Started Feb 25 02:31:18 PM PST 24
Finished Feb 25 02:32:13 PM PST 24
Peak memory 199560 kb
Host smart-35354373-fe21-4f7b-8cb2-6e1c1debf2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835490391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1835490391
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3458636717
Short name T206
Test name
Test status
Simulation time 1145093731 ps
CPU time 16.35 seconds
Started Feb 25 02:31:18 PM PST 24
Finished Feb 25 02:31:34 PM PST 24
Peak memory 199520 kb
Host smart-52996293-3543-43a9-bc0b-40919d0e0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458636717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3458636717
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3099229928
Short name T39
Test name
Test status
Simulation time 342691676 ps
CPU time 0.99 seconds
Started Feb 25 02:31:27 PM PST 24
Finished Feb 25 02:31:29 PM PST 24
Peak memory 217700 kb
Host smart-bf08ec9b-e5d8-48f7-a44b-4f82e6c6ab9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099229928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3099229928
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.918905580
Short name T500
Test name
Test status
Simulation time 734117527 ps
CPU time 3.06 seconds
Started Feb 25 02:31:17 PM PST 24
Finished Feb 25 02:31:20 PM PST 24
Peak memory 199372 kb
Host smart-b220d620-7592-4660-8b4b-0f93647b5059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918905580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.918905580
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.4107146814
Short name T36
Test name
Test status
Simulation time 13217451000 ps
CPU time 83.14 seconds
Started Feb 25 02:31:22 PM PST 24
Finished Feb 25 02:32:45 PM PST 24
Peak memory 199656 kb
Host smart-bf68565a-8475-42af-94c9-005af3fcccb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107146814 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.4107146814
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.962743429
Short name T166
Test name
Test status
Simulation time 98812247 ps
CPU time 0.99 seconds
Started Feb 25 02:31:15 PM PST 24
Finished Feb 25 02:31:16 PM PST 24
Peak memory 197220 kb
Host smart-e2cad905-ab94-4871-ab34-da62496852a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962743429 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.962743429
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3798624119
Short name T531
Test name
Test status
Simulation time 147837383997 ps
CPU time 502.31 seconds
Started Feb 25 02:31:15 PM PST 24
Finished Feb 25 02:39:38 PM PST 24
Peak memory 199568 kb
Host smart-07f16c2b-2fe5-49c2-a821-fc7e56644cca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798624119 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_sha_vectors.3798624119
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1735749084
Short name T505
Test name
Test status
Simulation time 12447487990 ps
CPU time 55.7 seconds
Started Feb 25 02:31:15 PM PST 24
Finished Feb 25 02:32:11 PM PST 24
Peak memory 199624 kb
Host smart-fc5db664-4205-4b24-ba6d-fab76da87c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735749084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1735749084
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.107271714
Short name T183
Test name
Test status
Simulation time 21077704 ps
CPU time 0.55 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:32:04 PM PST 24
Peak memory 193652 kb
Host smart-38916b94-b30e-4c5e-a3bf-d1e190b9b4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107271714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.107271714
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2457788317
Short name T23
Test name
Test status
Simulation time 1440810516 ps
CPU time 10.76 seconds
Started Feb 25 02:31:57 PM PST 24
Finished Feb 25 02:32:08 PM PST 24
Peak memory 214996 kb
Host smart-2bcbf887-1988-4453-ac6a-2309082f1b35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457788317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2457788317
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.4201848644
Short name T135
Test name
Test status
Simulation time 2755033854 ps
CPU time 66.61 seconds
Started Feb 25 02:32:00 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 199636 kb
Host smart-8c14d973-7475-462f-989f-fe43c33ad7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201848644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.4201848644
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.3557502769
Short name T159
Test name
Test status
Simulation time 48536886 ps
CPU time 0.65 seconds
Started Feb 25 02:31:57 PM PST 24
Finished Feb 25 02:31:58 PM PST 24
Peak memory 194772 kb
Host smart-8a0a8d31-ef68-49f5-b83e-a82a158f975a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3557502769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.3557502769
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1994287974
Short name T549
Test name
Test status
Simulation time 25437645249 ps
CPU time 104.04 seconds
Started Feb 25 02:32:01 PM PST 24
Finished Feb 25 02:33:45 PM PST 24
Peak memory 199656 kb
Host smart-0deb1bc3-d3e2-439f-a4ae-326e438f675d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994287974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1994287974
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.349059377
Short name T385
Test name
Test status
Simulation time 1807391662 ps
CPU time 18.67 seconds
Started Feb 25 02:31:59 PM PST 24
Finished Feb 25 02:32:18 PM PST 24
Peak memory 199528 kb
Host smart-8c6275a8-c082-4843-b28c-e2bac1f1a8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349059377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.349059377
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.1412586662
Short name T330
Test name
Test status
Simulation time 1591134012 ps
CPU time 3.51 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:32:07 PM PST 24
Peak memory 199348 kb
Host smart-3e4fb9c0-af10-4bb3-b7f6-f878d473a0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412586662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.1412586662
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.2504839341
Short name T121
Test name
Test status
Simulation time 209715541592 ps
CPU time 763.37 seconds
Started Feb 25 02:31:58 PM PST 24
Finished Feb 25 02:44:41 PM PST 24
Peak memory 199672 kb
Host smart-452a3131-53bc-4cba-91df-3692dd1c10ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504839341 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.2504839341
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2548068078
Short name T540
Test name
Test status
Simulation time 80057912 ps
CPU time 0.94 seconds
Started Feb 25 02:31:59 PM PST 24
Finished Feb 25 02:32:00 PM PST 24
Peak memory 196688 kb
Host smart-fbfc6f27-9809-4a6a-9437-0faf1689a104
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548068078 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2548068078
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.235617502
Short name T266
Test name
Test status
Simulation time 37335178480 ps
CPU time 388.57 seconds
Started Feb 25 02:32:01 PM PST 24
Finished Feb 25 02:38:29 PM PST 24
Peak memory 199444 kb
Host smart-9160b4b4-8b61-4b2c-881f-7f7dd3c47efd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235617502 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 10.hmac_test_sha_vectors.235617502
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.30542375
Short name T431
Test name
Test status
Simulation time 7516301437 ps
CPU time 72.33 seconds
Started Feb 25 02:32:00 PM PST 24
Finished Feb 25 02:33:12 PM PST 24
Peak memory 199608 kb
Host smart-e1260a3c-6f3f-45e4-bc97-25195a62cf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30542375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.30542375
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.229693641
Short name T255
Test name
Test status
Simulation time 13837128 ps
CPU time 0.56 seconds
Started Feb 25 02:32:09 PM PST 24
Finished Feb 25 02:32:11 PM PST 24
Peak memory 193748 kb
Host smart-e887300d-d7ca-4c6a-be79-28809055ee0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229693641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.229693641
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3976024607
Short name T294
Test name
Test status
Simulation time 3333592294 ps
CPU time 36.36 seconds
Started Feb 25 02:31:58 PM PST 24
Finished Feb 25 02:32:35 PM PST 24
Peak memory 237520 kb
Host smart-94d117f5-591c-4b6c-adc1-53d9654b4501
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3976024607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3976024607
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1905815770
Short name T345
Test name
Test status
Simulation time 2062419256 ps
CPU time 36.95 seconds
Started Feb 25 02:31:56 PM PST 24
Finished Feb 25 02:32:33 PM PST 24
Peak memory 199472 kb
Host smart-f585f6cc-e053-472d-9b9a-0d1b7433d14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905815770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1905815770
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1363313587
Short name T329
Test name
Test status
Simulation time 179212951 ps
CPU time 10.11 seconds
Started Feb 25 02:32:02 PM PST 24
Finished Feb 25 02:32:12 PM PST 24
Peak memory 199520 kb
Host smart-242ac09e-c06d-44c3-9337-52e0252f8812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363313587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1363313587
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.3206899564
Short name T216
Test name
Test status
Simulation time 43859906788 ps
CPU time 132.78 seconds
Started Feb 25 02:32:00 PM PST 24
Finished Feb 25 02:34:13 PM PST 24
Peak memory 199612 kb
Host smart-9a99d1d4-ee30-4034-a0f2-eb371344e40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206899564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3206899564
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.470644015
Short name T412
Test name
Test status
Simulation time 6427023132 ps
CPU time 25.59 seconds
Started Feb 25 02:31:57 PM PST 24
Finished Feb 25 02:32:23 PM PST 24
Peak memory 199632 kb
Host smart-c3465875-514b-43e4-885e-74eef872bc3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470644015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.470644015
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3836793466
Short name T580
Test name
Test status
Simulation time 305686595 ps
CPU time 3.41 seconds
Started Feb 25 02:32:02 PM PST 24
Finished Feb 25 02:32:05 PM PST 24
Peak memory 199496 kb
Host smart-a209fc81-fc52-456b-9dd6-2878fb4bb8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836793466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3836793466
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1449516912
Short name T455
Test name
Test status
Simulation time 4270151791 ps
CPU time 53.08 seconds
Started Feb 25 02:31:56 PM PST 24
Finished Feb 25 02:32:49 PM PST 24
Peak memory 199716 kb
Host smart-69f69e4d-b506-42ab-b4d4-1a574b3dc27e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449516912 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1449516912
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1411837955
Short name T175
Test name
Test status
Simulation time 63519320 ps
CPU time 1.16 seconds
Started Feb 25 02:31:57 PM PST 24
Finished Feb 25 02:31:58 PM PST 24
Peak memory 198672 kb
Host smart-f2c2bc77-d09b-4018-9f4a-e0e6210d6bc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411837955 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1411837955
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2981466982
Short name T262
Test name
Test status
Simulation time 26635786831 ps
CPU time 436.68 seconds
Started Feb 25 02:31:59 PM PST 24
Finished Feb 25 02:39:16 PM PST 24
Peak memory 199580 kb
Host smart-536f6b5a-e617-45c8-9a03-a5a57662007a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981466982 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_sha_vectors.2981466982
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.2577150601
Short name T457
Test name
Test status
Simulation time 3271023887 ps
CPU time 43.65 seconds
Started Feb 25 02:31:58 PM PST 24
Finished Feb 25 02:32:43 PM PST 24
Peak memory 199644 kb
Host smart-61faade8-8365-40e0-b174-729b4167a3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577150601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.2577150601
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2985343699
Short name T168
Test name
Test status
Simulation time 1715607578 ps
CPU time 10.75 seconds
Started Feb 25 02:32:08 PM PST 24
Finished Feb 25 02:32:19 PM PST 24
Peak memory 199504 kb
Host smart-fea25fc2-be88-461f-9ed8-fc6ed5575043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985343699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2985343699
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.89315251
Short name T256
Test name
Test status
Simulation time 12701144407 ps
CPU time 56.9 seconds
Started Feb 25 02:32:08 PM PST 24
Finished Feb 25 02:33:06 PM PST 24
Peak memory 199644 kb
Host smart-31c2befe-186d-4e6e-a915-72036ae8b0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89315251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.89315251
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.3341850900
Short name T50
Test name
Test status
Simulation time 1849261921 ps
CPU time 46.65 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:57 PM PST 24
Peak memory 199504 kb
Host smart-54cb6c46-fbe8-42b4-b6c7-a69309b60004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3341850900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.3341850900
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3891479683
Short name T506
Test name
Test status
Simulation time 10011078437 ps
CPU time 114.71 seconds
Started Feb 25 02:32:11 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 199640 kb
Host smart-9cfc2809-90fe-4132-8428-755d27576578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891479683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3891479683
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.509638932
Short name T180
Test name
Test status
Simulation time 4295707766 ps
CPU time 38.06 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:48 PM PST 24
Peak memory 199668 kb
Host smart-997b7ca8-06d7-4bc1-b7b0-4ba7a56484b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509638932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.509638932
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3053548897
Short name T213
Test name
Test status
Simulation time 390055013 ps
CPU time 3.18 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:13 PM PST 24
Peak memory 199412 kb
Host smart-c9188643-3ae1-4ea1-92dd-59296df6acca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053548897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3053548897
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1610134705
Short name T541
Test name
Test status
Simulation time 61818056 ps
CPU time 1.22 seconds
Started Feb 25 02:32:12 PM PST 24
Finished Feb 25 02:32:13 PM PST 24
Peak memory 198420 kb
Host smart-bb7117d9-590a-44d7-8e43-1d5a232f1382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610134705 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1610134705
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3362007008
Short name T476
Test name
Test status
Simulation time 66576074 ps
CPU time 1.15 seconds
Started Feb 25 02:32:11 PM PST 24
Finished Feb 25 02:32:13 PM PST 24
Peak memory 198120 kb
Host smart-8a8ec357-e6ce-499d-9a47-622283f056f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362007008 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3362007008
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.3614757510
Short name T171
Test name
Test status
Simulation time 29133575490 ps
CPU time 342.81 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:37:53 PM PST 24
Peak memory 199468 kb
Host smart-1be578c6-c1a5-42d9-b1cd-01c29b04b352
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614757510 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.3614757510
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3610261488
Short name T502
Test name
Test status
Simulation time 1733514469 ps
CPU time 8.27 seconds
Started Feb 25 02:32:09 PM PST 24
Finished Feb 25 02:32:18 PM PST 24
Peak memory 199504 kb
Host smart-c5e8d988-abac-4f9f-9648-5323264f59b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610261488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3610261488
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2862072506
Short name T336
Test name
Test status
Simulation time 14523699 ps
CPU time 0.59 seconds
Started Feb 25 02:32:18 PM PST 24
Finished Feb 25 02:32:20 PM PST 24
Peak memory 193752 kb
Host smart-a892218a-91a3-417f-9648-e25e2462be3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862072506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2862072506
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.221269941
Short name T124
Test name
Test status
Simulation time 6582595327 ps
CPU time 59.95 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:33:10 PM PST 24
Peak memory 224188 kb
Host smart-8221410c-b6b3-400f-9cdd-f7b90b2cf5b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=221269941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.221269941
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1835343359
Short name T532
Test name
Test status
Simulation time 443302496 ps
CPU time 20.11 seconds
Started Feb 25 02:32:08 PM PST 24
Finished Feb 25 02:32:28 PM PST 24
Peak memory 199580 kb
Host smart-ca25600b-bdbd-43fa-b960-9f60baef43d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835343359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1835343359
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2648521263
Short name T122
Test name
Test status
Simulation time 8769175077 ps
CPU time 113.95 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:34:05 PM PST 24
Peak memory 199192 kb
Host smart-13fcb14e-66ac-4d11-bce4-c91e66cd1f8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2648521263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2648521263
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1407170609
Short name T410
Test name
Test status
Simulation time 9143387255 ps
CPU time 23.81 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:34 PM PST 24
Peak memory 199640 kb
Host smart-9e2570aa-1448-4e78-bca5-f9c8c1b8295d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407170609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1407170609
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1056185191
Short name T286
Test name
Test status
Simulation time 1077939730 ps
CPU time 56.75 seconds
Started Feb 25 02:32:08 PM PST 24
Finished Feb 25 02:33:05 PM PST 24
Peak memory 199532 kb
Host smart-c685eea0-6264-486a-9e9f-0eba129cb6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056185191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1056185191
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3433099685
Short name T511
Test name
Test status
Simulation time 59000154 ps
CPU time 0.73 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:32:12 PM PST 24
Peak memory 195744 kb
Host smart-884f6e9e-25d2-4d4a-8a95-8efb6cf66630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433099685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3433099685
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.2338982990
Short name T360
Test name
Test status
Simulation time 151031501909 ps
CPU time 360.27 seconds
Started Feb 25 02:32:27 PM PST 24
Finished Feb 25 02:38:28 PM PST 24
Peak memory 198612 kb
Host smart-fc6efa4c-96a0-4031-9bc1-62728b07a763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338982990 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.2338982990
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2865226346
Short name T558
Test name
Test status
Simulation time 29181878 ps
CPU time 0.88 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:32:21 PM PST 24
Peak memory 196832 kb
Host smart-4bb8ba21-88ac-493e-9a3e-12f0a58619db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865226346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2865226346
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.1991821886
Short name T152
Test name
Test status
Simulation time 39018603498 ps
CPU time 429.82 seconds
Started Feb 25 02:32:08 PM PST 24
Finished Feb 25 02:39:19 PM PST 24
Peak memory 199560 kb
Host smart-be6b6851-9520-48a1-bbbe-0dfa51a5d62a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991821886 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.1991821886
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.3890292570
Short name T284
Test name
Test status
Simulation time 2277277256 ps
CPU time 55.32 seconds
Started Feb 25 02:32:10 PM PST 24
Finished Feb 25 02:33:05 PM PST 24
Peak memory 199644 kb
Host smart-7cb9c661-2887-4257-a204-80f21f9f1c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890292570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.3890292570
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1222431224
Short name T545
Test name
Test status
Simulation time 73719885 ps
CPU time 0.57 seconds
Started Feb 25 02:32:18 PM PST 24
Finished Feb 25 02:32:20 PM PST 24
Peak memory 193904 kb
Host smart-d8ba6c8e-fc8d-4809-9a90-50c4c87b4ff7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222431224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1222431224
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.1232559434
Short name T398
Test name
Test status
Simulation time 168560180 ps
CPU time 2.45 seconds
Started Feb 25 02:32:17 PM PST 24
Finished Feb 25 02:32:19 PM PST 24
Peak memory 199484 kb
Host smart-b5ab7f82-8a03-4f32-87bd-42b25113f7de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232559434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.1232559434
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.539025431
Short name T288
Test name
Test status
Simulation time 183313428 ps
CPU time 5.22 seconds
Started Feb 25 02:32:26 PM PST 24
Finished Feb 25 02:32:31 PM PST 24
Peak memory 199204 kb
Host smart-0bf0b48e-9750-4534-9d22-3f9ec85575ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539025431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.539025431
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.20211808
Short name T2
Test name
Test status
Simulation time 6693855435 ps
CPU time 89.87 seconds
Started Feb 25 02:32:24 PM PST 24
Finished Feb 25 02:33:55 PM PST 24
Peak memory 199668 kb
Host smart-d6f618bc-5e78-4926-907a-d846ded5b573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20211808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.20211808
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3451920854
Short name T359
Test name
Test status
Simulation time 642351843 ps
CPU time 31.72 seconds
Started Feb 25 02:32:26 PM PST 24
Finished Feb 25 02:32:59 PM PST 24
Peak memory 199512 kb
Host smart-8e0cc906-6808-44c4-890e-5ec94d7e65ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451920854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3451920854
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1243973156
Short name T382
Test name
Test status
Simulation time 5757241071 ps
CPU time 48.24 seconds
Started Feb 25 02:32:19 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 199608 kb
Host smart-9f682f80-c6c6-4c5f-a70e-f3c0129aeb7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243973156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1243973156
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.1253024340
Short name T391
Test name
Test status
Simulation time 2011121436 ps
CPU time 3.51 seconds
Started Feb 25 02:32:22 PM PST 24
Finished Feb 25 02:32:26 PM PST 24
Peak memory 199444 kb
Host smart-e5f1f3b9-ace0-4c14-ad96-56ab7fe19a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253024340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.1253024340
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.28076587
Short name T331
Test name
Test status
Simulation time 5576916682 ps
CPU time 251.09 seconds
Started Feb 25 02:32:22 PM PST 24
Finished Feb 25 02:36:33 PM PST 24
Peak memory 199688 kb
Host smart-f66154c9-ed41-4ee2-9e9b-457ee69858ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28076587 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.28076587
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1856314253
Short name T311
Test name
Test status
Simulation time 49091645 ps
CPU time 0.92 seconds
Started Feb 25 02:32:21 PM PST 24
Finished Feb 25 02:32:22 PM PST 24
Peak memory 196856 kb
Host smart-8c4c2fe0-5252-4d21-850e-12ea4079e376
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856314253 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1856314253
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3212265155
Short name T163
Test name
Test status
Simulation time 29809903558 ps
CPU time 444.15 seconds
Started Feb 25 02:32:19 PM PST 24
Finished Feb 25 02:39:44 PM PST 24
Peak memory 199576 kb
Host smart-346d7604-1f30-4532-9368-391b3f1c7a51
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212265155 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.3212265155
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1142766251
Short name T45
Test name
Test status
Simulation time 2274550796 ps
CPU time 29.62 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:32:50 PM PST 24
Peak memory 199572 kb
Host smart-2760b851-4de8-4c06-ac19-cf02f8c0085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142766251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1142766251
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2087837830
Short name T343
Test name
Test status
Simulation time 11585156 ps
CPU time 0.57 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:32:21 PM PST 24
Peak memory 193752 kb
Host smart-75a7b874-0955-4e42-924a-656c3247be52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087837830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2087837830
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4098988289
Short name T364
Test name
Test status
Simulation time 1395642116 ps
CPU time 21.23 seconds
Started Feb 25 02:32:21 PM PST 24
Finished Feb 25 02:32:43 PM PST 24
Peak memory 215228 kb
Host smart-1f89982b-b757-409b-b1f5-e94d4cdcdfb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098988289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4098988289
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3986222965
Short name T493
Test name
Test status
Simulation time 713610229 ps
CPU time 16.32 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:32:37 PM PST 24
Peak memory 199444 kb
Host smart-81b84fd9-1c53-4eaa-a2e7-21ba2a902902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986222965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3986222965
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2286521255
Short name T579
Test name
Test status
Simulation time 5745140563 ps
CPU time 75.39 seconds
Started Feb 25 02:32:27 PM PST 24
Finished Feb 25 02:33:43 PM PST 24
Peak memory 199616 kb
Host smart-2fc5b9b5-c768-442f-b536-9fee49550a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2286521255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2286521255
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2061022754
Short name T208
Test name
Test status
Simulation time 1742594971 ps
CPU time 23.37 seconds
Started Feb 25 02:32:22 PM PST 24
Finished Feb 25 02:32:46 PM PST 24
Peak memory 199448 kb
Host smart-74862331-c5df-4106-aa33-b53d795601c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061022754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2061022754
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.3139924093
Short name T513
Test name
Test status
Simulation time 8278402344 ps
CPU time 24.97 seconds
Started Feb 25 02:32:22 PM PST 24
Finished Feb 25 02:32:47 PM PST 24
Peak memory 199636 kb
Host smart-ba64adfe-67d9-44cd-bc6f-27bbe15401db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139924093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.3139924093
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3263626895
Short name T321
Test name
Test status
Simulation time 28892600 ps
CPU time 0.7 seconds
Started Feb 25 02:32:18 PM PST 24
Finished Feb 25 02:32:20 PM PST 24
Peak memory 195300 kb
Host smart-cb38d463-3949-422b-93dd-b785e2d632be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263626895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3263626895
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3260601526
Short name T509
Test name
Test status
Simulation time 117966450108 ps
CPU time 1464.65 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:56:45 PM PST 24
Peak memory 238592 kb
Host smart-9745042c-9d4d-4e33-8cbc-a5c52558a4b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260601526 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3260601526
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3446718758
Short name T264
Test name
Test status
Simulation time 243956765 ps
CPU time 0.94 seconds
Started Feb 25 02:32:18 PM PST 24
Finished Feb 25 02:32:20 PM PST 24
Peak memory 197156 kb
Host smart-fdb79505-8cb2-4bc2-ac72-47b6cbe5c7c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446718758 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3446718758
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.2227004556
Short name T494
Test name
Test status
Simulation time 8900614186 ps
CPU time 434.46 seconds
Started Feb 25 02:32:26 PM PST 24
Finished Feb 25 02:39:40 PM PST 24
Peak memory 199324 kb
Host smart-b2311505-249a-412c-bea9-bcc47146262a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227004556 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.hmac_test_sha_vectors.2227004556
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2111474983
Short name T111
Test name
Test status
Simulation time 11755862974 ps
CPU time 71.38 seconds
Started Feb 25 02:32:17 PM PST 24
Finished Feb 25 02:33:29 PM PST 24
Peak memory 199664 kb
Host smart-73b8fcc6-846d-4a96-a58f-6a526a6f7ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111474983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2111474983
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.527382957
Short name T379
Test name
Test status
Simulation time 44348806 ps
CPU time 0.56 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:32:34 PM PST 24
Peak memory 193732 kb
Host smart-1f31fe8d-6690-4acf-a5a0-e8038ef386bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527382957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.527382957
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2633143052
Short name T342
Test name
Test status
Simulation time 482730294 ps
CPU time 18.49 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:32:39 PM PST 24
Peak memory 228912 kb
Host smart-a3c50817-7115-43dc-bf7d-42630e82b746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633143052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2633143052
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.769239297
Short name T325
Test name
Test status
Simulation time 932625913 ps
CPU time 41.44 seconds
Started Feb 25 02:32:21 PM PST 24
Finished Feb 25 02:33:03 PM PST 24
Peak memory 199520 kb
Host smart-ec330d59-bf75-4884-b944-d390433bb11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769239297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.769239297
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2877706721
Short name T548
Test name
Test status
Simulation time 18467552 ps
CPU time 0.62 seconds
Started Feb 25 02:32:18 PM PST 24
Finished Feb 25 02:32:19 PM PST 24
Peak memory 194980 kb
Host smart-80b20cc5-6ae0-4458-8db1-c1c3c60b18ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877706721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2877706721
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.21200658
Short name T247
Test name
Test status
Simulation time 1157639066 ps
CPU time 31.06 seconds
Started Feb 25 02:32:27 PM PST 24
Finished Feb 25 02:32:59 PM PST 24
Peak memory 198536 kb
Host smart-2da16e9d-0c85-4ed5-afc6-23aa09c2deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21200658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.21200658
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.21912097
Short name T341
Test name
Test status
Simulation time 4399550080 ps
CPU time 85.44 seconds
Started Feb 25 02:32:20 PM PST 24
Finished Feb 25 02:33:46 PM PST 24
Peak memory 199592 kb
Host smart-5883b7d2-54be-4655-a16f-6112f33445d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21912097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.21912097
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.36636514
Short name T76
Test name
Test status
Simulation time 126363057 ps
CPU time 1.65 seconds
Started Feb 25 02:32:19 PM PST 24
Finished Feb 25 02:32:21 PM PST 24
Peak memory 199648 kb
Host smart-0d0b62b3-7908-4abc-a868-d139fc7e6de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36636514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.36636514
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3644164108
Short name T498
Test name
Test status
Simulation time 1716050921753 ps
CPU time 1476.01 seconds
Started Feb 25 02:32:40 PM PST 24
Finished Feb 25 02:57:16 PM PST 24
Peak memory 222552 kb
Host smart-2bcfea0e-5506-4081-8b93-56a2dd9797fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644164108 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3644164108
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1853601208
Short name T9
Test name
Test status
Simulation time 60517178 ps
CPU time 1.22 seconds
Started Feb 25 02:32:43 PM PST 24
Finished Feb 25 02:32:45 PM PST 24
Peak memory 198124 kb
Host smart-89bed085-eb0e-4718-b491-ebf0c70f106e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853601208 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1853601208
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1822118342
Short name T212
Test name
Test status
Simulation time 80525552703 ps
CPU time 450.64 seconds
Started Feb 25 02:32:40 PM PST 24
Finished Feb 25 02:40:11 PM PST 24
Peak memory 199484 kb
Host smart-df404bd1-c4ec-4c63-b93d-cb6ee60eb3ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822118342 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.1822118342
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.832022509
Short name T285
Test name
Test status
Simulation time 4616914832 ps
CPU time 46.69 seconds
Started Feb 25 02:32:40 PM PST 24
Finished Feb 25 02:33:27 PM PST 24
Peak memory 199656 kb
Host smart-cb6ec680-e0c4-4d0c-bdde-31e87eea77d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832022509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.832022509
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/163.hmac_stress_all_with_rand_reset.615786576
Short name T17
Test name
Test status
Simulation time 4094425605 ps
CPU time 190.56 seconds
Started Feb 25 02:35:25 PM PST 24
Finished Feb 25 02:38:36 PM PST 24
Peak memory 216164 kb
Host smart-3f4e9f14-5d8e-4467-b7c0-b54e2e5a6b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=615786576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.hmac_stress_all_with_rand_reset.615786576
Directory /workspace/163.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1685724998
Short name T497
Test name
Test status
Simulation time 18196419 ps
CPU time 0.55 seconds
Started Feb 25 02:32:39 PM PST 24
Finished Feb 25 02:32:40 PM PST 24
Peak memory 193944 kb
Host smart-00be64fe-2973-4d98-b675-7fbf74c743e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685724998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1685724998
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3366487685
Short name T299
Test name
Test status
Simulation time 849816956 ps
CPU time 25.26 seconds
Started Feb 25 02:32:41 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 215436 kb
Host smart-6444a517-afbd-40d9-9e76-ea60f03fb2b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3366487685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3366487685
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2430780501
Short name T426
Test name
Test status
Simulation time 3095093296 ps
CPU time 57.75 seconds
Started Feb 25 02:32:42 PM PST 24
Finished Feb 25 02:33:40 PM PST 24
Peak memory 199596 kb
Host smart-a0e58a20-1ceb-4eb3-b20b-bb8296c8dc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430780501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2430780501
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3222352354
Short name T437
Test name
Test status
Simulation time 524595727 ps
CPU time 14.55 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:32:48 PM PST 24
Peak memory 199552 kb
Host smart-4c9266d7-9048-455e-a52d-d9a3e82aa014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3222352354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3222352354
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1314549789
Short name T283
Test name
Test status
Simulation time 8187029205 ps
CPU time 135.33 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:34:48 PM PST 24
Peak memory 199652 kb
Host smart-b27e2d15-bd70-4f9a-8f34-562a325d6a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314549789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1314549789
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.4104843323
Short name T219
Test name
Test status
Simulation time 12501718549 ps
CPU time 111.95 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:34:25 PM PST 24
Peak memory 199652 kb
Host smart-e976e8b9-ff63-4d1f-a7c3-e4ed51423697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104843323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.4104843323
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3087099826
Short name T361
Test name
Test status
Simulation time 97354032 ps
CPU time 1.56 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:32:35 PM PST 24
Peak memory 199472 kb
Host smart-cd3054d2-840c-4d5e-9fe9-f4a0be568f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087099826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3087099826
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.1347314131
Short name T352
Test name
Test status
Simulation time 61298530 ps
CPU time 1.2 seconds
Started Feb 25 02:32:34 PM PST 24
Finished Feb 25 02:32:35 PM PST 24
Peak memory 197440 kb
Host smart-73e43c6c-9f86-4b02-85fb-e342fccecf60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347314131 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.1347314131
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.975541835
Short name T280
Test name
Test status
Simulation time 44363874985 ps
CPU time 523.09 seconds
Started Feb 25 02:32:34 PM PST 24
Finished Feb 25 02:41:17 PM PST 24
Peak memory 199552 kb
Host smart-ac9c739d-5af9-4b5f-bfd1-0d7350f2ebe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975541835 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.hmac_test_sha_vectors.975541835
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.1285925687
Short name T469
Test name
Test status
Simulation time 1015460269 ps
CPU time 18.22 seconds
Started Feb 25 02:32:41 PM PST 24
Finished Feb 25 02:32:59 PM PST 24
Peak memory 199500 kb
Host smart-0400c4b9-8d13-4c8b-9827-742f92fc5285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285925687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.1285925687
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.1478108239
Short name T575
Test name
Test status
Simulation time 36127784 ps
CPU time 0.59 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:32:49 PM PST 24
Peak memory 193740 kb
Host smart-c30515da-efbd-436d-a979-c00dd6d893d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478108239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.1478108239
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2939652684
Short name T251
Test name
Test status
Simulation time 8963716776 ps
CPU time 38.95 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:33:27 PM PST 24
Peak memory 207836 kb
Host smart-81ff7014-6c01-4e28-a45b-5adf73d4cbca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2939652684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2939652684
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2261288815
Short name T473
Test name
Test status
Simulation time 2894231461 ps
CPU time 21.39 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 02:33:08 PM PST 24
Peak memory 199572 kb
Host smart-353a3fb0-6da5-4d91-a2ee-870b66b4e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261288815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2261288815
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3138368269
Short name T222
Test name
Test status
Simulation time 205699674 ps
CPU time 10.73 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 02:32:57 PM PST 24
Peak memory 199484 kb
Host smart-49046a72-fd9d-424f-86fd-d51fdd59c9bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3138368269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3138368269
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4267638983
Short name T585
Test name
Test status
Simulation time 12953900017 ps
CPU time 81.05 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:34:10 PM PST 24
Peak memory 199604 kb
Host smart-6752ab5e-ad6f-4c80-8729-e37eb23d810c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267638983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4267638983
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2307038059
Short name T202
Test name
Test status
Simulation time 4026618261 ps
CPU time 48.07 seconds
Started Feb 25 02:32:45 PM PST 24
Finished Feb 25 02:33:34 PM PST 24
Peak memory 199644 kb
Host smart-4a2e64cc-259c-4a49-adfd-146a8c568344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307038059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2307038059
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3163054934
Short name T201
Test name
Test status
Simulation time 51942857 ps
CPU time 1.62 seconds
Started Feb 25 02:32:33 PM PST 24
Finished Feb 25 02:32:35 PM PST 24
Peak memory 199292 kb
Host smart-077a0365-9365-4a99-b253-4a60c957fb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163054934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3163054934
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2946623775
Short name T496
Test name
Test status
Simulation time 49742104289 ps
CPU time 530.72 seconds
Started Feb 25 02:32:51 PM PST 24
Finished Feb 25 02:41:42 PM PST 24
Peak memory 207904 kb
Host smart-1df44b65-6694-4641-bc15-3b87b7c3ed5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946623775 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2946623775
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3144247469
Short name T326
Test name
Test status
Simulation time 41650427 ps
CPU time 0.98 seconds
Started Feb 25 02:32:51 PM PST 24
Finished Feb 25 02:32:52 PM PST 24
Peak memory 197168 kb
Host smart-8f851f8a-b02e-4511-8270-46e24f5fae5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144247469 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3144247469
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.4090046349
Short name T173
Test name
Test status
Simulation time 15634761837 ps
CPU time 411.66 seconds
Started Feb 25 02:32:49 PM PST 24
Finished Feb 25 02:39:41 PM PST 24
Peak memory 199584 kb
Host smart-c0e7ce55-b39a-48b4-b940-3ff1cbd68fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090046349 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.4090046349
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3993697015
Short name T214
Test name
Test status
Simulation time 192953186 ps
CPU time 10.37 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:57 PM PST 24
Peak memory 199504 kb
Host smart-4c1a76db-28e0-4aea-bf2c-23140de9bbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993697015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3993697015
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/180.hmac_stress_all_with_rand_reset.3106670838
Short name T58
Test name
Test status
Simulation time 298479460471 ps
CPU time 1723.32 seconds
Started Feb 25 02:35:46 PM PST 24
Finished Feb 25 03:04:30 PM PST 24
Peak memory 218084 kb
Host smart-20d8372e-3496-442f-8b4e-93112b88a630
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106670838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.hmac_stress_all_with_rand_reset.3106670838
Directory /workspace/180.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/182.hmac_stress_all_with_rand_reset.1206592558
Short name T56
Test name
Test status
Simulation time 15832841196 ps
CPU time 431.88 seconds
Started Feb 25 02:35:47 PM PST 24
Finished Feb 25 02:43:00 PM PST 24
Peak memory 216212 kb
Host smart-15d27c19-8479-4a18-a8ee-779f794d3729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1206592558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.hmac_stress_all_with_rand_reset.1206592558
Directory /workspace/182.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2500091114
Short name T443
Test name
Test status
Simulation time 40347233 ps
CPU time 0.58 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 02:32:46 PM PST 24
Peak memory 193796 kb
Host smart-2e0a5226-3fa2-487c-a7d5-66b43bb1c0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500091114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2500091114
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.2828319907
Short name T207
Test name
Test status
Simulation time 296370984 ps
CPU time 8.72 seconds
Started Feb 25 02:32:44 PM PST 24
Finished Feb 25 02:32:53 PM PST 24
Peak memory 199468 kb
Host smart-0e566b33-9451-41d7-a6e7-f50b4013515f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828319907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.2828319907
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1396551244
Short name T467
Test name
Test status
Simulation time 37130515 ps
CPU time 0.61 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 02:32:47 PM PST 24
Peak memory 194132 kb
Host smart-0057e9fd-77be-4862-ba64-c0b0297141c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396551244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1396551244
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.325331901
Short name T566
Test name
Test status
Simulation time 1380391756 ps
CPU time 76.87 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:34:05 PM PST 24
Peak memory 199520 kb
Host smart-84fcb50e-9aaa-4196-bd5e-690d53e24d94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=325331901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.325331901
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.4087666581
Short name T261
Test name
Test status
Simulation time 15487148498 ps
CPU time 134.68 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:35:13 PM PST 24
Peak memory 199628 kb
Host smart-e57e3f7d-d74b-4d90-b99d-5a8de8b3ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087666581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.4087666581
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.52947638
Short name T551
Test name
Test status
Simulation time 4870350372 ps
CPU time 65.99 seconds
Started Feb 25 02:32:51 PM PST 24
Finished Feb 25 02:33:57 PM PST 24
Peak memory 199672 kb
Host smart-81d90a68-60f8-4ee0-bc3d-595ef7f383a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52947638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.52947638
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1835954106
Short name T451
Test name
Test status
Simulation time 144655509 ps
CPU time 1.37 seconds
Started Feb 25 02:32:49 PM PST 24
Finished Feb 25 02:32:51 PM PST 24
Peak memory 198312 kb
Host smart-3901bdcd-611b-425a-bdbf-8755c3b9ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835954106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1835954106
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1830678092
Short name T572
Test name
Test status
Simulation time 56905084474 ps
CPU time 1011.32 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 02:49:37 PM PST 24
Peak memory 240664 kb
Host smart-2a2e0dd5-6ec9-4b24-a81f-fab68cf92679
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830678092 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1830678092
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.4255581105
Short name T447
Test name
Test status
Simulation time 48551246 ps
CPU time 0.89 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:48 PM PST 24
Peak memory 196900 kb
Host smart-d532e4f2-8557-4932-8fb5-f6fa71ffb73b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255581105 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.4255581105
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.2729773253
Short name T587
Test name
Test status
Simulation time 44421119144 ps
CPU time 473.29 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:40:42 PM PST 24
Peak memory 199564 kb
Host smart-0b7eba2b-3252-4312-ae29-03d6c8a1edf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729773253 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_sha_vectors.2729773253
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2080782694
Short name T365
Test name
Test status
Simulation time 3206713170 ps
CPU time 7.74 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:55 PM PST 24
Peak memory 199656 kb
Host smart-8b548674-c926-4c9d-bd2f-b444f01fea40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080782694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2080782694
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/195.hmac_stress_all_with_rand_reset.1157238980
Short name T6
Test name
Test status
Simulation time 17468677405 ps
CPU time 312.49 seconds
Started Feb 25 02:35:45 PM PST 24
Finished Feb 25 02:40:58 PM PST 24
Peak memory 224344 kb
Host smart-aef8f309-b02d-478d-983f-abbcbb078cb3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157238980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.hmac_stress_all_with_rand_reset.1157238980
Directory /workspace/195.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.3222029589
Short name T350
Test name
Test status
Simulation time 22238473 ps
CPU time 0.57 seconds
Started Feb 25 02:31:26 PM PST 24
Finished Feb 25 02:31:26 PM PST 24
Peak memory 193732 kb
Host smart-b54c5d9e-92d9-480a-831e-86541d25048d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222029589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.3222029589
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2624675769
Short name T393
Test name
Test status
Simulation time 1398750380 ps
CPU time 20.74 seconds
Started Feb 25 02:31:27 PM PST 24
Finished Feb 25 02:31:48 PM PST 24
Peak memory 215032 kb
Host smart-2227c33d-3e3c-4615-b6a7-00f874b88533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624675769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2624675769
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1793634660
Short name T109
Test name
Test status
Simulation time 2834652449 ps
CPU time 37.22 seconds
Started Feb 25 02:31:27 PM PST 24
Finished Feb 25 02:32:04 PM PST 24
Peak memory 199632 kb
Host smart-f7fb6ece-ec04-44ff-a75b-29b88d8a5223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793634660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1793634660
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1323030368
Short name T512
Test name
Test status
Simulation time 267848534 ps
CPU time 15.04 seconds
Started Feb 25 02:31:23 PM PST 24
Finished Feb 25 02:31:38 PM PST 24
Peak memory 199524 kb
Host smart-08b62285-44be-4dc0-b67c-b236c23dd2c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1323030368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1323030368
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.120234285
Short name T305
Test name
Test status
Simulation time 16644979925 ps
CPU time 41.96 seconds
Started Feb 25 02:31:23 PM PST 24
Finished Feb 25 02:32:06 PM PST 24
Peak memory 199660 kb
Host smart-07476ed5-70c3-45c2-9f28-e64391fc37e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120234285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.120234285
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.1823260211
Short name T167
Test name
Test status
Simulation time 4345189920 ps
CPU time 16.81 seconds
Started Feb 25 02:31:28 PM PST 24
Finished Feb 25 02:31:45 PM PST 24
Peak memory 199640 kb
Host smart-6b3fe91e-01e6-4599-a30a-e60ca0a544c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823260211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.1823260211
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_smoke.1170704801
Short name T408
Test name
Test status
Simulation time 1095162343 ps
CPU time 3.72 seconds
Started Feb 25 02:31:24 PM PST 24
Finished Feb 25 02:31:28 PM PST 24
Peak memory 199520 kb
Host smart-5558fa14-82ca-4387-8884-772b5400d404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170704801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1170704801
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2463160214
Short name T54
Test name
Test status
Simulation time 451713777617 ps
CPU time 592.17 seconds
Started Feb 25 02:31:23 PM PST 24
Finished Feb 25 02:41:15 PM PST 24
Peak memory 207896 kb
Host smart-f65fea89-428d-4964-8c25-798c7717d781
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463160214 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2463160214
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1570554792
Short name T153
Test name
Test status
Simulation time 139051264 ps
CPU time 1.17 seconds
Started Feb 25 02:31:23 PM PST 24
Finished Feb 25 02:31:24 PM PST 24
Peak memory 199060 kb
Host smart-7dabe1f0-a359-449d-a345-932c9bdbf806
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570554792 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1570554792
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2018599636
Short name T524
Test name
Test status
Simulation time 39834642761 ps
CPU time 452.66 seconds
Started Feb 25 02:31:29 PM PST 24
Finished Feb 25 02:39:02 PM PST 24
Peak memory 199572 kb
Host smart-117ea954-9ec6-4a0e-8df0-2199399efdca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018599636 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.2018599636
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3293955454
Short name T397
Test name
Test status
Simulation time 17823072596 ps
CPU time 64.1 seconds
Started Feb 25 02:31:29 PM PST 24
Finished Feb 25 02:32:33 PM PST 24
Peak memory 199652 kb
Host smart-07413be7-0bd9-46d0-b06e-144afd3df3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293955454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3293955454
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.578928462
Short name T491
Test name
Test status
Simulation time 23233321 ps
CPU time 0.58 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:48 PM PST 24
Peak memory 193760 kb
Host smart-34ac0ba9-26c8-4ce8-9e8c-9d01b340593a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578928462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.578928462
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.864574605
Short name T186
Test name
Test status
Simulation time 2720045910 ps
CPU time 24.63 seconds
Started Feb 25 02:32:50 PM PST 24
Finished Feb 25 02:33:15 PM PST 24
Peak memory 220100 kb
Host smart-d19d4a78-8e50-4a5e-af9f-47cdf314695b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=864574605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.864574605
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2307145597
Short name T189
Test name
Test status
Simulation time 13119155131 ps
CPU time 43.66 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:33:32 PM PST 24
Peak memory 199656 kb
Host smart-1b16a2d4-66d0-4308-9fb6-e638ba6622d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307145597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2307145597
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3926528951
Short name T232
Test name
Test status
Simulation time 2051976620 ps
CPU time 29.78 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:33:18 PM PST 24
Peak memory 199524 kb
Host smart-d83a45c1-6b93-4204-b96f-e0bc107db8a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3926528951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3926528951
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2575002531
Short name T484
Test name
Test status
Simulation time 13372786163 ps
CPU time 162.06 seconds
Started Feb 25 02:32:48 PM PST 24
Finished Feb 25 02:35:31 PM PST 24
Peak memory 199636 kb
Host smart-b2a5875e-8fe9-4872-ad1c-1e2d83bea4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575002531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2575002531
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.190497065
Short name T174
Test name
Test status
Simulation time 5924795218 ps
CPU time 69.49 seconds
Started Feb 25 02:32:45 PM PST 24
Finished Feb 25 02:33:55 PM PST 24
Peak memory 199616 kb
Host smart-d963564e-61f8-4f1e-b3f6-4b8f2657e90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190497065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.190497065
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.3903540498
Short name T199
Test name
Test status
Simulation time 102504451 ps
CPU time 2.69 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:50 PM PST 24
Peak memory 199544 kb
Host smart-c1bc2ca7-1f5d-41ae-b927-6e8432498f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903540498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.3903540498
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.607008386
Short name T563
Test name
Test status
Simulation time 117105323075 ps
CPU time 2032.71 seconds
Started Feb 25 02:32:46 PM PST 24
Finished Feb 25 03:06:39 PM PST 24
Peak memory 239364 kb
Host smart-eef8cfe0-7926-4f77-933e-abe5f71f5d22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607008386 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.607008386
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3505448891
Short name T376
Test name
Test status
Simulation time 105402753 ps
CPU time 1.12 seconds
Started Feb 25 02:32:47 PM PST 24
Finished Feb 25 02:32:49 PM PST 24
Peak memory 198352 kb
Host smart-63b340f9-42ae-44c4-8154-301e50a7360f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505448891 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3505448891
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.555954870
Short name T298
Test name
Test status
Simulation time 12430044646 ps
CPU time 41.26 seconds
Started Feb 25 02:32:49 PM PST 24
Finished Feb 25 02:33:31 PM PST 24
Peak memory 199676 kb
Host smart-1b33ad95-c0ef-4684-9eff-74ce47f519f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555954870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.555954870
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1314646080
Short name T395
Test name
Test status
Simulation time 81957032 ps
CPU time 0.59 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:33:00 PM PST 24
Peak memory 194788 kb
Host smart-d8335252-bf10-4106-89af-de39cd4b727e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314646080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1314646080
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.2089768842
Short name T583
Test name
Test status
Simulation time 3998072795 ps
CPU time 26.08 seconds
Started Feb 25 02:32:53 PM PST 24
Finished Feb 25 02:33:19 PM PST 24
Peak memory 215996 kb
Host smart-86585294-d7e0-4ae6-8153-f93a4ec5ce50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089768842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.2089768842
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.3492251359
Short name T366
Test name
Test status
Simulation time 2195598679 ps
CPU time 25.17 seconds
Started Feb 25 02:32:54 PM PST 24
Finished Feb 25 02:33:20 PM PST 24
Peak memory 199636 kb
Host smart-96dfb8b1-5445-47c6-a1ba-a2a8d1b546d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492251359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.3492251359
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.260631354
Short name T164
Test name
Test status
Simulation time 22918355 ps
CPU time 0.89 seconds
Started Feb 25 02:32:57 PM PST 24
Finished Feb 25 02:32:58 PM PST 24
Peak memory 197036 kb
Host smart-8dfa8787-5162-4238-8b11-3c342df3d547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=260631354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.260631354
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.528583345
Short name T44
Test name
Test status
Simulation time 16517904532 ps
CPU time 185.4 seconds
Started Feb 25 02:32:56 PM PST 24
Finished Feb 25 02:36:01 PM PST 24
Peak memory 199732 kb
Host smart-0574ff0d-3f42-4223-b11d-2447ea8b89f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528583345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.528583345
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.904245029
Short name T510
Test name
Test status
Simulation time 8756115577 ps
CPU time 30.39 seconds
Started Feb 25 02:32:57 PM PST 24
Finished Feb 25 02:33:27 PM PST 24
Peak memory 199632 kb
Host smart-f1d6086d-16bb-45b2-88a4-b5f9ceb7d050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904245029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.904245029
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2431748937
Short name T49
Test name
Test status
Simulation time 130768673 ps
CPU time 1.69 seconds
Started Feb 25 02:32:55 PM PST 24
Finished Feb 25 02:32:57 PM PST 24
Peak memory 199296 kb
Host smart-987a31f4-8d33-4e60-867c-f43d518cede7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431748937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2431748937
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4023655025
Short name T69
Test name
Test status
Simulation time 350428332505 ps
CPU time 1026.78 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:50:05 PM PST 24
Peak memory 199664 kb
Host smart-233801af-0594-417c-b77c-4dc7369163b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023655025 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4023655025
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1990918244
Short name T454
Test name
Test status
Simulation time 753951939 ps
CPU time 0.96 seconds
Started Feb 25 02:32:54 PM PST 24
Finished Feb 25 02:32:55 PM PST 24
Peak memory 196608 kb
Host smart-3765f312-f35c-466a-a50d-a2a2756cc768
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990918244 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1990918244
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.2738027021
Short name T470
Test name
Test status
Simulation time 57364721621 ps
CPU time 429.12 seconds
Started Feb 25 02:32:52 PM PST 24
Finished Feb 25 02:40:01 PM PST 24
Peak memory 199616 kb
Host smart-81a71598-8b9e-4c96-974c-5636b4d877ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738027021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_sha_vectors.2738027021
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2735151971
Short name T19
Test name
Test status
Simulation time 12715906881 ps
CPU time 48.05 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:33:46 PM PST 24
Peak memory 199644 kb
Host smart-0716ece8-d15a-488b-8dd5-6aefd91c430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735151971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2735151971
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2725347484
Short name T552
Test name
Test status
Simulation time 40185546 ps
CPU time 0.57 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:32:59 PM PST 24
Peak memory 193764 kb
Host smart-f24684a0-e918-404b-9a45-5e11b663a538
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725347484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2725347484
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.870601833
Short name T260
Test name
Test status
Simulation time 1290646025 ps
CPU time 42.57 seconds
Started Feb 25 02:32:53 PM PST 24
Finished Feb 25 02:33:36 PM PST 24
Peak memory 215864 kb
Host smart-8dac8c4b-125a-4391-9415-5acb60a1ef5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870601833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.870601833
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.608328017
Short name T420
Test name
Test status
Simulation time 910736867 ps
CPU time 41.01 seconds
Started Feb 25 02:32:59 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 199508 kb
Host smart-79012193-ea41-463d-b94a-3b69581386ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608328017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.608328017
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3536031283
Short name T471
Test name
Test status
Simulation time 1565599004 ps
CPU time 40.91 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:33:39 PM PST 24
Peak memory 199520 kb
Host smart-7a24e1dd-1878-48f1-ad60-7e3213e128b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536031283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3536031283
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1625400003
Short name T418
Test name
Test status
Simulation time 8921846770 ps
CPU time 36.04 seconds
Started Feb 25 02:32:53 PM PST 24
Finished Feb 25 02:33:29 PM PST 24
Peak memory 199628 kb
Host smart-f65d7848-ab72-4d8c-853f-4954dc186544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625400003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1625400003
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3129205092
Short name T550
Test name
Test status
Simulation time 8718751767 ps
CPU time 28.3 seconds
Started Feb 25 02:32:51 PM PST 24
Finished Feb 25 02:33:20 PM PST 24
Peak memory 199628 kb
Host smart-9ea6be30-83e6-439f-b9b5-da2c99c0818c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129205092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3129205092
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1230261915
Short name T204
Test name
Test status
Simulation time 201620710 ps
CPU time 4.44 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:33:04 PM PST 24
Peak memory 199508 kb
Host smart-383d14b1-730b-43ae-9c97-4b7bae69f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230261915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1230261915
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.3253141436
Short name T281
Test name
Test status
Simulation time 8366204328 ps
CPU time 185.33 seconds
Started Feb 25 02:32:59 PM PST 24
Finished Feb 25 02:36:04 PM PST 24
Peak memory 199652 kb
Host smart-5334707f-e499-49d0-bab2-8ca10fd68e57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253141436 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.3253141436
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.76275503
Short name T401
Test name
Test status
Simulation time 36884727 ps
CPU time 0.91 seconds
Started Feb 25 02:32:52 PM PST 24
Finished Feb 25 02:32:54 PM PST 24
Peak memory 197084 kb
Host smart-3530027d-d3eb-45ef-8cdd-f375ab9c2f76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76275503 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.hmac_test_hmac_vectors.76275503
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3866515303
Short name T263
Test name
Test status
Simulation time 131146931107 ps
CPU time 420.55 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:40:01 PM PST 24
Peak memory 199600 kb
Host smart-115964f3-9884-4bef-a80e-fb69b258419f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866515303 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3866515303
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.233008670
Short name T539
Test name
Test status
Simulation time 4301036901 ps
CPU time 57.66 seconds
Started Feb 25 02:32:57 PM PST 24
Finished Feb 25 02:33:54 PM PST 24
Peak memory 199648 kb
Host smart-94b8d18a-6744-4a75-b78b-5470fb3763ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233008670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.233008670
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.665585299
Short name T355
Test name
Test status
Simulation time 12707429 ps
CPU time 0.57 seconds
Started Feb 25 02:32:56 PM PST 24
Finished Feb 25 02:32:56 PM PST 24
Peak memory 193980 kb
Host smart-f7c794bd-9514-4db2-bcd7-48cd5154eaff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665585299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.665585299
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2913050893
Short name T353
Test name
Test status
Simulation time 6958157718 ps
CPU time 54.49 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:33:54 PM PST 24
Peak memory 216060 kb
Host smart-9723b140-eddb-477f-8ed7-f25503e66cc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913050893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2913050893
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.420777100
Short name T215
Test name
Test status
Simulation time 73500261 ps
CPU time 3.26 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:33:01 PM PST 24
Peak memory 199472 kb
Host smart-5a7a86b4-5193-4c9f-91ba-c997a6625dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420777100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.420777100
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.4164279008
Short name T203
Test name
Test status
Simulation time 1484505696 ps
CPU time 40.09 seconds
Started Feb 25 02:32:55 PM PST 24
Finished Feb 25 02:33:36 PM PST 24
Peak memory 199540 kb
Host smart-031970d8-f069-4e45-b004-ef00b5afe963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164279008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.4164279008
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2383972012
Short name T157
Test name
Test status
Simulation time 37760099594 ps
CPU time 30.29 seconds
Started Feb 25 02:32:52 PM PST 24
Finished Feb 25 02:33:22 PM PST 24
Peak memory 199544 kb
Host smart-99881ff1-64c8-46de-8144-96ea03cb797d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383972012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2383972012
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1911758084
Short name T225
Test name
Test status
Simulation time 14686017828 ps
CPU time 106.35 seconds
Started Feb 25 02:32:51 PM PST 24
Finished Feb 25 02:34:37 PM PST 24
Peak memory 199800 kb
Host smart-70b76ae7-c0ce-400a-b731-cab85eeca800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911758084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1911758084
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1413887594
Short name T184
Test name
Test status
Simulation time 1072523214 ps
CPU time 4.04 seconds
Started Feb 25 02:32:58 PM PST 24
Finished Feb 25 02:33:02 PM PST 24
Peak memory 199528 kb
Host smart-ece6ecff-4e3b-41ba-8735-c4c9367312d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413887594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1413887594
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1114901456
Short name T405
Test name
Test status
Simulation time 18474485323 ps
CPU time 394.87 seconds
Started Feb 25 02:32:59 PM PST 24
Finished Feb 25 02:39:34 PM PST 24
Peak memory 223108 kb
Host smart-082dc229-31cc-47eb-b082-47965552307d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114901456 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1114901456
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1322342871
Short name T252
Test name
Test status
Simulation time 80174156 ps
CPU time 0.96 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:33:01 PM PST 24
Peak memory 197448 kb
Host smart-046afa06-5df7-40e9-898c-46d21a2b05a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322342871 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.1322342871
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.3440267019
Short name T231
Test name
Test status
Simulation time 179417442921 ps
CPU time 489.59 seconds
Started Feb 25 02:32:54 PM PST 24
Finished Feb 25 02:41:04 PM PST 24
Peak memory 199576 kb
Host smart-a362dabb-40b4-4c53-8832-12d51232103e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440267019 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.3440267019
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1326935456
Short name T581
Test name
Test status
Simulation time 94260164 ps
CPU time 2.08 seconds
Started Feb 25 02:32:55 PM PST 24
Finished Feb 25 02:32:58 PM PST 24
Peak memory 199528 kb
Host smart-a6e00516-81db-4d93-98ee-a6e8a8c4abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326935456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1326935456
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2351737011
Short name T414
Test name
Test status
Simulation time 23386760 ps
CPU time 0.56 seconds
Started Feb 25 02:33:09 PM PST 24
Finished Feb 25 02:33:10 PM PST 24
Peak memory 193760 kb
Host smart-51b4a2f5-d64f-47e4-a9f4-0adcebbb7c0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351737011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2351737011
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3248837129
Short name T351
Test name
Test status
Simulation time 291311628 ps
CPU time 3 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:33:11 PM PST 24
Peak memory 199448 kb
Host smart-eeb1b86d-72ab-4dff-91e6-96763e849ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248837129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3248837129
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1639333997
Short name T486
Test name
Test status
Simulation time 2243986074 ps
CPU time 38.72 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:33:47 PM PST 24
Peak memory 199628 kb
Host smart-61e1bc3e-bab5-4861-a8df-60cb49955448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639333997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1639333997
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.722411714
Short name T333
Test name
Test status
Simulation time 267588762 ps
CPU time 7.23 seconds
Started Feb 25 02:33:06 PM PST 24
Finished Feb 25 02:33:13 PM PST 24
Peak memory 199536 kb
Host smart-a2621769-df16-45c5-a899-19de2c362408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722411714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.722411714
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2729344188
Short name T42
Test name
Test status
Simulation time 1211924031 ps
CPU time 41.77 seconds
Started Feb 25 02:33:07 PM PST 24
Finished Feb 25 02:33:49 PM PST 24
Peak memory 199480 kb
Host smart-01ea1946-5697-4a8f-adcc-e360adc39043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729344188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2729344188
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4111582861
Short name T136
Test name
Test status
Simulation time 1048806963 ps
CPU time 19.16 seconds
Started Feb 25 02:33:10 PM PST 24
Finished Feb 25 02:33:29 PM PST 24
Peak memory 199472 kb
Host smart-e2c0ad52-6a40-436b-948d-eeac7bffe990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111582861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4111582861
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1462460553
Short name T31
Test name
Test status
Simulation time 181729078 ps
CPU time 2.14 seconds
Started Feb 25 02:33:00 PM PST 24
Finished Feb 25 02:33:02 PM PST 24
Peak memory 199416 kb
Host smart-00c6bd1e-0732-47d1-8920-e1c8e2e9464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462460553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1462460553
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2155141078
Short name T73
Test name
Test status
Simulation time 252602380246 ps
CPU time 863.21 seconds
Started Feb 25 02:33:07 PM PST 24
Finished Feb 25 02:47:30 PM PST 24
Peak memory 247084 kb
Host smart-1c9a5a4f-e36e-4fa4-9d0a-b3cd5e955325
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155141078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2155141078
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1116490398
Short name T296
Test name
Test status
Simulation time 216752163 ps
CPU time 1.2 seconds
Started Feb 25 02:33:06 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 198500 kb
Host smart-4b277b4a-4db6-4434-8e27-85027699e8fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116490398 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1116490398
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2918126147
Short name T303
Test name
Test status
Simulation time 28269441631 ps
CPU time 387.75 seconds
Started Feb 25 02:33:07 PM PST 24
Finished Feb 25 02:39:35 PM PST 24
Peak memory 199532 kb
Host smart-4e8a2d09-f04f-4794-af13-6e586fd92ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918126147 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.2918126147
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2973346377
Short name T196
Test name
Test status
Simulation time 1877985226 ps
CPU time 69.92 seconds
Started Feb 25 02:33:09 PM PST 24
Finished Feb 25 02:34:19 PM PST 24
Peak memory 199532 kb
Host smart-b4a0fd67-b7b3-4ca6-ba19-fd02219d1cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973346377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2973346377
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2921869458
Short name T522
Test name
Test status
Simulation time 16720460 ps
CPU time 0.6 seconds
Started Feb 25 02:33:07 PM PST 24
Finished Feb 25 02:33:08 PM PST 24
Peak memory 194776 kb
Host smart-df21f201-f485-44eb-99c5-55bbe8b2b91e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921869458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2921869458
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2487246193
Short name T292
Test name
Test status
Simulation time 2362183232 ps
CPU time 39.62 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:33:47 PM PST 24
Peak memory 227256 kb
Host smart-abe49f23-d8b2-4636-93c6-b317e76c2fec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2487246193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2487246193
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.141056564
Short name T63
Test name
Test status
Simulation time 1667209727 ps
CPU time 36.87 seconds
Started Feb 25 02:33:05 PM PST 24
Finished Feb 25 02:33:42 PM PST 24
Peak memory 199628 kb
Host smart-c3bc4251-1363-49bd-8b31-63523d0da10e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141056564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.141056564
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1330902119
Short name T97
Test name
Test status
Simulation time 871367614 ps
CPU time 11.15 seconds
Started Feb 25 02:33:09 PM PST 24
Finished Feb 25 02:33:21 PM PST 24
Peak memory 199536 kb
Host smart-5834db1f-214a-46da-b584-79f888620662
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330902119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1330902119
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3780096873
Short name T438
Test name
Test status
Simulation time 2443514066 ps
CPU time 62.35 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:34:10 PM PST 24
Peak memory 199652 kb
Host smart-2017e905-472e-4474-b7df-d18b9255bc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780096873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3780096873
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.420710575
Short name T570
Test name
Test status
Simulation time 1113171501 ps
CPU time 61.73 seconds
Started Feb 25 02:33:09 PM PST 24
Finished Feb 25 02:34:11 PM PST 24
Peak memory 199496 kb
Host smart-5c555589-732e-41aa-ae53-d957b2424025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420710575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.420710575
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2601985818
Short name T561
Test name
Test status
Simulation time 2213709720 ps
CPU time 3.11 seconds
Started Feb 25 02:33:06 PM PST 24
Finished Feb 25 02:33:09 PM PST 24
Peak memory 199612 kb
Host smart-b56cfb37-b6f9-4e6e-9773-6abb8aa7335f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601985818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2601985818
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.1766705107
Short name T554
Test name
Test status
Simulation time 38295232876 ps
CPU time 501.81 seconds
Started Feb 25 02:33:11 PM PST 24
Finished Feb 25 02:41:33 PM PST 24
Peak memory 237588 kb
Host smart-4d711dd4-727d-4afd-9f96-71ce6179c055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766705107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.1766705107
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_stress_all_with_rand_reset.2208119961
Short name T16
Test name
Test status
Simulation time 149469697099 ps
CPU time 1428.97 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:56:57 PM PST 24
Peak memory 240816 kb
Host smart-6a015c59-1a71-494c-9968-391a9ebb31a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2208119961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all_with_rand_reset.2208119961
Directory /workspace/25.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.161778315
Short name T275
Test name
Test status
Simulation time 310525928 ps
CPU time 1.23 seconds
Started Feb 25 02:33:10 PM PST 24
Finished Feb 25 02:33:12 PM PST 24
Peak memory 198292 kb
Host smart-52dd7ba8-6052-440b-847f-699280e6037d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161778315 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.161778315
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.258884846
Short name T442
Test name
Test status
Simulation time 43152112481 ps
CPU time 500.37 seconds
Started Feb 25 02:33:06 PM PST 24
Finished Feb 25 02:41:27 PM PST 24
Peak memory 199436 kb
Host smart-4885e53c-21f0-4ea4-80fc-bcf59d43081c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258884846 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 25.hmac_test_sha_vectors.258884846
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2621768175
Short name T238
Test name
Test status
Simulation time 4607250784 ps
CPU time 15.39 seconds
Started Feb 25 02:33:08 PM PST 24
Finished Feb 25 02:33:23 PM PST 24
Peak memory 199584 kb
Host smart-099733d0-53ce-4876-b2d7-0a5fc039f23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621768175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2621768175
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.24633182
Short name T448
Test name
Test status
Simulation time 18552143 ps
CPU time 0.58 seconds
Started Feb 25 02:33:14 PM PST 24
Finished Feb 25 02:33:14 PM PST 24
Peak memory 193744 kb
Host smart-c1f570d1-3cf7-400f-9fef-4b3bc5605d4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.24633182
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1851362137
Short name T129
Test name
Test status
Simulation time 1416151462 ps
CPU time 39.65 seconds
Started Feb 25 02:33:11 PM PST 24
Finished Feb 25 02:33:51 PM PST 24
Peak memory 215636 kb
Host smart-232b673a-c692-46e7-a694-3041d574b9f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851362137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1851362137
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3060179739
Short name T101
Test name
Test status
Simulation time 2045448676 ps
CPU time 53.45 seconds
Started Feb 25 02:33:12 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 199512 kb
Host smart-d944e08a-7483-4203-8209-ab61f716dc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060179739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3060179739
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4208977107
Short name T543
Test name
Test status
Simulation time 3218288637 ps
CPU time 84.01 seconds
Started Feb 25 02:33:17 PM PST 24
Finished Feb 25 02:34:41 PM PST 24
Peak memory 199612 kb
Host smart-5c015796-4934-4b6d-8672-0a693c5dc1c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4208977107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4208977107
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3339990779
Short name T12
Test name
Test status
Simulation time 7864366971 ps
CPU time 91.37 seconds
Started Feb 25 02:33:11 PM PST 24
Finished Feb 25 02:34:42 PM PST 24
Peak memory 199624 kb
Host smart-748a87ce-3601-47e0-888f-f3401f443085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339990779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3339990779
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1712999034
Short name T223
Test name
Test status
Simulation time 585923351 ps
CPU time 6.9 seconds
Started Feb 25 02:33:07 PM PST 24
Finished Feb 25 02:33:14 PM PST 24
Peak memory 199552 kb
Host smart-1994c29c-c07c-4711-8130-aae42baa608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712999034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1712999034
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.250330575
Short name T354
Test name
Test status
Simulation time 972620341 ps
CPU time 2.78 seconds
Started Feb 25 02:33:06 PM PST 24
Finished Feb 25 02:33:09 PM PST 24
Peak memory 199564 kb
Host smart-7659491d-97e2-40b3-b934-9908df872b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250330575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.250330575
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.4149344224
Short name T108
Test name
Test status
Simulation time 8246761856 ps
CPU time 372.51 seconds
Started Feb 25 02:33:17 PM PST 24
Finished Feb 25 02:39:30 PM PST 24
Peak memory 240432 kb
Host smart-1dd86e43-9985-4437-8e99-2a9f63f22bb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149344224 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.4149344224
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1977571661
Short name T259
Test name
Test status
Simulation time 49010980 ps
CPU time 0.97 seconds
Started Feb 25 02:33:13 PM PST 24
Finished Feb 25 02:33:14 PM PST 24
Peak memory 196876 kb
Host smart-52202c59-b95a-4503-aa93-8f071133b69e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977571661 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1977571661
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.377384398
Short name T400
Test name
Test status
Simulation time 62076399552 ps
CPU time 387.98 seconds
Started Feb 25 02:33:14 PM PST 24
Finished Feb 25 02:39:42 PM PST 24
Peak memory 199544 kb
Host smart-f345f45b-d0f9-4d96-bce8-112f16a04936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377384398 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.hmac_test_sha_vectors.377384398
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3560271274
Short name T436
Test name
Test status
Simulation time 369780511 ps
CPU time 5.54 seconds
Started Feb 25 02:33:15 PM PST 24
Finished Feb 25 02:33:21 PM PST 24
Peak memory 199580 kb
Host smart-04073d65-3541-4448-81cb-6006440836b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560271274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3560271274
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1302128581
Short name T430
Test name
Test status
Simulation time 20317865 ps
CPU time 0.58 seconds
Started Feb 25 02:33:15 PM PST 24
Finished Feb 25 02:33:16 PM PST 24
Peak memory 193752 kb
Host smart-9c4d9624-671c-4253-9936-ab4331e7d6b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302128581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1302128581
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3423515761
Short name T441
Test name
Test status
Simulation time 1375502918 ps
CPU time 44.52 seconds
Started Feb 25 02:33:15 PM PST 24
Finished Feb 25 02:34:00 PM PST 24
Peak memory 222260 kb
Host smart-e8183b2a-3302-4aa6-b827-de88540dfa50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3423515761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3423515761
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1400444355
Short name T578
Test name
Test status
Simulation time 615473417 ps
CPU time 29.15 seconds
Started Feb 25 02:33:10 PM PST 24
Finished Feb 25 02:33:39 PM PST 24
Peak memory 199516 kb
Host smart-49eed7fa-6577-4cb4-8bf2-383d497a5316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400444355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1400444355
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.2701566564
Short name T404
Test name
Test status
Simulation time 2284126812 ps
CPU time 124.17 seconds
Started Feb 25 02:33:13 PM PST 24
Finished Feb 25 02:35:17 PM PST 24
Peak memory 199624 kb
Host smart-37a5f834-1f8c-4bf0-936b-fca186e7ee20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701566564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.2701566564
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1773677651
Short name T160
Test name
Test status
Simulation time 126589787042 ps
CPU time 121.28 seconds
Started Feb 25 02:33:11 PM PST 24
Finished Feb 25 02:35:13 PM PST 24
Peak memory 199696 kb
Host smart-1bfafead-13b2-416a-bfea-bd703c105aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773677651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1773677651
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.308256283
Short name T118
Test name
Test status
Simulation time 11736901724 ps
CPU time 147.65 seconds
Started Feb 25 02:33:17 PM PST 24
Finished Feb 25 02:35:44 PM PST 24
Peak memory 199604 kb
Host smart-b48e5203-d24f-40e0-9253-4b807eb9d0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308256283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.308256283
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2895296095
Short name T435
Test name
Test status
Simulation time 315285156 ps
CPU time 4.37 seconds
Started Feb 25 02:33:12 PM PST 24
Finished Feb 25 02:33:17 PM PST 24
Peak memory 199352 kb
Host smart-1efa46ac-933e-4e6b-b7af-0ae9ea3328b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895296095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2895296095
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1861169406
Short name T490
Test name
Test status
Simulation time 44795164304 ps
CPU time 1217.12 seconds
Started Feb 25 02:33:16 PM PST 24
Finished Feb 25 02:53:33 PM PST 24
Peak memory 232436 kb
Host smart-ce534ce0-3f11-43dd-bafb-b7d878e9c2be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861169406 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1861169406
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1528464861
Short name T335
Test name
Test status
Simulation time 30192209 ps
CPU time 0.83 seconds
Started Feb 25 02:33:13 PM PST 24
Finished Feb 25 02:33:13 PM PST 24
Peak memory 197220 kb
Host smart-85e063d6-ec15-442c-a6ef-a95aa9760e5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528464861 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1528464861
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.119199107
Short name T314
Test name
Test status
Simulation time 55677288921 ps
CPU time 471.45 seconds
Started Feb 25 02:33:14 PM PST 24
Finished Feb 25 02:41:06 PM PST 24
Peak memory 199556 kb
Host smart-5cbaf5d4-e3ce-42e5-b842-c00d944e5658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119199107 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 27.hmac_test_sha_vectors.119199107
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1620746063
Short name T221
Test name
Test status
Simulation time 258623309 ps
CPU time 11.75 seconds
Started Feb 25 02:33:14 PM PST 24
Finished Feb 25 02:33:25 PM PST 24
Peak memory 199508 kb
Host smart-d4f08401-6384-43f2-bb22-e6267bbbe695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620746063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1620746063
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2025889677
Short name T535
Test name
Test status
Simulation time 15488592 ps
CPU time 0.56 seconds
Started Feb 25 02:33:22 PM PST 24
Finished Feb 25 02:33:23 PM PST 24
Peak memory 193752 kb
Host smart-b3b0081d-0fbf-4da6-a524-a8f9f8e03487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025889677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2025889677
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1088279309
Short name T363
Test name
Test status
Simulation time 1827360177 ps
CPU time 13.13 seconds
Started Feb 25 02:33:23 PM PST 24
Finished Feb 25 02:33:37 PM PST 24
Peak memory 199492 kb
Host smart-ebf4e22a-98f3-4032-b511-32d85826a3ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088279309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1088279309
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1759558647
Short name T327
Test name
Test status
Simulation time 436886638 ps
CPU time 6.58 seconds
Started Feb 25 02:33:23 PM PST 24
Finished Feb 25 02:33:29 PM PST 24
Peak memory 199484 kb
Host smart-e82538b5-3c40-4ee8-a161-bd98b8715948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759558647 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1759558647
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.2495025006
Short name T11
Test name
Test status
Simulation time 782472067 ps
CPU time 43.41 seconds
Started Feb 25 02:33:24 PM PST 24
Finished Feb 25 02:34:07 PM PST 24
Peak memory 199524 kb
Host smart-3450895a-8b2d-48aa-9f64-32503dd9f9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495025006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.2495025006
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.841573415
Short name T98
Test name
Test status
Simulation time 399102330 ps
CPU time 11.9 seconds
Started Feb 25 02:33:21 PM PST 24
Finished Feb 25 02:33:33 PM PST 24
Peak memory 199620 kb
Host smart-46da3bb6-d65a-4ef5-a256-30af7dd82fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841573415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.841573415
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2062817879
Short name T409
Test name
Test status
Simulation time 4622854324 ps
CPU time 81.06 seconds
Started Feb 25 02:33:27 PM PST 24
Finished Feb 25 02:34:48 PM PST 24
Peak memory 199628 kb
Host smart-9945fc53-929d-4269-bac5-df565ccc37c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062817879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2062817879
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1808475472
Short name T253
Test name
Test status
Simulation time 266596629 ps
CPU time 3.18 seconds
Started Feb 25 02:33:20 PM PST 24
Finished Feb 25 02:33:24 PM PST 24
Peak memory 199484 kb
Host smart-efac0d01-2018-4926-bfdd-07cedca4dc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808475472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1808475472
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1822195241
Short name T586
Test name
Test status
Simulation time 44615123 ps
CPU time 0.9 seconds
Started Feb 25 02:33:23 PM PST 24
Finished Feb 25 02:33:24 PM PST 24
Peak memory 197548 kb
Host smart-636f14a5-7424-4b90-9af2-0249f2730c17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822195241 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1822195241
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2674608554
Short name T302
Test name
Test status
Simulation time 75214616208 ps
CPU time 416.45 seconds
Started Feb 25 02:33:27 PM PST 24
Finished Feb 25 02:40:23 PM PST 24
Peak memory 199424 kb
Host smart-252db692-153a-4384-b4a9-45cd95be71e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674608554 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.2674608554
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_alert_test.436906605
Short name T478
Test name
Test status
Simulation time 24386955 ps
CPU time 0.58 seconds
Started Feb 25 02:33:30 PM PST 24
Finished Feb 25 02:33:31 PM PST 24
Peak memory 194780 kb
Host smart-c3b25bfb-cde4-4400-be13-f3fc468a2796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436906605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.436906605
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.3225949597
Short name T273
Test name
Test status
Simulation time 7671031049 ps
CPU time 18.01 seconds
Started Feb 25 02:33:23 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 207836 kb
Host smart-90386d63-3994-43b1-8253-3a60a6e34d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3225949597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.3225949597
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2014656724
Short name T495
Test name
Test status
Simulation time 12284087272 ps
CPU time 37.31 seconds
Started Feb 25 02:33:20 PM PST 24
Finished Feb 25 02:33:57 PM PST 24
Peak memory 199572 kb
Host smart-4b90bcfc-9769-4e06-b82b-295fee7b0068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014656724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2014656724
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.4121284515
Short name T120
Test name
Test status
Simulation time 4443048966 ps
CPU time 118.08 seconds
Started Feb 25 02:33:23 PM PST 24
Finished Feb 25 02:35:21 PM PST 24
Peak memory 199604 kb
Host smart-a93bc414-931e-4aa8-8606-d910b5e2cbb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121284515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.4121284515
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.347222866
Short name T362
Test name
Test status
Simulation time 39061489814 ps
CPU time 109.67 seconds
Started Feb 25 02:33:22 PM PST 24
Finished Feb 25 02:35:12 PM PST 24
Peak memory 199728 kb
Host smart-10ffec76-6008-4866-9350-70e5f2a523fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347222866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.347222866
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2393250902
Short name T371
Test name
Test status
Simulation time 6443414210 ps
CPU time 38.07 seconds
Started Feb 25 02:33:21 PM PST 24
Finished Feb 25 02:33:59 PM PST 24
Peak memory 199664 kb
Host smart-bfca7e35-b4df-4d75-a4c9-586c896580f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393250902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2393250902
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1397299169
Short name T229
Test name
Test status
Simulation time 114029713 ps
CPU time 1.62 seconds
Started Feb 25 02:33:24 PM PST 24
Finished Feb 25 02:33:26 PM PST 24
Peak memory 199484 kb
Host smart-a055f179-88b5-49f6-8a00-51d771254c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397299169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1397299169
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.2345374747
Short name T527
Test name
Test status
Simulation time 66411748653 ps
CPU time 778.05 seconds
Started Feb 25 02:33:25 PM PST 24
Finished Feb 25 02:46:24 PM PST 24
Peak memory 207884 kb
Host smart-1c5c95e2-244f-4600-9625-615704e74a40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345374747 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.2345374747
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.4251435380
Short name T226
Test name
Test status
Simulation time 56910264 ps
CPU time 1.02 seconds
Started Feb 25 02:33:27 PM PST 24
Finished Feb 25 02:33:28 PM PST 24
Peak memory 197468 kb
Host smart-3e8cbacc-188d-4190-a4d6-d12414714a08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251435380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.4251435380
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3898220706
Short name T340
Test name
Test status
Simulation time 102837097979 ps
CPU time 416.5 seconds
Started Feb 25 02:33:21 PM PST 24
Finished Feb 25 02:40:17 PM PST 24
Peak memory 199616 kb
Host smart-ff8bab57-4af3-479f-a26b-cedb26b1b4ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898220706 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.3898220706
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.4113177675
Short name T348
Test name
Test status
Simulation time 12267019599 ps
CPU time 49.3 seconds
Started Feb 25 02:33:22 PM PST 24
Finished Feb 25 02:34:11 PM PST 24
Peak memory 199656 kb
Host smart-14d7a403-422b-4556-8b71-af512bc83972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113177675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.4113177675
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2715602952
Short name T445
Test name
Test status
Simulation time 16653347 ps
CPU time 0.6 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:31:34 PM PST 24
Peak memory 193744 kb
Host smart-0e557aaa-8d37-4132-b8ab-9b962afdfdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715602952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2715602952
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.78365527
Short name T520
Test name
Test status
Simulation time 20222388534 ps
CPU time 44.71 seconds
Started Feb 25 02:31:22 PM PST 24
Finished Feb 25 02:32:07 PM PST 24
Peak memory 204752 kb
Host smart-f7fb72c1-914a-4220-8fd4-2f51a2d9536c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=78365527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.78365527
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3773957517
Short name T110
Test name
Test status
Simulation time 822611782 ps
CPU time 38.5 seconds
Started Feb 25 02:31:24 PM PST 24
Finished Feb 25 02:32:03 PM PST 24
Peak memory 199528 kb
Host smart-548deeb0-dd96-40c3-a045-9b4816a84c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773957517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3773957517
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1348518823
Short name T105
Test name
Test status
Simulation time 2184048220 ps
CPU time 58.92 seconds
Started Feb 25 02:31:22 PM PST 24
Finished Feb 25 02:32:21 PM PST 24
Peak memory 199640 kb
Host smart-d217d8c9-9dd0-4a70-83e8-7434de2708f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348518823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1348518823
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_long_msg.265000897
Short name T182
Test name
Test status
Simulation time 198988405 ps
CPU time 10.59 seconds
Started Feb 25 02:31:26 PM PST 24
Finished Feb 25 02:31:36 PM PST 24
Peak memory 199504 kb
Host smart-507a59cf-5e0d-4866-a597-24573b84cbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265000897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.265000897
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.371304615
Short name T38
Test name
Test status
Simulation time 376246839 ps
CPU time 0.99 seconds
Started Feb 25 02:31:36 PM PST 24
Finished Feb 25 02:31:38 PM PST 24
Peak memory 217704 kb
Host smart-5f9e808d-5f24-4cf1-b28d-7e6bf8d25afc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371304615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.371304615
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.4216295144
Short name T589
Test name
Test status
Simulation time 113669432 ps
CPU time 1.4 seconds
Started Feb 25 02:31:28 PM PST 24
Finished Feb 25 02:31:29 PM PST 24
Peak memory 199516 kb
Host smart-5f386862-b6e9-4b3c-a9f7-e7de63326c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216295144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.4216295144
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.840376549
Short name T126
Test name
Test status
Simulation time 74794864442 ps
CPU time 318.55 seconds
Started Feb 25 02:31:36 PM PST 24
Finished Feb 25 02:36:54 PM PST 24
Peak memory 211568 kb
Host smart-367d0a50-d63a-4484-b2f7-2b0dc3614d18
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840376549 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.840376549
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1100938949
Short name T528
Test name
Test status
Simulation time 95545979 ps
CPU time 0.92 seconds
Started Feb 25 02:31:32 PM PST 24
Finished Feb 25 02:31:33 PM PST 24
Peak memory 197352 kb
Host smart-5f0ed216-d53c-45de-a8fb-430fc365d5d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100938949 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.1100938949
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.2850139437
Short name T474
Test name
Test status
Simulation time 147124553128 ps
CPU time 413.11 seconds
Started Feb 25 02:31:31 PM PST 24
Finished Feb 25 02:38:25 PM PST 24
Peak memory 199536 kb
Host smart-cb3143d6-2c18-458e-a77a-182be084efca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850139437 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.2850139437
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.763937829
Short name T407
Test name
Test status
Simulation time 4342122728 ps
CPU time 40.23 seconds
Started Feb 25 02:31:24 PM PST 24
Finished Feb 25 02:32:05 PM PST 24
Peak memory 199596 kb
Host smart-d746b3bb-cab8-495f-8582-48aa98ffa4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763937829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.763937829
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.1874327367
Short name T588
Test name
Test status
Simulation time 11558819 ps
CPU time 0.56 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:33:32 PM PST 24
Peak memory 193944 kb
Host smart-9ba3935e-f365-4175-8d5f-801418ee7856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874327367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.1874327367
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.1685977776
Short name T188
Test name
Test status
Simulation time 5030667289 ps
CPU time 28.27 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:34:00 PM PST 24
Peak memory 199664 kb
Host smart-7b0a0c4f-bd47-40b4-9ea8-8975e33087eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685977776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.1685977776
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.771393109
Short name T576
Test name
Test status
Simulation time 3692578373 ps
CPU time 33.56 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:34:05 PM PST 24
Peak memory 199624 kb
Host smart-0f5256db-fbcb-4355-84f3-658ed3447154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771393109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.771393109
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2340620192
Short name T62
Test name
Test status
Simulation time 219122635 ps
CPU time 12.21 seconds
Started Feb 25 02:33:32 PM PST 24
Finished Feb 25 02:33:44 PM PST 24
Peak memory 199504 kb
Host smart-b19452b9-8683-442c-b0e4-2a6e370274c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2340620192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2340620192
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1935814757
Short name T373
Test name
Test status
Simulation time 3929395642 ps
CPU time 195.51 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:36:47 PM PST 24
Peak memory 199628 kb
Host smart-07e44abb-4111-47b5-8180-790a40e785f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935814757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1935814757
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2780132487
Short name T413
Test name
Test status
Simulation time 10032401182 ps
CPU time 59.43 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:34:30 PM PST 24
Peak memory 199708 kb
Host smart-5a18d068-f99f-4ade-aead-216660a83288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780132487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2780132487
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3415296892
Short name T211
Test name
Test status
Simulation time 102835997 ps
CPU time 1.72 seconds
Started Feb 25 02:33:34 PM PST 24
Finished Feb 25 02:33:36 PM PST 24
Peak memory 199492 kb
Host smart-07630b27-b4ee-411b-b730-0d665ab7ba2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415296892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3415296892
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3802179182
Short name T573
Test name
Test status
Simulation time 66699755519 ps
CPU time 1688.74 seconds
Started Feb 25 02:33:38 PM PST 24
Finished Feb 25 03:01:47 PM PST 24
Peak memory 221132 kb
Host smart-614d67df-f743-4362-91b2-98fb2245ce17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802179182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3802179182
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3879196644
Short name T278
Test name
Test status
Simulation time 108560171 ps
CPU time 0.93 seconds
Started Feb 25 02:33:33 PM PST 24
Finished Feb 25 02:33:35 PM PST 24
Peak memory 196796 kb
Host smart-9b2f8f35-954f-4df1-b731-79d4d5b9f298
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879196644 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3879196644
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1628686680
Short name T313
Test name
Test status
Simulation time 8011056173 ps
CPU time 401.22 seconds
Started Feb 25 02:33:30 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 199580 kb
Host smart-b98d6f2f-a991-42e7-ba92-ea77bf881cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628686680 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1628686680
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.192579420
Short name T402
Test name
Test status
Simulation time 2373502966 ps
CPU time 22.13 seconds
Started Feb 25 02:33:33 PM PST 24
Finished Feb 25 02:33:55 PM PST 24
Peak memory 199640 kb
Host smart-c919c4eb-3182-4afe-828c-b4a6295310d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192579420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.192579420
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.1438337309
Short name T291
Test name
Test status
Simulation time 39833847 ps
CPU time 0.56 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:33:31 PM PST 24
Peak memory 193708 kb
Host smart-aeaf628e-bd8d-49c3-8c00-3cc6f203d1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438337309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.1438337309
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2296136341
Short name T138
Test name
Test status
Simulation time 2991657031 ps
CPU time 10.58 seconds
Started Feb 25 02:33:32 PM PST 24
Finished Feb 25 02:33:42 PM PST 24
Peak memory 207828 kb
Host smart-b7c00816-8659-4150-965a-8e2d126242df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296136341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2296136341
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2828573797
Short name T241
Test name
Test status
Simulation time 2575978547 ps
CPU time 34.4 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 199620 kb
Host smart-ec5ed9cb-94ef-492c-b53a-2351ec13cf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828573797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2828573797
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.347728206
Short name T356
Test name
Test status
Simulation time 765455913 ps
CPU time 39.53 seconds
Started Feb 25 02:33:35 PM PST 24
Finished Feb 25 02:34:15 PM PST 24
Peak memory 199580 kb
Host smart-e333d228-0cfa-4a69-bddf-baaf0932cae5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=347728206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.347728206
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.701333147
Short name T249
Test name
Test status
Simulation time 16171363256 ps
CPU time 139.11 seconds
Started Feb 25 02:33:32 PM PST 24
Finished Feb 25 02:35:51 PM PST 24
Peak memory 199732 kb
Host smart-5248c4bb-8004-49b6-bb4b-7e8588677bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701333147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.701333147
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1695798897
Short name T460
Test name
Test status
Simulation time 122571177 ps
CPU time 6.52 seconds
Started Feb 25 02:33:34 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 199556 kb
Host smart-f9999790-3cb3-4a7d-bf52-6b074ff87579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695798897 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1695798897
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2379057709
Short name T236
Test name
Test status
Simulation time 145512935 ps
CPU time 2.27 seconds
Started Feb 25 02:33:36 PM PST 24
Finished Feb 25 02:33:39 PM PST 24
Peak memory 199500 kb
Host smart-3de57117-89b0-4708-829e-ea246796150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379057709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2379057709
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1719008345
Short name T116
Test name
Test status
Simulation time 174037426644 ps
CPU time 741.37 seconds
Started Feb 25 02:33:30 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 225252 kb
Host smart-91533bf8-2911-462d-98f5-003bebc4cc78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719008345 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1719008345
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3891840506
Short name T307
Test name
Test status
Simulation time 60845974 ps
CPU time 1.06 seconds
Started Feb 25 02:33:38 PM PST 24
Finished Feb 25 02:33:39 PM PST 24
Peak memory 197084 kb
Host smart-c9aa18d7-b32a-4759-8035-4f75aef057b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891840506 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3891840506
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.1570688156
Short name T433
Test name
Test status
Simulation time 28301801834 ps
CPU time 462.97 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:41:14 PM PST 24
Peak memory 199644 kb
Host smart-2dd55ff7-ad05-4833-841e-bd4be70ddfd2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570688156 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_sha_vectors.1570688156
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4112189120
Short name T377
Test name
Test status
Simulation time 1019617233 ps
CPU time 18.22 seconds
Started Feb 25 02:33:33 PM PST 24
Finished Feb 25 02:33:52 PM PST 24
Peak memory 199544 kb
Host smart-c60a7be6-0628-42b0-b638-c7028846cc62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112189120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4112189120
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3999670263
Short name T228
Test name
Test status
Simulation time 27162446 ps
CPU time 0.61 seconds
Started Feb 25 02:33:46 PM PST 24
Finished Feb 25 02:33:47 PM PST 24
Peak memory 193868 kb
Host smart-4268d141-64e9-449a-8c07-e5210378a6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999670263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3999670263
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.875515035
Short name T26
Test name
Test status
Simulation time 1302975060 ps
CPU time 10.86 seconds
Started Feb 25 02:33:35 PM PST 24
Finished Feb 25 02:33:46 PM PST 24
Peak memory 199496 kb
Host smart-eb3790d5-8ad7-41d1-9b83-7424414a3fc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=875515035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.875515035
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.554106317
Short name T544
Test name
Test status
Simulation time 9664836617 ps
CPU time 9.14 seconds
Started Feb 25 02:33:34 PM PST 24
Finished Feb 25 02:33:44 PM PST 24
Peak memory 199632 kb
Host smart-750d8471-5079-416a-9db2-fda2ba631d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554106317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.554106317
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.4105693186
Short name T239
Test name
Test status
Simulation time 2039083289 ps
CPU time 31.19 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:34:02 PM PST 24
Peak memory 199520 kb
Host smart-10c51ccc-1e65-428b-ab48-6b74410aa927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4105693186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.4105693186
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.1681836847
Short name T571
Test name
Test status
Simulation time 1610386097 ps
CPU time 43.28 seconds
Started Feb 25 02:33:36 PM PST 24
Finished Feb 25 02:34:19 PM PST 24
Peak memory 199544 kb
Host smart-edcc497e-e60f-466e-ae12-3c9fc65753e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681836847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.1681836847
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.315661045
Short name T507
Test name
Test status
Simulation time 6518744921 ps
CPU time 106.89 seconds
Started Feb 25 02:33:32 PM PST 24
Finished Feb 25 02:35:19 PM PST 24
Peak memory 199668 kb
Host smart-83a78ff7-0b8e-492f-b731-6995e4cf1a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315661045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.315661045
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2783417328
Short name T504
Test name
Test status
Simulation time 43537436 ps
CPU time 1.42 seconds
Started Feb 25 02:33:31 PM PST 24
Finished Feb 25 02:33:32 PM PST 24
Peak memory 199256 kb
Host smart-c2fc94a6-0a80-49ae-913e-c4c31135e308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783417328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2783417328
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.199016541
Short name T133
Test name
Test status
Simulation time 184108480520 ps
CPU time 820.41 seconds
Started Feb 25 02:33:41 PM PST 24
Finished Feb 25 02:47:21 PM PST 24
Peak memory 247944 kb
Host smart-4e8b566b-f745-4af6-aaa0-a854cc2f8c4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199016541 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.199016541
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.2715428531
Short name T64
Test name
Test status
Simulation time 27996662 ps
CPU time 0.91 seconds
Started Feb 25 02:33:43 PM PST 24
Finished Feb 25 02:33:45 PM PST 24
Peak memory 196808 kb
Host smart-5f6273d9-204c-4c12-bee3-ec7102d667c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715428531 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.2715428531
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.974893699
Short name T521
Test name
Test status
Simulation time 140778115385 ps
CPU time 396.92 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:40:16 PM PST 24
Peak memory 199584 kb
Host smart-5c1e62c8-ffbc-4085-8ebe-bcacd421c098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974893699 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_sha_vectors.974893699
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.399076955
Short name T295
Test name
Test status
Simulation time 1856582935 ps
CPU time 7.33 seconds
Started Feb 25 02:33:42 PM PST 24
Finished Feb 25 02:33:50 PM PST 24
Peak memory 199500 kb
Host smart-e2e721e2-6393-412a-a1e9-08a097303f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399076955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.399076955
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1306010038
Short name T300
Test name
Test status
Simulation time 125099987 ps
CPU time 0.56 seconds
Started Feb 25 02:33:41 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 193752 kb
Host smart-e949ca85-f6de-4460-85ed-5e4d7bc13c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306010038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1306010038
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.2444005286
Short name T24
Test name
Test status
Simulation time 4460938058 ps
CPU time 15.32 seconds
Started Feb 25 02:33:46 PM PST 24
Finished Feb 25 02:34:01 PM PST 24
Peak memory 214604 kb
Host smart-13fe3548-b6da-438b-94e8-47f523507f9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2444005286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.2444005286
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.4016992861
Short name T515
Test name
Test status
Simulation time 42647995 ps
CPU time 1.94 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 199560 kb
Host smart-8239e312-7f1b-4c72-b4eb-1a311e6b6610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016992861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.4016992861
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1812389039
Short name T304
Test name
Test status
Simulation time 132002922 ps
CPU time 1.86 seconds
Started Feb 25 02:33:40 PM PST 24
Finished Feb 25 02:33:42 PM PST 24
Peak memory 199456 kb
Host smart-cd8ca485-5217-4275-8165-0cd926b30be5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812389039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1812389039
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1475709847
Short name T516
Test name
Test status
Simulation time 8452110936 ps
CPU time 103.62 seconds
Started Feb 25 02:33:43 PM PST 24
Finished Feb 25 02:35:27 PM PST 24
Peak memory 199612 kb
Host smart-b9dcd317-c7aa-4c1f-9a44-538dbeed5b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475709847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1475709847
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.785542217
Short name T459
Test name
Test status
Simulation time 230327174 ps
CPU time 3.52 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:33:43 PM PST 24
Peak memory 199448 kb
Host smart-d8ee8f04-75ba-4d35-8f53-7aeb5a874005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785542217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.785542217
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3036333502
Short name T282
Test name
Test status
Simulation time 816761217 ps
CPU time 4.35 seconds
Started Feb 25 02:33:43 PM PST 24
Finished Feb 25 02:33:48 PM PST 24
Peak memory 199532 kb
Host smart-1d88a311-9b58-483c-bb7b-a09e80c16a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036333502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3036333502
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.938503802
Short name T434
Test name
Test status
Simulation time 22910813368 ps
CPU time 1107.79 seconds
Started Feb 25 02:33:42 PM PST 24
Finished Feb 25 02:52:10 PM PST 24
Peak memory 231820 kb
Host smart-cfc94270-4579-4b88-9832-1f72ea9c30c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938503802 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.938503802
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3495946078
Short name T369
Test name
Test status
Simulation time 71076650 ps
CPU time 1.33 seconds
Started Feb 25 02:33:47 PM PST 24
Finished Feb 25 02:33:49 PM PST 24
Peak memory 198448 kb
Host smart-a16a0f97-31ed-4e14-abf7-aecff7147841
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495946078 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.3495946078
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2355279582
Short name T519
Test name
Test status
Simulation time 27546415160 ps
CPU time 464.1 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:41:24 PM PST 24
Peak memory 199548 kb
Host smart-9f856d70-6bcd-47b3-8ad9-8ce4a92ab219
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355279582 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.hmac_test_sha_vectors.2355279582
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.9309244
Short name T269
Test name
Test status
Simulation time 31567489255 ps
CPU time 66.05 seconds
Started Feb 25 02:33:42 PM PST 24
Finished Feb 25 02:34:48 PM PST 24
Peak memory 199636 kb
Host smart-a07ec700-67eb-44e5-bd76-61ff4683ba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9309244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.9309244
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3973044535
Short name T582
Test name
Test status
Simulation time 12909690 ps
CPU time 0.57 seconds
Started Feb 25 02:33:44 PM PST 24
Finished Feb 25 02:33:45 PM PST 24
Peak memory 193952 kb
Host smart-2db17cbf-c224-4e3e-8609-3cffe5a11f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973044535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3973044535
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.3506816376
Short name T456
Test name
Test status
Simulation time 1252687141 ps
CPU time 50.98 seconds
Started Feb 25 02:33:43 PM PST 24
Finished Feb 25 02:34:34 PM PST 24
Peak memory 232356 kb
Host smart-14e776be-aef3-42ae-b148-b9367ac5df68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3506816376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.3506816376
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.909680785
Short name T463
Test name
Test status
Simulation time 9247136082 ps
CPU time 33.51 seconds
Started Feb 25 02:33:47 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 199760 kb
Host smart-05102f30-6545-409e-9b5c-cf54a0f9870f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909680785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.909680785
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.2512688785
Short name T406
Test name
Test status
Simulation time 880495612 ps
CPU time 46.92 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:34:26 PM PST 24
Peak memory 199564 kb
Host smart-f9cfcd4c-1c02-4b5d-b66c-b0acedc3f84d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2512688785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.2512688785
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1417103781
Short name T564
Test name
Test status
Simulation time 2583550375 ps
CPU time 59.15 seconds
Started Feb 25 02:33:40 PM PST 24
Finished Feb 25 02:34:40 PM PST 24
Peak memory 199592 kb
Host smart-0772236a-c898-48ce-9aae-f1ca1cc6b3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417103781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1417103781
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3962222666
Short name T10
Test name
Test status
Simulation time 1849704696 ps
CPU time 91.1 seconds
Started Feb 25 02:33:37 PM PST 24
Finished Feb 25 02:35:08 PM PST 24
Peak memory 199528 kb
Host smart-aa04da2b-3160-4d0f-b3c0-3ffb63184cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962222666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3962222666
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.1601923038
Short name T556
Test name
Test status
Simulation time 355421903 ps
CPU time 1.12 seconds
Started Feb 25 02:33:40 PM PST 24
Finished Feb 25 02:33:41 PM PST 24
Peak memory 198684 kb
Host smart-6aa19d18-4cc8-4303-aa2e-6ccf3b80583b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601923038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.1601923038
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.534064929
Short name T74
Test name
Test status
Simulation time 356537111854 ps
CPU time 1321.84 seconds
Started Feb 25 02:33:44 PM PST 24
Finished Feb 25 02:55:46 PM PST 24
Peak memory 236568 kb
Host smart-03ac5e10-0bdc-4566-98e5-3dbdfa1b60f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534064929 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.534064929
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2725980872
Short name T235
Test name
Test status
Simulation time 54020464 ps
CPU time 1.07 seconds
Started Feb 25 02:33:42 PM PST 24
Finished Feb 25 02:33:43 PM PST 24
Peak memory 198128 kb
Host smart-55a28277-6284-4177-b9dd-77ed2ed36ae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725980872 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2725980872
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2758781354
Short name T220
Test name
Test status
Simulation time 58344303617 ps
CPU time 464.83 seconds
Started Feb 25 02:33:41 PM PST 24
Finished Feb 25 02:41:26 PM PST 24
Peak memory 199612 kb
Host smart-209f9c7a-5a10-4ac5-a444-371822350c39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758781354 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.hmac_test_sha_vectors.2758781354
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.480918990
Short name T1
Test name
Test status
Simulation time 7935199247 ps
CPU time 76.58 seconds
Started Feb 25 02:33:42 PM PST 24
Finished Feb 25 02:34:59 PM PST 24
Peak memory 199568 kb
Host smart-9f7ec5e5-183c-4050-8248-deb1005b34ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480918990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.480918990
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2197154432
Short name T35
Test name
Test status
Simulation time 13636460 ps
CPU time 0.56 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:34:01 PM PST 24
Peak memory 193760 kb
Host smart-c57de666-0cf7-4b70-9c1c-f21db4fcc585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197154432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2197154432
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4015574611
Short name T518
Test name
Test status
Simulation time 1475941026 ps
CPU time 48.47 seconds
Started Feb 25 02:33:46 PM PST 24
Finished Feb 25 02:34:35 PM PST 24
Peak memory 215668 kb
Host smart-937502c6-bcec-441c-bc30-9dc0e51ed6bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4015574611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4015574611
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1523970293
Short name T170
Test name
Test status
Simulation time 2645998653 ps
CPU time 29.8 seconds
Started Feb 25 02:33:54 PM PST 24
Finished Feb 25 02:34:24 PM PST 24
Peak memory 199616 kb
Host smart-915c3058-d7d4-43d0-801c-7ca2fe07ba9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523970293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1523970293
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2430450938
Short name T187
Test name
Test status
Simulation time 341752907 ps
CPU time 16.49 seconds
Started Feb 25 02:34:03 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 199572 kb
Host smart-265cbe18-0c0a-4e7b-88a5-e15da5574b59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2430450938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2430450938
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.143467695
Short name T529
Test name
Test status
Simulation time 7293106042 ps
CPU time 100.86 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:35:41 PM PST 24
Peak memory 199868 kb
Host smart-6077028e-276b-41e8-be35-49a2bd809996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143467695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.143467695
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3381102227
Short name T421
Test name
Test status
Simulation time 3036800568 ps
CPU time 45.77 seconds
Started Feb 25 02:33:43 PM PST 24
Finished Feb 25 02:34:29 PM PST 24
Peak memory 199640 kb
Host smart-bd4b1431-e246-446d-8038-bc9dda77b76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381102227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3381102227
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.1582000121
Short name T227
Test name
Test status
Simulation time 636205682 ps
CPU time 3.19 seconds
Started Feb 25 02:33:39 PM PST 24
Finished Feb 25 02:33:43 PM PST 24
Peak memory 199504 kb
Host smart-38d6db61-3200-4363-a956-256982387552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582000121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.1582000121
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.2087137323
Short name T346
Test name
Test status
Simulation time 71804520 ps
CPU time 1.19 seconds
Started Feb 25 02:33:53 PM PST 24
Finished Feb 25 02:33:54 PM PST 24
Peak memory 198040 kb
Host smart-c8a13c36-16ea-4a6b-99c0-b7ee4568f8de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087137323 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.2087137323
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.756228079
Short name T156
Test name
Test status
Simulation time 56024014 ps
CPU time 1.18 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:34:02 PM PST 24
Peak memory 199492 kb
Host smart-148d6815-5b19-480f-a258-54dbc836e0a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756228079 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.756228079
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.398222333
Short name T315
Test name
Test status
Simulation time 117283933 ps
CPU time 3.19 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:33:58 PM PST 24
Peak memory 199532 kb
Host smart-dd5643fb-f7cf-4f24-8be4-671918864036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398222333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.398222333
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.642758333
Short name T267
Test name
Test status
Simulation time 18075689 ps
CPU time 0.56 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:33:56 PM PST 24
Peak memory 193780 kb
Host smart-e3ff1a53-416d-47df-ad3f-2e4840f20a80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642758333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.642758333
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1144321505
Short name T106
Test name
Test status
Simulation time 699000755 ps
CPU time 25.94 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:34:21 PM PST 24
Peak memory 222044 kb
Host smart-ff8dcfe9-ba51-49f1-ac37-355043e18d54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1144321505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1144321505
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1489054000
Short name T449
Test name
Test status
Simulation time 1417701214 ps
CPU time 67.52 seconds
Started Feb 25 02:34:01 PM PST 24
Finished Feb 25 02:35:10 PM PST 24
Peak memory 199424 kb
Host smart-661f1d78-cc18-48c0-8a73-5f48c8b47397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489054000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1489054000
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_error.2774365390
Short name T243
Test name
Test status
Simulation time 15063805340 ps
CPU time 133.59 seconds
Started Feb 25 02:33:57 PM PST 24
Finished Feb 25 02:36:11 PM PST 24
Peak memory 199652 kb
Host smart-409850b8-f20b-487b-b2b3-2fa9db4f8f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774365390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2774365390
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2600046923
Short name T151
Test name
Test status
Simulation time 675143043 ps
CPU time 34.02 seconds
Started Feb 25 02:33:59 PM PST 24
Finished Feb 25 02:34:33 PM PST 24
Peak memory 199524 kb
Host smart-f9953ca2-cb91-43f2-8800-ba04ea259989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600046923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2600046923
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.738468922
Short name T192
Test name
Test status
Simulation time 139537703 ps
CPU time 0.78 seconds
Started Feb 25 02:33:53 PM PST 24
Finished Feb 25 02:33:54 PM PST 24
Peak memory 196744 kb
Host smart-bca1b625-0c56-48ef-a472-662d4de645c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738468922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.738468922
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3866230677
Short name T71
Test name
Test status
Simulation time 48869159259 ps
CPU time 302 seconds
Started Feb 25 02:33:57 PM PST 24
Finished Feb 25 02:38:59 PM PST 24
Peak memory 215124 kb
Host smart-d43789f1-f6f8-4639-80ca-95df9a5fd6e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866230677 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3866230677
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3695862441
Short name T242
Test name
Test status
Simulation time 33522524 ps
CPU time 1.08 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:34:01 PM PST 24
Peak memory 198552 kb
Host smart-3eed39d3-b6fd-4f6f-93e8-59f1938afcb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695862441 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3695862441
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.256706880
Short name T487
Test name
Test status
Simulation time 31800281426 ps
CPU time 472.47 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:41:47 PM PST 24
Peak memory 199552 kb
Host smart-81c15515-1e03-4edf-ab28-1d63d002909b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256706880 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.hmac_test_sha_vectors.256706880
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3234747797
Short name T547
Test name
Test status
Simulation time 25990085518 ps
CPU time 81.23 seconds
Started Feb 25 02:33:53 PM PST 24
Finished Feb 25 02:35:14 PM PST 24
Peak memory 199648 kb
Host smart-1e54c928-5aec-4554-b4b4-dba728c47d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234747797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3234747797
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.3839867235
Short name T427
Test name
Test status
Simulation time 80247214 ps
CPU time 0.63 seconds
Started Feb 25 02:34:05 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 193960 kb
Host smart-ff06d1e7-5c8e-487f-8e14-294034592c1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839867235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.3839867235
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3519628994
Short name T21
Test name
Test status
Simulation time 1020780257 ps
CPU time 36.34 seconds
Started Feb 25 02:33:56 PM PST 24
Finished Feb 25 02:34:32 PM PST 24
Peak memory 232284 kb
Host smart-77b56d82-0802-48a6-9c9a-92707d0041fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3519628994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3519628994
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1056673440
Short name T417
Test name
Test status
Simulation time 5508878648 ps
CPU time 30.28 seconds
Started Feb 25 02:34:02 PM PST 24
Finished Feb 25 02:34:33 PM PST 24
Peak memory 199636 kb
Host smart-22c12b8f-614a-4716-be35-29e67a885401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056673440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1056673440
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.3374567233
Short name T514
Test name
Test status
Simulation time 2337369594 ps
CPU time 61.79 seconds
Started Feb 25 02:33:58 PM PST 24
Finished Feb 25 02:35:00 PM PST 24
Peak memory 199624 kb
Host smart-b4525c31-91b7-4f3d-bd2b-c4bd7d79460e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3374567233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.3374567233
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2468117706
Short name T492
Test name
Test status
Simulation time 12161781611 ps
CPU time 70.7 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:35:06 PM PST 24
Peak memory 199596 kb
Host smart-40227ede-9c7b-4dc0-bbce-d8d1655e7a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468117706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2468117706
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3466228125
Short name T555
Test name
Test status
Simulation time 1802937337 ps
CPU time 16.25 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:34:17 PM PST 24
Peak memory 199532 kb
Host smart-d2d701ce-67e2-42f5-9c61-9ebe5e0a5994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466228125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3466228125
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1464806547
Short name T177
Test name
Test status
Simulation time 668354291 ps
CPU time 3.74 seconds
Started Feb 25 02:34:01 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 199444 kb
Host smart-cae97866-6ae7-4cb0-aa9d-45565338b98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464806547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1464806547
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.437713012
Short name T68
Test name
Test status
Simulation time 78069921807 ps
CPU time 1012.82 seconds
Started Feb 25 02:34:06 PM PST 24
Finished Feb 25 02:50:59 PM PST 24
Peak memory 199680 kb
Host smart-11ab6368-ee94-4c34-9c32-a7c395670fad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437713012 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.437713012
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.4117478863
Short name T217
Test name
Test status
Simulation time 137155511 ps
CPU time 0.94 seconds
Started Feb 25 02:34:00 PM PST 24
Finished Feb 25 02:34:02 PM PST 24
Peak memory 196860 kb
Host smart-bd317e1d-6761-478c-86db-35ad24d708dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117478863 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.4117478863
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2957628829
Short name T488
Test name
Test status
Simulation time 34863346355 ps
CPU time 423.37 seconds
Started Feb 25 02:33:55 PM PST 24
Finished Feb 25 02:40:59 PM PST 24
Peak memory 199544 kb
Host smart-b4471595-1c52-4303-a6ea-3e9950f00122
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957628829 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.2957628829
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.4167696241
Short name T257
Test name
Test status
Simulation time 1337843648 ps
CPU time 18.03 seconds
Started Feb 25 02:34:01 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 199436 kb
Host smart-2f87975b-c1d8-4de4-ac4c-f9ac06cfde59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167696241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.4167696241
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.846942509
Short name T320
Test name
Test status
Simulation time 13776016 ps
CPU time 0.56 seconds
Started Feb 25 02:34:04 PM PST 24
Finished Feb 25 02:34:05 PM PST 24
Peak memory 194776 kb
Host smart-0f850d30-178f-447b-8af7-1d0af671e3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846942509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.846942509
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2018339516
Short name T423
Test name
Test status
Simulation time 11478377716 ps
CPU time 46.74 seconds
Started Feb 25 02:34:05 PM PST 24
Finished Feb 25 02:34:52 PM PST 24
Peak memory 232288 kb
Host smart-15cd560f-bf4e-4565-9fc8-80c4b92ff518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2018339516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2018339516
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.3250917993
Short name T125
Test name
Test status
Simulation time 3382453886 ps
CPU time 52.93 seconds
Started Feb 25 02:34:03 PM PST 24
Finished Feb 25 02:34:56 PM PST 24
Peak memory 199616 kb
Host smart-a3ad7224-9201-480c-bf01-9b6571944b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250917993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.3250917993
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3424192533
Short name T112
Test name
Test status
Simulation time 5164547637 ps
CPU time 131.61 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:36:20 PM PST 24
Peak memory 199624 kb
Host smart-b08f727d-082f-4052-b3c7-fdbe933e55e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3424192533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3424192533
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2727057334
Short name T481
Test name
Test status
Simulation time 4119741168 ps
CPU time 53.88 seconds
Started Feb 25 02:34:06 PM PST 24
Finished Feb 25 02:35:00 PM PST 24
Peak memory 199624 kb
Host smart-20943d25-0a7b-4c67-b703-15a34135b56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727057334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2727057334
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2744948283
Short name T290
Test name
Test status
Simulation time 6294019980 ps
CPU time 60.97 seconds
Started Feb 25 02:34:08 PM PST 24
Finished Feb 25 02:35:09 PM PST 24
Peak memory 199628 kb
Host smart-012a6af7-b3bd-4791-837b-9d0b2efa7b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744948283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2744948283
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3100339999
Short name T415
Test name
Test status
Simulation time 283362724 ps
CPU time 1.43 seconds
Started Feb 25 02:34:07 PM PST 24
Finished Feb 25 02:34:09 PM PST 24
Peak memory 199228 kb
Host smart-f32b2620-edf3-462f-ad11-ffda9cef980a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100339999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3100339999
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2059043125
Short name T370
Test name
Test status
Simulation time 35525777188 ps
CPU time 658.66 seconds
Started Feb 25 02:34:03 PM PST 24
Finished Feb 25 02:45:02 PM PST 24
Peak memory 238500 kb
Host smart-af028a6a-1f20-4678-9de7-4c12686ea5a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059043125 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2059043125
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2400913761
Short name T466
Test name
Test status
Simulation time 205117617 ps
CPU time 1.12 seconds
Started Feb 25 02:34:06 PM PST 24
Finished Feb 25 02:34:08 PM PST 24
Peak memory 198324 kb
Host smart-ce08fcf9-d21e-4b35-afe3-6940820df58d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400913761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2400913761
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1519281699
Short name T312
Test name
Test status
Simulation time 14157282555 ps
CPU time 366.03 seconds
Started Feb 25 02:34:05 PM PST 24
Finished Feb 25 02:40:12 PM PST 24
Peak memory 199596 kb
Host smart-8a4c0184-3535-4fc6-b631-cbd0bd6011d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519281699 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.hmac_test_sha_vectors.1519281699
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1965109803
Short name T194
Test name
Test status
Simulation time 773239270 ps
CPU time 19.26 seconds
Started Feb 25 02:34:06 PM PST 24
Finished Feb 25 02:34:26 PM PST 24
Peak memory 199488 kb
Host smart-5ddaa5c3-0f02-4e71-a916-a7f29f33a6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965109803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1965109803
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3299643552
Short name T268
Test name
Test status
Simulation time 33572189 ps
CPU time 0.56 seconds
Started Feb 25 02:34:16 PM PST 24
Finished Feb 25 02:34:17 PM PST 24
Peak memory 193752 kb
Host smart-9ba8a419-f556-45b4-8cf2-b34ae5b98fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299643552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3299643552
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.3951792493
Short name T218
Test name
Test status
Simulation time 1682083737 ps
CPU time 14.41 seconds
Started Feb 25 02:34:12 PM PST 24
Finished Feb 25 02:34:27 PM PST 24
Peak memory 214948 kb
Host smart-3f3afe24-1e17-4ed9-90fb-201765774976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951792493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.3951792493
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.825469667
Short name T224
Test name
Test status
Simulation time 1475234586 ps
CPU time 71.6 seconds
Started Feb 25 02:34:06 PM PST 24
Finished Feb 25 02:35:18 PM PST 24
Peak memory 199540 kb
Host smart-fd625a1d-108a-4f0e-a045-ea103e3cef19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825469667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.825469667
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1944452785
Short name T139
Test name
Test status
Simulation time 7548440780 ps
CPU time 75.49 seconds
Started Feb 25 02:34:05 PM PST 24
Finished Feb 25 02:35:21 PM PST 24
Peak memory 199620 kb
Host smart-8c2ac3af-9409-48b3-8e76-3b8f2a69aa9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1944452785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1944452785
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.3703743079
Short name T258
Test name
Test status
Simulation time 7177012630 ps
CPU time 112.03 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:36:01 PM PST 24
Peak memory 199616 kb
Host smart-514146f1-f1bf-4f12-92db-3aaa2210320a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703743079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.3703743079
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.335711603
Short name T594
Test name
Test status
Simulation time 17520763613 ps
CPU time 56.9 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:35:08 PM PST 24
Peak memory 199476 kb
Host smart-3c80940a-00b6-4f1c-adf7-a8aa0cfd296f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335711603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.335711603
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.673745608
Short name T450
Test name
Test status
Simulation time 855664076 ps
CPU time 4.24 seconds
Started Feb 25 02:34:08 PM PST 24
Finished Feb 25 02:34:13 PM PST 24
Peak memory 199620 kb
Host smart-aac7eff7-6776-42e7-9a31-564bac34a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673745608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.673745608
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.2149229262
Short name T272
Test name
Test status
Simulation time 1661568631 ps
CPU time 42.51 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:34:53 PM PST 24
Peak memory 199428 kb
Host smart-892ad70e-59a5-4181-9e39-05f2cacf13c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149229262 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.2149229262
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2341112594
Short name T65
Test name
Test status
Simulation time 32057054 ps
CPU time 1.09 seconds
Started Feb 25 02:34:07 PM PST 24
Finished Feb 25 02:34:08 PM PST 24
Peak memory 197684 kb
Host smart-47e8ba4c-c24a-43fc-9234-6eb82cabe295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341112594 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2341112594
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2160530888
Short name T444
Test name
Test status
Simulation time 18355944894 ps
CPU time 403.24 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:40:53 PM PST 24
Peak memory 199580 kb
Host smart-4cee6e1e-87fb-437c-b970-1bbeb799907d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160530888 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.2160530888
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1086099321
Short name T240
Test name
Test status
Simulation time 16080506928 ps
CPU time 58.53 seconds
Started Feb 25 02:34:04 PM PST 24
Finished Feb 25 02:35:02 PM PST 24
Peak memory 199664 kb
Host smart-3c3e2891-4ed6-4b48-9487-dae13ea51d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086099321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1086099321
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1609624635
Short name T34
Test name
Test status
Simulation time 15334048 ps
CPU time 0.58 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:31:34 PM PST 24
Peak memory 193952 kb
Host smart-cb5bbb1f-645b-495d-b1b0-faf55fe4654a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609624635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1609624635
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3960822584
Short name T388
Test name
Test status
Simulation time 955473124 ps
CPU time 29.83 seconds
Started Feb 25 02:31:38 PM PST 24
Finished Feb 25 02:32:08 PM PST 24
Peak memory 207756 kb
Host smart-d068d62e-040a-421b-a3e2-6b55c17bdfde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3960822584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3960822584
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.3797086972
Short name T569
Test name
Test status
Simulation time 1754548461 ps
CPU time 24.79 seconds
Started Feb 25 02:31:32 PM PST 24
Finished Feb 25 02:31:57 PM PST 24
Peak memory 199512 kb
Host smart-223ecc09-6fb6-4180-b1aa-a182031a893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797086972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.3797086972
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3102549890
Short name T28
Test name
Test status
Simulation time 5322547003 ps
CPU time 74.05 seconds
Started Feb 25 02:31:34 PM PST 24
Finished Feb 25 02:32:49 PM PST 24
Peak memory 199704 kb
Host smart-4e46ebd8-6be4-4382-a27b-9b8bb793444e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102549890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3102549890
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.304280240
Short name T517
Test name
Test status
Simulation time 1167566791 ps
CPU time 56.3 seconds
Started Feb 25 02:31:36 PM PST 24
Finished Feb 25 02:32:33 PM PST 24
Peak memory 199544 kb
Host smart-02e63911-a6c2-4014-8384-a7f3aff3ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304280240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.304280240
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.755476629
Short name T489
Test name
Test status
Simulation time 7279916296 ps
CPU time 77.32 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:32:50 PM PST 24
Peak memory 199624 kb
Host smart-e2b63199-241f-4f75-bd74-17935b8e8709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755476629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.755476629
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2961816592
Short name T40
Test name
Test status
Simulation time 82349481 ps
CPU time 0.77 seconds
Started Feb 25 02:31:34 PM PST 24
Finished Feb 25 02:31:35 PM PST 24
Peak memory 216436 kb
Host smart-dd8382e8-ac32-43b6-aa39-5cac9a229872
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961816592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2961816592
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1210252780
Short name T422
Test name
Test status
Simulation time 66946961 ps
CPU time 0.91 seconds
Started Feb 25 02:31:37 PM PST 24
Finished Feb 25 02:31:38 PM PST 24
Peak memory 197020 kb
Host smart-cbdccb0a-1f82-45d8-b5ca-d053ebb1216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210252780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1210252780
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2036523199
Short name T114
Test name
Test status
Simulation time 136729742592 ps
CPU time 1214.8 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:51:48 PM PST 24
Peak memory 232440 kb
Host smart-727a4c06-11bd-44f9-a50d-038d171a4981
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036523199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2036523199
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.962184820
Short name T499
Test name
Test status
Simulation time 95662199 ps
CPU time 0.87 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:31:34 PM PST 24
Peak memory 196792 kb
Host smart-3e7de3f8-1910-48fc-b477-c363b10e67ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962184820 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.962184820
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2620585185
Short name T358
Test name
Test status
Simulation time 70054566514 ps
CPU time 471.41 seconds
Started Feb 25 02:31:34 PM PST 24
Finished Feb 25 02:39:26 PM PST 24
Peak memory 199508 kb
Host smart-fb903bac-0c89-457c-a4b5-52a2f5946f95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620585185 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.2620585185
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.346512475
Short name T131
Test name
Test status
Simulation time 919170763 ps
CPU time 30.32 seconds
Started Feb 25 02:31:35 PM PST 24
Finished Feb 25 02:32:06 PM PST 24
Peak memory 199500 kb
Host smart-cfd1c86f-5156-43dc-94ad-df550f4d8cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346512475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.346512475
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1799398072
Short name T161
Test name
Test status
Simulation time 38469737 ps
CPU time 0.55 seconds
Started Feb 25 02:34:07 PM PST 24
Finished Feb 25 02:34:08 PM PST 24
Peak memory 193956 kb
Host smart-0b496b49-9040-4328-b226-89f9750aeb5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799398072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1799398072
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.112780766
Short name T193
Test name
Test status
Simulation time 198549117 ps
CPU time 10.09 seconds
Started Feb 25 02:34:10 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 199468 kb
Host smart-09702d20-b35a-4dd7-be4c-4bbf62a6ac73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112780766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.112780766
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1299906519
Short name T536
Test name
Test status
Simulation time 10436163209 ps
CPU time 138.47 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:36:30 PM PST 24
Peak memory 199472 kb
Host smart-d3af5c6d-abd4-4a6f-9511-dad2d3fd7b07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1299906519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1299906519
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2509928520
Short name T270
Test name
Test status
Simulation time 12307112788 ps
CPU time 78.88 seconds
Started Feb 25 02:34:14 PM PST 24
Finished Feb 25 02:35:33 PM PST 24
Peak memory 199632 kb
Host smart-0c64693e-367f-43f4-bb24-2d08dd6ab583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509928520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2509928520
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1542717819
Short name T77
Test name
Test status
Simulation time 26655779808 ps
CPU time 80.44 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:35:30 PM PST 24
Peak memory 199664 kb
Host smart-3e050fa4-e0df-4945-8871-49a12c890d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542717819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1542717819
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.174053165
Short name T508
Test name
Test status
Simulation time 996895787 ps
CPU time 2.77 seconds
Started Feb 25 02:34:12 PM PST 24
Finished Feb 25 02:34:15 PM PST 24
Peak memory 199576 kb
Host smart-fac863ed-4343-495c-8041-be440d4f340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174053165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.174053165
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.4287636450
Short name T103
Test name
Test status
Simulation time 95296382167 ps
CPU time 1832.8 seconds
Started Feb 25 02:34:12 PM PST 24
Finished Feb 25 03:04:45 PM PST 24
Peak memory 232464 kb
Host smart-61c75d3c-3f0a-4503-b5b5-926bdd66543e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287636450 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.4287636450
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3696831315
Short name T461
Test name
Test status
Simulation time 90322922 ps
CPU time 0.94 seconds
Started Feb 25 02:34:13 PM PST 24
Finished Feb 25 02:34:14 PM PST 24
Peak memory 197632 kb
Host smart-9c0292b4-fbc4-444a-8eb8-906a92bd2718
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696831315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3696831315
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.2435213367
Short name T428
Test name
Test status
Simulation time 29497506807 ps
CPU time 389.43 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:40:39 PM PST 24
Peak memory 199580 kb
Host smart-b9e99e56-93da-438e-83e6-15e81cdc5350
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435213367 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_sha_vectors.2435213367
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.3878517912
Short name T154
Test name
Test status
Simulation time 1048458237 ps
CPU time 10.43 seconds
Started Feb 25 02:34:12 PM PST 24
Finished Feb 25 02:34:22 PM PST 24
Peak memory 199500 kb
Host smart-629ffc87-dd5e-472d-b92a-82cc8afb156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878517912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.3878517912
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.3391644299
Short name T274
Test name
Test status
Simulation time 12198305 ps
CPU time 0.57 seconds
Started Feb 25 02:34:17 PM PST 24
Finished Feb 25 02:34:18 PM PST 24
Peak memory 193964 kb
Host smart-dab916b3-efb0-4dc1-99fc-8d741ce31da9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391644299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.3391644299
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2124871339
Short name T22
Test name
Test status
Simulation time 543425404 ps
CPU time 9.96 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:34:21 PM PST 24
Peak memory 207664 kb
Host smart-3fbd7dc7-8dcd-48eb-b403-7f8fb91fbd20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2124871339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2124871339
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1824370224
Short name T546
Test name
Test status
Simulation time 2756356587 ps
CPU time 49.75 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:35:01 PM PST 24
Peak memory 199652 kb
Host smart-a77f7018-8999-45c9-bc62-bb8cc04883f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824370224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1824370224
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.2817471927
Short name T322
Test name
Test status
Simulation time 641615749 ps
CPU time 35 seconds
Started Feb 25 02:34:09 PM PST 24
Finished Feb 25 02:34:44 PM PST 24
Peak memory 199488 kb
Host smart-4efc395a-1af5-48c3-be17-23e8311cecad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2817471927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.2817471927
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2281643837
Short name T464
Test name
Test status
Simulation time 752819518 ps
CPU time 36.15 seconds
Started Feb 25 02:34:11 PM PST 24
Finished Feb 25 02:34:47 PM PST 24
Peak memory 199396 kb
Host smart-4bfbe45a-03c4-4c1e-bc46-218229b400ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281643837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2281643837
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_smoke.2696589937
Short name T248
Test name
Test status
Simulation time 121926830 ps
CPU time 3.2 seconds
Started Feb 25 02:34:08 PM PST 24
Finished Feb 25 02:34:11 PM PST 24
Peak memory 199484 kb
Host smart-f2a13ab1-2128-429e-8540-d17d98827f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696589937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2696589937
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.1429381712
Short name T140
Test name
Test status
Simulation time 33040323801 ps
CPU time 392.53 seconds
Started Feb 25 02:34:16 PM PST 24
Finished Feb 25 02:40:49 PM PST 24
Peak memory 233352 kb
Host smart-a2550e62-59bf-4e35-a7d7-25ab571d2dce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429381712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.1429381712
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2931741792
Short name T440
Test name
Test status
Simulation time 28115854 ps
CPU time 0.9 seconds
Started Feb 25 02:34:08 PM PST 24
Finished Feb 25 02:34:09 PM PST 24
Peak memory 196776 kb
Host smart-9d71eec3-9bb4-4b54-8b3d-fca40ae2579c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931741792 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2931741792
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.3002930924
Short name T399
Test name
Test status
Simulation time 44260229314 ps
CPU time 375.15 seconds
Started Feb 25 02:34:14 PM PST 24
Finished Feb 25 02:40:29 PM PST 24
Peak memory 199572 kb
Host smart-87d7ab89-ba1d-44aa-b354-cc1cae41fc91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002930924 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_sha_vectors.3002930924
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.3347588484
Short name T293
Test name
Test status
Simulation time 5679747299 ps
CPU time 23.03 seconds
Started Feb 25 02:34:10 PM PST 24
Finished Feb 25 02:34:33 PM PST 24
Peak memory 199640 kb
Host smart-0f302566-30ec-4be3-a592-bf7c35760053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347588484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.3347588484
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.178415193
Short name T176
Test name
Test status
Simulation time 14437342 ps
CPU time 0.57 seconds
Started Feb 25 02:34:21 PM PST 24
Finished Feb 25 02:34:22 PM PST 24
Peak memory 193752 kb
Host smart-b975be8a-6884-4796-b42f-f70f49fe4cf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178415193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.178415193
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.213443779
Short name T190
Test name
Test status
Simulation time 466596229 ps
CPU time 10.53 seconds
Started Feb 25 02:34:16 PM PST 24
Finished Feb 25 02:34:27 PM PST 24
Peak memory 221560 kb
Host smart-09c1f372-3965-4f5e-b239-f9e3263f4ff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213443779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.213443779
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3685945606
Short name T127
Test name
Test status
Simulation time 1776538246 ps
CPU time 14.92 seconds
Started Feb 25 02:34:17 PM PST 24
Finished Feb 25 02:34:32 PM PST 24
Peak memory 199504 kb
Host smart-ad3beef6-85ba-48e3-97c7-06581b1f2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685945606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3685945606
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1374577008
Short name T483
Test name
Test status
Simulation time 138531950 ps
CPU time 3.58 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:34:22 PM PST 24
Peak memory 199520 kb
Host smart-2925bcb3-e072-47ee-a05f-06f02986c315
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374577008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1374577008
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3449844212
Short name T332
Test name
Test status
Simulation time 1122914079 ps
CPU time 57.89 seconds
Started Feb 25 02:34:22 PM PST 24
Finished Feb 25 02:35:20 PM PST 24
Peak memory 199520 kb
Host smart-2fce31d5-51fa-451c-85b5-953f6b268ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449844212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3449844212
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1741087610
Short name T368
Test name
Test status
Simulation time 2874810047 ps
CPU time 27.04 seconds
Started Feb 25 02:34:15 PM PST 24
Finished Feb 25 02:34:42 PM PST 24
Peak memory 199680 kb
Host smart-1c84c51d-4205-4e49-8df8-f6d3e3003290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741087610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1741087610
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3521157095
Short name T396
Test name
Test status
Simulation time 833373921 ps
CPU time 3.16 seconds
Started Feb 25 02:34:16 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 199424 kb
Host smart-3e7aa5fc-fdc7-415a-87b7-8ed61c1ac7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521157095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3521157095
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.287247028
Short name T128
Test name
Test status
Simulation time 19265628113 ps
CPU time 320.63 seconds
Started Feb 25 02:34:20 PM PST 24
Finished Feb 25 02:39:41 PM PST 24
Peak memory 224240 kb
Host smart-bc0d0b33-f695-47c3-96fa-67e7827bd8b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287247028 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.287247028
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3058962659
Short name T250
Test name
Test status
Simulation time 73068833 ps
CPU time 1.31 seconds
Started Feb 25 02:34:17 PM PST 24
Finished Feb 25 02:34:19 PM PST 24
Peak memory 198752 kb
Host smart-fc4f0738-262d-402b-bea5-31a1c6094e04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058962659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3058962659
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1330882076
Short name T233
Test name
Test status
Simulation time 99325234730 ps
CPU time 396.83 seconds
Started Feb 25 02:34:20 PM PST 24
Finished Feb 25 02:40:57 PM PST 24
Peak memory 199560 kb
Host smart-9e715bf7-19d9-40f8-afc3-047163afdfcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330882076 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.1330882076
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_alert_test.3282448653
Short name T560
Test name
Test status
Simulation time 13784713 ps
CPU time 0.55 seconds
Started Feb 25 02:34:26 PM PST 24
Finished Feb 25 02:34:27 PM PST 24
Peak memory 193744 kb
Host smart-ba0fd217-a1df-447c-8863-442c4e085c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282448653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.3282448653
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.4263800581
Short name T276
Test name
Test status
Simulation time 1159002517 ps
CPU time 4.78 seconds
Started Feb 25 02:34:16 PM PST 24
Finished Feb 25 02:34:21 PM PST 24
Peak memory 199544 kb
Host smart-f504af04-ed89-4e46-955d-f62d8c2a849c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263800581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.4263800581
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2531970319
Short name T195
Test name
Test status
Simulation time 1954677138 ps
CPU time 7.81 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:34:26 PM PST 24
Peak memory 199528 kb
Host smart-625f61ec-357b-46f7-a06e-14f59e26f87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531970319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2531970319
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2793452248
Short name T43
Test name
Test status
Simulation time 646054002 ps
CPU time 35.46 seconds
Started Feb 25 02:34:20 PM PST 24
Finished Feb 25 02:34:56 PM PST 24
Peak memory 199504 kb
Host smart-1f99e21e-f08b-4758-a7c9-8bb288a1119d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793452248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2793452248
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.1600928394
Short name T429
Test name
Test status
Simulation time 26948223128 ps
CPU time 109.24 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:36:07 PM PST 24
Peak memory 199596 kb
Host smart-df242785-8fd3-47a9-b8c5-9840092483de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600928394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1600928394
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3713330011
Short name T357
Test name
Test status
Simulation time 1044405993 ps
CPU time 13.61 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:34:32 PM PST 24
Peak memory 199536 kb
Host smart-890b5b1b-55f8-42e4-b291-529898c34682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713330011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3713330011
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.678257246
Short name T416
Test name
Test status
Simulation time 80826478 ps
CPU time 1.47 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:34:20 PM PST 24
Peak memory 198420 kb
Host smart-8edb77ba-fd33-472b-9e4c-2e7a19817746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678257246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.678257246
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2642635633
Short name T75
Test name
Test status
Simulation time 457006570809 ps
CPU time 1379.48 seconds
Started Feb 25 02:34:19 PM PST 24
Finished Feb 25 02:57:19 PM PST 24
Peak memory 207868 kb
Host smart-244a91aa-e721-43c0-937a-eb6ce570b512
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642635633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2642635633
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1280264219
Short name T349
Test name
Test status
Simulation time 32360602 ps
CPU time 1.08 seconds
Started Feb 25 02:34:21 PM PST 24
Finished Feb 25 02:34:23 PM PST 24
Peak memory 197376 kb
Host smart-9b2b0b6b-734b-4a3f-8a40-60da7deae594
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280264219 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.1280264219
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1508702642
Short name T46
Test name
Test status
Simulation time 26318831133 ps
CPU time 319.54 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:39:38 PM PST 24
Peak memory 199592 kb
Host smart-f86c1ea8-b70e-4040-989a-d50d74841035
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508702642 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.1508702642
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1292316031
Short name T465
Test name
Test status
Simulation time 2276375215 ps
CPU time 22.32 seconds
Started Feb 25 02:34:18 PM PST 24
Finished Feb 25 02:34:40 PM PST 24
Peak memory 199632 kb
Host smart-d5a93dfd-4df3-42c3-89b2-b273527ecb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292316031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1292316031
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2822903727
Short name T66
Test name
Test status
Simulation time 56145689 ps
CPU time 0.56 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:34:29 PM PST 24
Peak memory 193764 kb
Host smart-e4ff3ccd-b0d6-4f3d-8f83-fde2c3307995
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822903727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2822903727
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2793299209
Short name T559
Test name
Test status
Simulation time 2699386062 ps
CPU time 53.17 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:35:22 PM PST 24
Peak memory 220012 kb
Host smart-712beb05-1148-4869-8314-cc7ad25abd9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793299209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2793299209
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1679079440
Short name T411
Test name
Test status
Simulation time 4459545347 ps
CPU time 46.12 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:35:13 PM PST 24
Peak memory 199620 kb
Host smart-5e66a044-9c98-48fc-a89b-39efe640c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679079440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1679079440
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.247082993
Short name T375
Test name
Test status
Simulation time 3931516914 ps
CPU time 42.42 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:35:10 PM PST 24
Peak memory 199668 kb
Host smart-26f8a366-18ac-4756-8fe8-aaddeb087a7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247082993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.247082993
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1953471453
Short name T386
Test name
Test status
Simulation time 15896991287 ps
CPU time 126.34 seconds
Started Feb 25 02:34:25 PM PST 24
Finished Feb 25 02:36:32 PM PST 24
Peak memory 199620 kb
Host smart-b09f91ed-5cb6-45a6-8b46-b790ed90e63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953471453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1953471453
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.362676948
Short name T14
Test name
Test status
Simulation time 17601646373 ps
CPU time 77.06 seconds
Started Feb 25 02:34:25 PM PST 24
Finished Feb 25 02:35:42 PM PST 24
Peak memory 199668 kb
Host smart-9d3d6f91-0832-43c3-be4a-1608d6ecb79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362676948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.362676948
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1649059468
Short name T287
Test name
Test status
Simulation time 774246295 ps
CPU time 2.07 seconds
Started Feb 25 02:34:30 PM PST 24
Finished Feb 25 02:34:32 PM PST 24
Peak memory 199492 kb
Host smart-f0a54380-6f06-4a7a-bfbc-6799cee70007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649059468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1649059468
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3328187805
Short name T387
Test name
Test status
Simulation time 17326563914 ps
CPU time 853.91 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:48:43 PM PST 24
Peak memory 239748 kb
Host smart-5e93576b-c88e-4681-a769-4779ab0196b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328187805 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3328187805
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.250265149
Short name T33
Test name
Test status
Simulation time 147240847 ps
CPU time 0.92 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:34:28 PM PST 24
Peak memory 197172 kb
Host smart-bb6471b2-2d3d-462f-bcba-768bbd7e8eca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250265149 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.250265149
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.2882476214
Short name T155
Test name
Test status
Simulation time 87627029004 ps
CPU time 499.93 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:42:48 PM PST 24
Peak memory 199556 kb
Host smart-f5bcf0d1-30d8-4649-801a-cc370204a682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882476214 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_sha_vectors.2882476214
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4091735969
Short name T198
Test name
Test status
Simulation time 5175867186 ps
CPU time 35.48 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:35:03 PM PST 24
Peak memory 199652 kb
Host smart-d8d66cb2-39d9-43e3-b841-3f05161bfd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091735969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4091735969
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1171884308
Short name T424
Test name
Test status
Simulation time 78062012 ps
CPU time 0.53 seconds
Started Feb 25 02:34:32 PM PST 24
Finished Feb 25 02:34:33 PM PST 24
Peak memory 193744 kb
Host smart-5b07e8ca-dd54-425f-8aa8-901695e43f22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171884308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1171884308
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2053116923
Short name T316
Test name
Test status
Simulation time 7849778972 ps
CPU time 18.91 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:34:47 PM PST 24
Peak memory 215304 kb
Host smart-03616dd1-0434-4331-a455-689cc980ccbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053116923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2053116923
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.3758672657
Short name T468
Test name
Test status
Simulation time 2644884627 ps
CPU time 29.23 seconds
Started Feb 25 02:34:26 PM PST 24
Finished Feb 25 02:34:56 PM PST 24
Peak memory 199648 kb
Host smart-d77ee0fe-d235-4fb6-9b79-661f770da45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758672657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.3758672657
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.462336126
Short name T538
Test name
Test status
Simulation time 1082919683 ps
CPU time 49.32 seconds
Started Feb 25 02:34:25 PM PST 24
Finished Feb 25 02:35:14 PM PST 24
Peak memory 199512 kb
Host smart-f886661e-d38b-4265-92b4-57fc7f31d23e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=462336126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.462336126
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1615037427
Short name T378
Test name
Test status
Simulation time 50336241928 ps
CPU time 181.38 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:37:28 PM PST 24
Peak memory 199628 kb
Host smart-b686481c-df3f-4e44-aef5-97f4e1f4a92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615037427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1615037427
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3426612304
Short name T482
Test name
Test status
Simulation time 55775310061 ps
CPU time 46.44 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:35:22 PM PST 24
Peak memory 199640 kb
Host smart-66dd4f11-9bb2-4ab1-b947-49e7db67a6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426612304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3426612304
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1140478994
Short name T279
Test name
Test status
Simulation time 157416581 ps
CPU time 1.3 seconds
Started Feb 25 02:34:32 PM PST 24
Finished Feb 25 02:34:34 PM PST 24
Peak memory 199276 kb
Host smart-a0bb503d-98df-4ac2-a0bd-81ece35f4784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140478994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1140478994
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.692827028
Short name T254
Test name
Test status
Simulation time 60152399 ps
CPU time 1.16 seconds
Started Feb 25 02:34:28 PM PST 24
Finished Feb 25 02:34:29 PM PST 24
Peak memory 198152 kb
Host smart-f6d48424-51c7-4965-9047-235a0139ec22
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692827028 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.692827028
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.749852480
Short name T591
Test name
Test status
Simulation time 120062858344 ps
CPU time 419.94 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:41:35 PM PST 24
Peak memory 199560 kb
Host smart-c018d9b1-5baf-404e-bf2a-0c2771bdc98d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749852480 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.hmac_test_sha_vectors.749852480
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2211608048
Short name T525
Test name
Test status
Simulation time 6351075784 ps
CPU time 55.39 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:35:30 PM PST 24
Peak memory 199652 kb
Host smart-4dab13d0-42d4-47e1-985d-20a6f4abaebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211608048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2211608048
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3759230904
Short name T237
Test name
Test status
Simulation time 21963747 ps
CPU time 0.57 seconds
Started Feb 25 02:34:36 PM PST 24
Finished Feb 25 02:34:36 PM PST 24
Peak memory 193960 kb
Host smart-3f8452cc-07b6-4436-baa5-57dd18795770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759230904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3759230904
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.4028235393
Short name T472
Test name
Test status
Simulation time 1323611534 ps
CPU time 21.07 seconds
Started Feb 25 02:34:26 PM PST 24
Finished Feb 25 02:34:47 PM PST 24
Peak memory 215884 kb
Host smart-fd62a995-486b-4bfc-ad05-38be2fcd0817
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028235393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.4028235393
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2578674801
Short name T318
Test name
Test status
Simulation time 16653243452 ps
CPU time 32.35 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:35:00 PM PST 24
Peak memory 199668 kb
Host smart-b7a080aa-327d-485b-b6d6-367dbac379b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578674801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2578674801
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2713279395
Short name T107
Test name
Test status
Simulation time 7536204579 ps
CPU time 81.47 seconds
Started Feb 25 02:34:32 PM PST 24
Finished Feb 25 02:35:53 PM PST 24
Peak memory 199632 kb
Host smart-53c28252-e634-496a-9704-97916dfe7eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713279395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2713279395
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2327564915
Short name T245
Test name
Test status
Simulation time 30638293598 ps
CPU time 124.32 seconds
Started Feb 25 02:34:29 PM PST 24
Finished Feb 25 02:36:33 PM PST 24
Peak memory 199640 kb
Host smart-b91a535a-2c58-462a-bf46-28b49dd18ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327564915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2327564915
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.4040876619
Short name T367
Test name
Test status
Simulation time 3788478729 ps
CPU time 16.14 seconds
Started Feb 25 02:34:27 PM PST 24
Finished Feb 25 02:34:43 PM PST 24
Peak memory 199652 kb
Host smart-5d0c1689-3eb6-45d3-9e5e-735c2adbbf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040876619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.4040876619
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3521950039
Short name T501
Test name
Test status
Simulation time 140677612 ps
CPU time 2.17 seconds
Started Feb 25 02:34:30 PM PST 24
Finished Feb 25 02:34:32 PM PST 24
Peak memory 199496 kb
Host smart-285f377e-b25f-4a1f-8f06-838846a8cb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521950039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3521950039
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3871291896
Short name T113
Test name
Test status
Simulation time 23673491927 ps
CPU time 1150.92 seconds
Started Feb 25 02:34:37 PM PST 24
Finished Feb 25 02:53:48 PM PST 24
Peak memory 199660 kb
Host smart-d8388c4f-0238-42b0-8216-238b4314cb04
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871291896 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3871291896
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1466944460
Short name T334
Test name
Test status
Simulation time 28064838 ps
CPU time 0.96 seconds
Started Feb 25 02:34:33 PM PST 24
Finished Feb 25 02:34:34 PM PST 24
Peak memory 196936 kb
Host smart-09ca89cc-a5bc-454f-9f8d-9f998845b1c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466944460 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.1466944460
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3154661853
Short name T30
Test name
Test status
Simulation time 55497932346 ps
CPU time 411.8 seconds
Started Feb 25 02:34:44 PM PST 24
Finished Feb 25 02:41:36 PM PST 24
Peak memory 199592 kb
Host smart-31995257-66fb-4fc6-9592-4db7fecbfb31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154661853 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.3154661853
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.25291305
Short name T172
Test name
Test status
Simulation time 3839573058 ps
CPU time 34.29 seconds
Started Feb 25 02:34:33 PM PST 24
Finished Feb 25 02:35:07 PM PST 24
Peak memory 199616 kb
Host smart-f4f0cea6-8c86-4582-a5dc-cb586b955638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25291305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.25291305
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4023312016
Short name T13
Test name
Test status
Simulation time 13774687 ps
CPU time 0.6 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:34:36 PM PST 24
Peak memory 193748 kb
Host smart-aa940567-fa20-474a-a5b7-851336f7ca16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023312016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4023312016
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.2654914755
Short name T565
Test name
Test status
Simulation time 10227911324 ps
CPU time 60.51 seconds
Started Feb 25 02:34:34 PM PST 24
Finished Feb 25 02:35:35 PM PST 24
Peak memory 232368 kb
Host smart-8f1c266e-8f13-48d1-b656-3c87db55b6b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2654914755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.2654914755
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.796113293
Short name T328
Test name
Test status
Simulation time 673638059 ps
CPU time 9.52 seconds
Started Feb 25 02:34:34 PM PST 24
Finished Feb 25 02:34:43 PM PST 24
Peak memory 199428 kb
Host smart-5fd27a2e-d9f9-445b-92c9-aee7ea59dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796113293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.796113293
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.213643829
Short name T78
Test name
Test status
Simulation time 2505203636 ps
CPU time 134.34 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:36:50 PM PST 24
Peak memory 199620 kb
Host smart-cf90f38d-7566-43de-8412-78d310423198
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213643829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.213643829
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.853849424
Short name T179
Test name
Test status
Simulation time 78473063006 ps
CPU time 197.06 seconds
Started Feb 25 02:34:34 PM PST 24
Finished Feb 25 02:37:51 PM PST 24
Peak memory 199724 kb
Host smart-fb0c5fba-62a2-4c61-9ccd-1d9dfb5cae42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853849424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.853849424
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.628146570
Short name T372
Test name
Test status
Simulation time 6217157945 ps
CPU time 81.63 seconds
Started Feb 25 02:34:37 PM PST 24
Finished Feb 25 02:35:59 PM PST 24
Peak memory 199632 kb
Host smart-798c627a-bb1b-4b0b-b849-c1e9277e4fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628146570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.628146570
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.407994913
Short name T390
Test name
Test status
Simulation time 164638714 ps
CPU time 3.72 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:34:39 PM PST 24
Peak memory 199624 kb
Host smart-585a67a8-1a21-4e50-8923-bdfaeb2a6ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407994913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.407994913
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.3785496373
Short name T574
Test name
Test status
Simulation time 7869138790 ps
CPU time 72.65 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:35:47 PM PST 24
Peak memory 199672 kb
Host smart-52a008c5-c206-4939-ad32-f243117ea283
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785496373 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.3785496373
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.626056231
Short name T534
Test name
Test status
Simulation time 54956932 ps
CPU time 1.15 seconds
Started Feb 25 02:34:44 PM PST 24
Finished Feb 25 02:34:45 PM PST 24
Peak memory 198200 kb
Host smart-08813cd7-8b09-4b17-82d9-7fc3073814a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626056231 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_hmac_vectors.626056231
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1823407789
Short name T530
Test name
Test status
Simulation time 120044878501 ps
CPU time 477.14 seconds
Started Feb 25 02:34:33 PM PST 24
Finished Feb 25 02:42:30 PM PST 24
Peak memory 199616 kb
Host smart-d99d45c7-a003-4334-9d6e-1b750c439a83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823407789 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.hmac_test_sha_vectors.1823407789
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.134818742
Short name T462
Test name
Test status
Simulation time 7824127346 ps
CPU time 36.12 seconds
Started Feb 25 02:34:44 PM PST 24
Finished Feb 25 02:35:20 PM PST 24
Peak memory 199648 kb
Host smart-19a4366c-d0a2-419c-8a9c-097a4f52f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134818742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.134818742
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2116548691
Short name T568
Test name
Test status
Simulation time 44091047 ps
CPU time 0.58 seconds
Started Feb 25 02:34:51 PM PST 24
Finished Feb 25 02:34:52 PM PST 24
Peak memory 194780 kb
Host smart-2bb3d40d-0b8d-41b9-95b4-8790f2dbf9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116548691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2116548691
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.192008547
Short name T297
Test name
Test status
Simulation time 957067335 ps
CPU time 28.77 seconds
Started Feb 25 02:34:37 PM PST 24
Finished Feb 25 02:35:06 PM PST 24
Peak memory 212184 kb
Host smart-2b9efd64-4800-4a15-8cec-1e6cbd738881
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=192008547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.192008547
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.3778715141
Short name T308
Test name
Test status
Simulation time 279361963 ps
CPU time 3.66 seconds
Started Feb 25 02:34:48 PM PST 24
Finished Feb 25 02:34:52 PM PST 24
Peak memory 199468 kb
Host smart-b4429741-f572-4d25-ac00-c3b3b71c7879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778715141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.3778715141
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1435069739
Short name T265
Test name
Test status
Simulation time 1367685668 ps
CPU time 74.44 seconds
Started Feb 25 02:34:52 PM PST 24
Finished Feb 25 02:36:08 PM PST 24
Peak memory 199568 kb
Host smart-f7be28a2-0629-4c81-96d9-cdcc8bd28fd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1435069739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1435069739
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1554608899
Short name T347
Test name
Test status
Simulation time 1704328778 ps
CPU time 87.4 seconds
Started Feb 25 02:34:51 PM PST 24
Finished Feb 25 02:36:19 PM PST 24
Peak memory 199528 kb
Host smart-8ab4a570-9b82-49b7-8cb4-9940b97037a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554608899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1554608899
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.1834280649
Short name T27
Test name
Test status
Simulation time 2898776188 ps
CPU time 76.27 seconds
Started Feb 25 02:34:36 PM PST 24
Finished Feb 25 02:35:52 PM PST 24
Peak memory 199632 kb
Host smart-b88f4329-e242-4c57-ae43-25f80375b6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834280649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.1834280649
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.2750074818
Short name T134
Test name
Test status
Simulation time 155464300 ps
CPU time 3.67 seconds
Started Feb 25 02:34:35 PM PST 24
Finished Feb 25 02:34:39 PM PST 24
Peak memory 199500 kb
Host smart-0f8fa541-ceb7-4a11-b10a-7edc251562ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750074818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.2750074818
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3882379536
Short name T557
Test name
Test status
Simulation time 65443843541 ps
CPU time 840.44 seconds
Started Feb 25 02:34:48 PM PST 24
Finished Feb 25 02:48:49 PM PST 24
Peak memory 221048 kb
Host smart-2772cdf5-b66f-40df-b895-bd2b110d1d94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882379536 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3882379536
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2271722504
Short name T169
Test name
Test status
Simulation time 55496988 ps
CPU time 1.26 seconds
Started Feb 25 02:34:52 PM PST 24
Finished Feb 25 02:34:55 PM PST 24
Peak memory 198696 kb
Host smart-5cf0d843-931a-4e0b-92fe-b1a4e7521d24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271722504 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2271722504
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3927574373
Short name T289
Test name
Test status
Simulation time 27140222475 ps
CPU time 423.88 seconds
Started Feb 25 02:34:47 PM PST 24
Finished Feb 25 02:41:51 PM PST 24
Peak memory 199580 kb
Host smart-b60e08e0-40ce-4af3-879c-c5b76ca62b9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927574373 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.3927574373
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.328762315
Short name T306
Test name
Test status
Simulation time 4505410580 ps
CPU time 77.91 seconds
Started Feb 25 02:34:46 PM PST 24
Finished Feb 25 02:36:04 PM PST 24
Peak memory 199648 kb
Host smart-ef7ccd7d-e32e-45bb-90d9-46aad6ad7490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328762315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.328762315
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.3331852923
Short name T338
Test name
Test status
Simulation time 46376508 ps
CPU time 0.56 seconds
Started Feb 25 02:34:48 PM PST 24
Finished Feb 25 02:34:49 PM PST 24
Peak memory 193752 kb
Host smart-96bc2842-4cc2-4a3b-8d43-2350b2b6dafd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331852923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.3331852923
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2318267619
Short name T200
Test name
Test status
Simulation time 4592780478 ps
CPU time 47.2 seconds
Started Feb 25 02:34:48 PM PST 24
Finished Feb 25 02:35:36 PM PST 24
Peak memory 226172 kb
Host smart-38d07870-0b61-46b7-b192-7a69c18bfbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318267619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2318267619
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2855364705
Short name T324
Test name
Test status
Simulation time 3319974409 ps
CPU time 50 seconds
Started Feb 25 02:34:49 PM PST 24
Finished Feb 25 02:35:40 PM PST 24
Peak memory 199580 kb
Host smart-543338e6-1c78-493e-8e22-a15b0eaf7a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855364705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2855364705
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.662788110
Short name T458
Test name
Test status
Simulation time 1240215089 ps
CPU time 65.79 seconds
Started Feb 25 02:34:47 PM PST 24
Finished Feb 25 02:35:54 PM PST 24
Peak memory 199508 kb
Host smart-4222121e-eb09-4081-9537-8245a6333f0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=662788110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.662788110
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.3205498459
Short name T344
Test name
Test status
Simulation time 6347332997 ps
CPU time 111.16 seconds
Started Feb 25 02:34:52 PM PST 24
Finished Feb 25 02:36:45 PM PST 24
Peak memory 199796 kb
Host smart-3361817f-e4f6-4722-b64c-cd3a8b69a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205498459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.3205498459
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1830251089
Short name T503
Test name
Test status
Simulation time 348321777 ps
CPU time 17.58 seconds
Started Feb 25 02:34:52 PM PST 24
Finished Feb 25 02:35:11 PM PST 24
Peak memory 199528 kb
Host smart-38c1aa57-9f81-4170-9018-120795418854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830251089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1830251089
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3670617699
Short name T162
Test name
Test status
Simulation time 204042731 ps
CPU time 2.9 seconds
Started Feb 25 02:34:55 PM PST 24
Finished Feb 25 02:34:58 PM PST 24
Peak memory 199508 kb
Host smart-caef73e9-2eb4-470d-b71f-ba187aaa5cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670617699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3670617699
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.978353131
Short name T60
Test name
Test status
Simulation time 47247520 ps
CPU time 0.88 seconds
Started Feb 25 02:34:48 PM PST 24
Finished Feb 25 02:34:50 PM PST 24
Peak memory 197116 kb
Host smart-6c5b91e0-8b00-4476-9554-63012f5c0c3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978353131 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.978353131
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.360300753
Short name T475
Test name
Test status
Simulation time 7914672575 ps
CPU time 401.79 seconds
Started Feb 25 02:34:46 PM PST 24
Finished Feb 25 02:41:28 PM PST 24
Peak memory 199552 kb
Host smart-50d5f0d8-482c-4a0c-94dc-bd32df7a7b2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360300753 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 49.hmac_test_sha_vectors.360300753
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.156906230
Short name T542
Test name
Test status
Simulation time 651227577 ps
CPU time 7.73 seconds
Started Feb 25 02:34:55 PM PST 24
Finished Feb 25 02:35:03 PM PST 24
Peak memory 199580 kb
Host smart-c08fa452-42f0-49ed-8172-0c8914419e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156906230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.156906230
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.408373709
Short name T301
Test name
Test status
Simulation time 13362579 ps
CPU time 0.62 seconds
Started Feb 25 02:31:46 PM PST 24
Finished Feb 25 02:31:47 PM PST 24
Peak memory 193756 kb
Host smart-bcd563ea-8e8d-4229-90b1-b9dff314389c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408373709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.408373709
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.3396779257
Short name T123
Test name
Test status
Simulation time 938596377 ps
CPU time 30.42 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:32:04 PM PST 24
Peak memory 207724 kb
Host smart-9b7805b0-cf02-4af8-9e1c-8ec88e18a229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3396779257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.3396779257
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.539191313
Short name T319
Test name
Test status
Simulation time 581330057 ps
CPU time 27.31 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:32:00 PM PST 24
Peak memory 199512 kb
Host smart-8da19494-8ab3-4fde-860f-a500247f5e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539191313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.539191313
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3813596736
Short name T137
Test name
Test status
Simulation time 10229336009 ps
CPU time 88.25 seconds
Started Feb 25 02:31:35 PM PST 24
Finished Feb 25 02:33:03 PM PST 24
Peak memory 199684 kb
Host smart-62137f3f-344e-4ce0-9424-ccf490b22212
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3813596736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3813596736
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.3250527707
Short name T537
Test name
Test status
Simulation time 3333142997 ps
CPU time 173.92 seconds
Started Feb 25 02:31:32 PM PST 24
Finished Feb 25 02:34:26 PM PST 24
Peak memory 199688 kb
Host smart-cdcc9eff-be3b-4a00-8838-07745bb195ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250527707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.3250527707
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.281770811
Short name T309
Test name
Test status
Simulation time 6866637446 ps
CPU time 93.14 seconds
Started Feb 25 02:31:34 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 199624 kb
Host smart-32cbcba1-2ea9-49a5-9c0b-3e452ade1331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281770811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.281770811
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.306449270
Short name T271
Test name
Test status
Simulation time 1829296846 ps
CPU time 1.78 seconds
Started Feb 25 02:31:34 PM PST 24
Finished Feb 25 02:31:36 PM PST 24
Peak memory 199556 kb
Host smart-d0b21386-cc67-4a59-bd21-942bd92d3777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306449270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.306449270
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2673302021
Short name T47
Test name
Test status
Simulation time 173207545 ps
CPU time 0.93 seconds
Started Feb 25 02:31:32 PM PST 24
Finished Feb 25 02:31:33 PM PST 24
Peak memory 196872 kb
Host smart-33179d87-76a1-4b1d-a24e-6b883635bc57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673302021 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2673302021
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1785989196
Short name T485
Test name
Test status
Simulation time 25422895607 ps
CPU time 442.18 seconds
Started Feb 25 02:31:33 PM PST 24
Finished Feb 25 02:38:55 PM PST 24
Peak memory 199552 kb
Host smart-a40ef5f0-2a57-43ba-9d74-c1dcd4dd5b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785989196 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.1785989196
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4243579703
Short name T205
Test name
Test status
Simulation time 2339869535 ps
CPU time 5.8 seconds
Started Feb 25 02:31:32 PM PST 24
Finished Feb 25 02:31:38 PM PST 24
Peak memory 199644 kb
Host smart-c9f97638-39fa-49cc-b6e8-552ab2fad33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243579703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4243579703
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/53.hmac_stress_all_with_rand_reset.2984444054
Short name T15
Test name
Test status
Simulation time 97958659614 ps
CPU time 708.69 seconds
Started Feb 25 02:34:46 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 232416 kb
Host smart-74d63b7a-f144-43b2-b34b-35c81ec20297
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984444054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.hmac_stress_all_with_rand_reset.2984444054
Directory /workspace/53.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2973962845
Short name T452
Test name
Test status
Simulation time 13428107 ps
CPU time 0.58 seconds
Started Feb 25 02:31:45 PM PST 24
Finished Feb 25 02:31:46 PM PST 24
Peak memory 193788 kb
Host smart-fe62d0de-d93f-4858-8f66-29b3e920ea95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973962845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2973962845
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2702123071
Short name T185
Test name
Test status
Simulation time 4122370227 ps
CPU time 43.25 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:32:33 PM PST 24
Peak memory 207844 kb
Host smart-6a1bb2ec-a083-4222-8fe1-12823e15a2d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702123071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2702123071
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2195646657
Short name T584
Test name
Test status
Simulation time 543628996 ps
CPU time 11.23 seconds
Started Feb 25 02:31:47 PM PST 24
Finished Feb 25 02:31:59 PM PST 24
Peak memory 199556 kb
Host smart-39483bcd-aa9c-488b-abc3-7ffa0d9efd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195646657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2195646657
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.1035822144
Short name T277
Test name
Test status
Simulation time 1026116000 ps
CPU time 28.35 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:32:19 PM PST 24
Peak memory 199568 kb
Host smart-76605e5d-11d8-4f76-8d46-39cb54f4e6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035822144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.1035822144
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1175664937
Short name T425
Test name
Test status
Simulation time 7859166433 ps
CPU time 135.11 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:34:06 PM PST 24
Peak memory 199624 kb
Host smart-35b9e937-a0d3-4e67-8ce5-30e2ea309220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175664937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1175664937
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.2953801588
Short name T453
Test name
Test status
Simulation time 220949939 ps
CPU time 4.67 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:31:54 PM PST 24
Peak memory 199340 kb
Host smart-50757a67-ac03-43a2-8eaa-f5d3dd2162f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953801588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.2953801588
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1951826176
Short name T592
Test name
Test status
Simulation time 400050408 ps
CPU time 4.46 seconds
Started Feb 25 02:31:45 PM PST 24
Finished Feb 25 02:31:49 PM PST 24
Peak memory 199564 kb
Host smart-7d2dbb19-2793-4f3d-9f5d-f3bb49578753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951826176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1951826176
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.382681335
Short name T72
Test name
Test status
Simulation time 327584951020 ps
CPU time 1664.72 seconds
Started Feb 25 02:31:46 PM PST 24
Finished Feb 25 02:59:31 PM PST 24
Peak memory 240672 kb
Host smart-70d9c608-3523-4b7f-ae3c-9e22c92844d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382681335 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.382681335
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.1566913423
Short name T191
Test name
Test status
Simulation time 41130018 ps
CPU time 1.01 seconds
Started Feb 25 02:31:44 PM PST 24
Finished Feb 25 02:31:45 PM PST 24
Peak memory 197416 kb
Host smart-b1007fd8-2d09-4837-b28b-c8ca4866db3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566913423 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.1566913423
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2380245148
Short name T383
Test name
Test status
Simulation time 644834442 ps
CPU time 26.02 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:32:16 PM PST 24
Peak memory 199512 kb
Host smart-357c25f1-ee5d-4687-9728-ddc1b2f81146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380245148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2380245148
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1208175239
Short name T48
Test name
Test status
Simulation time 16714666 ps
CPU time 0.58 seconds
Started Feb 25 02:31:55 PM PST 24
Finished Feb 25 02:31:55 PM PST 24
Peak memory 193948 kb
Host smart-a2c0ebde-3df3-4ec0-9305-3ce7df994d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208175239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1208175239
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.152537495
Short name T526
Test name
Test status
Simulation time 470290855 ps
CPU time 8.07 seconds
Started Feb 25 02:31:52 PM PST 24
Finished Feb 25 02:32:00 PM PST 24
Peak memory 207684 kb
Host smart-91f19167-7c78-4768-8166-4014172721a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=152537495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.152537495
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.268788686
Short name T310
Test name
Test status
Simulation time 3818977321 ps
CPU time 11.39 seconds
Started Feb 25 02:31:45 PM PST 24
Finished Feb 25 02:31:56 PM PST 24
Peak memory 199644 kb
Host smart-b82dfa2f-e5f2-4485-8e5d-e47aa373d6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268788686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.268788686
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.2246577179
Short name T210
Test name
Test status
Simulation time 2949569904 ps
CPU time 78.78 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:33:10 PM PST 24
Peak memory 199636 kb
Host smart-03539dba-21e7-4277-86aa-bb2e86ab06fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2246577179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.2246577179
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2440503605
Short name T197
Test name
Test status
Simulation time 160845283 ps
CPU time 8.26 seconds
Started Feb 25 02:31:52 PM PST 24
Finished Feb 25 02:32:00 PM PST 24
Peak memory 199540 kb
Host smart-1ae2c831-159b-40cf-ad30-a88c539bb0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440503605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2440503605
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2337612961
Short name T590
Test name
Test status
Simulation time 13971375731 ps
CPU time 93.49 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:33:25 PM PST 24
Peak memory 199608 kb
Host smart-3bdd251f-c5fa-44a4-bf85-4bf3c52fb162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337612961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2337612961
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2061494516
Short name T230
Test name
Test status
Simulation time 242104537 ps
CPU time 3 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:31:54 PM PST 24
Peak memory 199568 kb
Host smart-5f2e534b-2e5c-4a76-ae08-74a150ef086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061494516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2061494516
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.774785284
Short name T317
Test name
Test status
Simulation time 8867988745 ps
CPU time 446.96 seconds
Started Feb 25 02:31:53 PM PST 24
Finished Feb 25 02:39:20 PM PST 24
Peak memory 199556 kb
Host smart-25332051-77c9-49fa-b596-afb464388637
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774785284 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.774785284
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.839369133
Short name T158
Test name
Test status
Simulation time 50471069 ps
CPU time 0.98 seconds
Started Feb 25 02:31:53 PM PST 24
Finished Feb 25 02:31:54 PM PST 24
Peak memory 196940 kb
Host smart-78199728-215a-4380-bc87-cc1aba2ebb89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839369133 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.839369133
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3368573358
Short name T533
Test name
Test status
Simulation time 57677938277 ps
CPU time 467.28 seconds
Started Feb 25 02:31:53 PM PST 24
Finished Feb 25 02:39:41 PM PST 24
Peak memory 199556 kb
Host smart-5985a93b-72f9-4692-9bc6-282ab5faa5d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368573358 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_sha_vectors.3368573358
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1770594244
Short name T593
Test name
Test status
Simulation time 17926582146 ps
CPU time 52.82 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:32:56 PM PST 24
Peak memory 199656 kb
Host smart-d2daffbc-7a05-4235-b4ba-8a2f567a63c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770594244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1770594244
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.3195112290
Short name T337
Test name
Test status
Simulation time 69793701 ps
CPU time 0.58 seconds
Started Feb 25 02:31:53 PM PST 24
Finished Feb 25 02:31:54 PM PST 24
Peak memory 194972 kb
Host smart-000e3d2f-f530-4421-9add-306bd8c0b96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195112290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.3195112290
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2682107496
Short name T234
Test name
Test status
Simulation time 376988911 ps
CPU time 13.92 seconds
Started Feb 25 02:31:54 PM PST 24
Finished Feb 25 02:32:08 PM PST 24
Peak memory 221232 kb
Host smart-ae368b48-a8bf-4530-816a-76e0756e378b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2682107496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2682107496
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2145786256
Short name T32
Test name
Test status
Simulation time 2178803458 ps
CPU time 28.71 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:32:19 PM PST 24
Peak memory 199644 kb
Host smart-cbd76b67-20e9-484d-bb5b-06ede808615f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145786256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2145786256
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.580749191
Short name T181
Test name
Test status
Simulation time 3734261706 ps
CPU time 50.87 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:32:41 PM PST 24
Peak memory 199612 kb
Host smart-e1b167ce-c3a9-4c27-a579-f836d5061648
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=580749191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.580749191
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.2222629061
Short name T432
Test name
Test status
Simulation time 19655996038 ps
CPU time 115.08 seconds
Started Feb 25 02:31:52 PM PST 24
Finished Feb 25 02:33:47 PM PST 24
Peak memory 199564 kb
Host smart-94992891-edcb-4923-9317-43d087ea7921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222629061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.2222629061
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.743002054
Short name T178
Test name
Test status
Simulation time 6289449318 ps
CPU time 89.27 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:33:20 PM PST 24
Peak memory 199664 kb
Host smart-80cd16a3-930c-480b-ba83-830c687624ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743002054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.743002054
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.558862812
Short name T553
Test name
Test status
Simulation time 3154176607 ps
CPU time 3.9 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:31:55 PM PST 24
Peak memory 199624 kb
Host smart-4051580f-4ecd-4737-80fe-4608572d0d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558862812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.558862812
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1840342935
Short name T380
Test name
Test status
Simulation time 10740149278 ps
CPU time 484.41 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:39:55 PM PST 24
Peak memory 224404 kb
Host smart-4af71c2f-eb5b-4741-bf46-279131206a2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840342935 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1840342935
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.383459514
Short name T577
Test name
Test status
Simulation time 52160147 ps
CPU time 1.19 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:31:51 PM PST 24
Peak memory 198344 kb
Host smart-d7791ae7-2cf5-4799-9d6f-fcaed2aec7a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383459514 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_hmac_vectors.383459514
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.1936280922
Short name T392
Test name
Test status
Simulation time 15934366216 ps
CPU time 406.26 seconds
Started Feb 25 02:31:54 PM PST 24
Finished Feb 25 02:38:41 PM PST 24
Peak memory 199592 kb
Host smart-228afdbc-6ee5-469f-923c-0cc118aed17d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936280922 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.1936280922
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.2228371623
Short name T117
Test name
Test status
Simulation time 2066568437 ps
CPU time 72.79 seconds
Started Feb 25 02:31:55 PM PST 24
Finished Feb 25 02:33:07 PM PST 24
Peak memory 199588 kb
Host smart-79245445-d189-4d0a-880c-e8c13dd56d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228371623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.2228371623
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2297812617
Short name T244
Test name
Test status
Simulation time 20467796 ps
CPU time 0.57 seconds
Started Feb 25 02:31:57 PM PST 24
Finished Feb 25 02:31:58 PM PST 24
Peak memory 193720 kb
Host smart-499c9133-e95f-4970-9752-d5516d2624fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297812617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2297812617
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3008890049
Short name T61
Test name
Test status
Simulation time 418852939 ps
CPU time 17.26 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:32:08 PM PST 24
Peak memory 199496 kb
Host smart-79439c7a-fadc-4e6b-8eea-6c135323a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008890049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3008890049
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1818421288
Short name T99
Test name
Test status
Simulation time 1506990415 ps
CPU time 40.72 seconds
Started Feb 25 02:31:55 PM PST 24
Finished Feb 25 02:32:36 PM PST 24
Peak memory 199556 kb
Host smart-b8db8c25-011b-4389-974b-7403b8d41dae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818421288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1818421288
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3593782117
Short name T477
Test name
Test status
Simulation time 12860061329 ps
CPU time 58.91 seconds
Started Feb 25 02:31:50 PM PST 24
Finished Feb 25 02:32:49 PM PST 24
Peak memory 199696 kb
Host smart-56d18105-0cef-4c98-bb72-b6bf061125d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593782117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3593782117
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3535935214
Short name T479
Test name
Test status
Simulation time 33996678950 ps
CPU time 116.61 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:34:00 PM PST 24
Peak memory 199432 kb
Host smart-762fbe63-3370-4791-9315-1341eaab9320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535935214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3535935214
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.573335608
Short name T419
Test name
Test status
Simulation time 1306306300 ps
CPU time 4.66 seconds
Started Feb 25 02:31:51 PM PST 24
Finished Feb 25 02:31:56 PM PST 24
Peak memory 199540 kb
Host smart-6630b5da-510c-40d1-b3eb-3f61fd37de20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573335608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.573335608
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3059934974
Short name T446
Test name
Test status
Simulation time 45900346910 ps
CPU time 537.58 seconds
Started Feb 25 02:32:02 PM PST 24
Finished Feb 25 02:41:00 PM PST 24
Peak memory 199680 kb
Host smart-125fc1ed-a794-4d07-8839-c2ec0bf224dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059934974 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3059934974
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2789532469
Short name T67
Test name
Test status
Simulation time 59710172 ps
CPU time 1.26 seconds
Started Feb 25 02:32:03 PM PST 24
Finished Feb 25 02:32:05 PM PST 24
Peak memory 198820 kb
Host smart-94cdebd2-e9b3-447c-a37f-07ddc35f036d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789532469 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2789532469
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.3066048632
Short name T165
Test name
Test status
Simulation time 7810155253 ps
CPU time 388.52 seconds
Started Feb 25 02:31:59 PM PST 24
Finished Feb 25 02:38:28 PM PST 24
Peak memory 199560 kb
Host smart-3c4c4f98-8eda-4f21-ab49-fece72f0db4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066048632 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.3066048632
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2696190131
Short name T439
Test name
Test status
Simulation time 540342868 ps
CPU time 7.25 seconds
Started Feb 25 02:31:54 PM PST 24
Finished Feb 25 02:32:02 PM PST 24
Peak memory 199544 kb
Host smart-5df02849-be8c-4f08-8bff-6e628199bea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696190131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2696190131
Directory /workspace/9.hmac_wipe_secret/latest

Test location /workspace/coverage/default/98.hmac_stress_all_with_rand_reset.3135753165
Short name T57
Test name
Test status
Simulation time 146589351129 ps
CPU time 3457.78 seconds
Started Feb 25 02:35:09 PM PST 24
Finished Feb 25 03:32:48 PM PST 24
Peak memory 257048 kb
Host smart-7cd5d1a5-b15c-40b7-9674-3a27a97150cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3135753165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.hmac_stress_all_with_rand_reset.3135753165
Directory /workspace/98.hmac_stress_all_with_rand_reset/latest
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