Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14558311	1			T2	191188		T3	13864		T4	138348
all_values[1]	14558311	1			T2	191188		T3	13864		T4	138348
all_values[2]	14558311	1			T2	191188		T3	13864		T4	138348

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126770

1

T2

193

T3

5

T5

25

auto[1]

43548163

1

T2

573371

T3

41587

T4

415044

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30741672

1

T2

367860

T3

36658

T4

269839

auto[1]

12933261

1

T2

205704

T3

4934

T4

145205

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38379	1			T2	2		T5	4		T31	18
all_values[0]	auto[0]	auto[1]	423	1			T2	1		T5	4		T31	4
all_values[0]	auto[1]	auto[0]	14471962	1			T2	190693		T3	13827		T4	137960
all_values[0]	auto[1]	auto[1]	47547	1			T2	492		T3	37		T4	388
all_values[1]	auto[0]	auto[0]	24866	1			T2	180		T3	4		T5	10
all_values[1]	auto[0]	auto[1]	15507	1			T2	4		T3	1		T17	6
all_values[1]	auto[1]	auto[0]	7713880	1			T2	95294		T3	8963		T4	56807
all_values[1]	auto[1]	auto[1]	6804058	1			T2	95710		T3	4896		T4	81541
all_values[2]	auto[0]	auto[0]	27391	1			T2	2		T5	4		T8	2
all_values[2]	auto[0]	auto[1]	20204	1			T2	4		T5	3		T50	11
all_values[2]	auto[1]	auto[0]	8465194	1			T2	81689		T3	13864		T4	75072
all_values[2]	auto[1]	auto[1]	6045522	1			T2	109493		T4	63276		T5	54815