Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.70	97.17	86.31	100.00	76.32	90.97	99.42

Total modules in report: 35

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NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
hmac	83.24	94.90	77.89	100.00	40.00	86.67	100.00
prim_sha2_32	83.33	100.00	66.67
tlul_adapter_sram	84.26	96.92	75.23			79.17	85.71
prim_sha2_pad	84.26	95.37	90.70		66.67	84.31
prim_fifo_sync	88.48	97.73	61.20			95.00	100.00
prim_fifo_sync	100.00						100.00
prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )	100.00	100.00
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	73.08		73.08
prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	95.00	100.00				90.00
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 )	94.12	100.00	88.24
prim_fifo_sync ( parameter Width=36,Pass=1,Depth=16,OutputZeroIfEmpty=1,Secure=0,DepthW=5,gen_normal_fifo.PTRV_W=4,gen_normal_fifo.PTR_WIDTH=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	100.00					100.00
prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	66.04	90.91	41.18
prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PTRV_W=1,gen_normal_fifo.PTR_WIDTH=2 )	42.31		42.31
prim_sha2	88.51	93.20	77.78		90.00	93.06
hmac_core	93.77	97.17	88.24		100.00	89.66
prim_packer	95.10	100.00	93.75			86.67	100.00
tlul_rsp_intg_gen	95.83	91.67					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	83.33	83.33
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
prim_fifo_sync_cnt	97.22	94.44				100.00
prim_fifo_sync_cnt	100.00					100.00
prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 )	88.89	88.89
prim_fifo_sync_cnt ( parameter Depth=16,Width=5,Secure=0 )	100.00	100.00
tlul_socket_1n	97.67	98.21	97.73			94.74	100.00
tlul_adapter_reg	98.91	100.00	95.65			100.00	100.00
hmac_reg_top	99.10	100.00	96.42			100.00	100.00
tlul_data_integ_dec	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
hmac_csr_assert_fpv	100.00						100.00
tlul_fifo_sync	100.00		100.00			100.00
tlul_assert	100.00	100.00				100.00	100.00
prim_onehot_check	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=3,RESVAL=0,Mubi=0 + DW=1,SwAccess=0,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_secded_inv_39_32_dec	100.00			100.00
prim_generic_buf	100.00	100.00
prim_intr_hw	100.00	100.00	100.00			100.00	100.00
prim_subreg_arb	100.00	100.00	100.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 )	100.00	100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
tlul_sram_byte	100.00	100.00
tlul_err	100.00	100.00	100.00			100.00	100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_secded_inv_64_57_dec	100.00			100.00
tlul_data_integ_enc
prim_reg_we_check
prim_buf
tb