Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7104812

1

T2

77756

T3

5481

T4

74681

auto[1]

2426330

1

T2

3882

T3

8145

T5

81692

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2489745

1

T2

4372

T3

7248

T5

74908

auto[1]

7041397

1

T2

77266

T3

6378

T4

74681

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6373251

1

T2

78830

T3

7642

T4

74681

auto[1]

3157891

1

T2

2808

T3

5984

T5

99228

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6262852	1			T2	78778		T3	4790		T4	72172
fifo_depth[1]	456502	1			T2	1954		T3	979		T4	1820
fifo_depth[2]	379595	1			T2	625		T3	1011		T4	544
fifo_depth[3]	308126	1			T2	178		T3	947		T4	120
fifo_depth[4]	287378	1			T2	72		T3	1003		T4	21
fifo_depth[5]	244804	1			T2	17		T3	942		T4	3
fifo_depth[6]	249294	1			T2	6		T3	948		T4	1
fifo_depth[7]	211884	1			T2	2		T3	922		T5	8046
fifo_depth[8]	235494	1			T2	5		T3	773		T5	9777
fifo_depth[9]	143181	1			T2	1		T3	574		T5	6329
fifo_depth[10]	136414	1			T3	365		T5	6915		T15	5
fifo_depth[11]	84007	1			T3	183		T5	4376		T15	3
fifo_depth[12]	128700	1			T3	107		T5	6050		T15	2
fifo_depth[13]	58733	1			T3	55		T5	3374		T15	3
fifo_depth[14]	91685	1			T3	17		T5	4966		T15	1
fifo_depth[15]	52325	1			T3	7		T5	2979		T15	1
fifo_depth[16]	200168	1			T3	3		T5	8871		T7	2

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3268290

1

T2

2860

T3

8836

T4

2509

auto[1]

6262852

1

T2

78778

T3

4790

T4

72172

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9330974

1

T2

81638

T3

13623

T4

74681

auto[1]

200168

1

T3

3

T5

8871

T7

2

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

225285

1

T2

78

T3

1460

T5

10747

auto[0]

auto[0]

auto[0]

auto[1]

201342

1

T2

88

T3

2441

T5

12882

auto[0]

auto[0]

auto[1]

auto[0]

1062455

1

T2

2518

T3

550

T4

2509

auto[0]

auto[0]

auto[1]

auto[1]

214690

1

T2

61

T3

407

T5

9914

auto[0]

auto[1]

auto[0]

auto[0]

419673

1

T2

18

T3

110

T5

11572

auto[0]

auto[1]

auto[0]

auto[1]

353650

1

T2

74

T3

582

T5

18919

auto[0]

auto[1]

auto[1]

auto[0]

384282

1

T2

10

T3

1402

T5

20809

auto[0]

auto[1]

auto[1]

auto[1]

406913

1

T2

13

T3

1884

T5

17486

auto[1]

auto[0]

auto[0]

auto[0]

250965

1

T2

1586

T3

895

T5

4193

auto[1]

auto[0]

auto[0]

auto[1]

231601

1

T2

781

T3

1375

T5

2560

auto[1]

auto[0]

auto[1]

auto[0]

3953424

1

T2

72637

T3

307

T4

72172

auto[1]

auto[0]

auto[1]

auto[1]

233489

1

T2

1081

T3

207

T5

3274

auto[1]

auto[1]

auto[0]

auto[0]

410820

1

T2

848

T3

50

T5

5809

auto[1]

auto[1]

auto[0]

auto[1]

396409

1

T2

899

T3

335

T5

8226

auto[1]

auto[1]

auto[1]

auto[0]

397908

1

T2

61

T3

707

T5

7976

auto[1]

auto[1]

auto[1]

auto[1]

388236

1

T2

885

T3

914

T5

8431

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

449503

1

T2

1664

T3

2355

T5

14515

auto[0]

auto[0]

auto[0]

auto[1]

413039

1

T2

869

T3

3816

T5

14411

auto[0]

auto[0]

auto[1]

auto[0]

4994029

1

T2

75155

T3

857

T4

74681

auto[0]

auto[0]

auto[1]

auto[1]

426504

1

T2

1142

T3

614

T5

11953

auto[0]

auto[1]

auto[0]

auto[0]

800217

1

T2

866

T3

160

T5

17284

auto[0]

auto[1]

auto[0]

auto[1]

726936

1

T2

973

T3

917

T5

26402

auto[0]

auto[1]

auto[1]

auto[0]

754880

1

T2

71

T3

2106

T5

26098

auto[0]

auto[1]

auto[1]

auto[1]

765866

1

T2

898

T3

2798

T5

24456

auto[1]

auto[0]

auto[0]

auto[0]

26747

1

T5

425

T8

1

T65

426

auto[1]

auto[0]

auto[0]

auto[1]

19904

1

T5

1031

T64

293

T65

481

auto[1]

auto[0]

auto[1]

auto[0]

21850

1

T5

1192

T7

2

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

21675

1

T5

1235

T65

207

T40

1

auto[1]

auto[1]

auto[0]

auto[0]

30276

1

T5

97

T8

1

T64

109

auto[1]

auto[1]

auto[0]

auto[1]

23123

1

T5

743

T8

1

T64

567

auto[1]

auto[1]

auto[1]

auto[0]

27310

1

T3

3

T5

2687

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

29283

1

T5

1461

T8

1

T64

158

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	250965	1			T2	1586		T3	895		T5	4193
fifo_depth[0]	auto[0]	auto[0]	auto[1]	231601	1			T2	781		T3	1375		T5	2560
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3953424	1			T2	72637		T3	307		T4	72172
fifo_depth[0]	auto[0]	auto[1]	auto[1]	233489	1			T2	1081		T3	207		T5	3274
fifo_depth[0]	auto[1]	auto[0]	auto[0]	410820	1			T2	848		T3	50		T5	5809
fifo_depth[0]	auto[1]	auto[0]	auto[1]	396409	1			T2	899		T3	335		T5	8226
fifo_depth[0]	auto[1]	auto[1]	auto[0]	397908	1			T2	61		T3	707		T5	7976
fifo_depth[0]	auto[1]	auto[1]	auto[1]	388236	1			T2	885		T3	914		T5	8431
fifo_depth[1]	auto[0]	auto[0]	auto[0]	19947	1			T2	32		T3	175		T5	625
fifo_depth[1]	auto[0]	auto[0]	auto[1]	18324	1			T2	37		T3	273		T5	368
fifo_depth[1]	auto[0]	auto[1]	auto[0]	232217	1			T2	1772		T3	65		T4	1820
fifo_depth[1]	auto[0]	auto[1]	auto[1]	17312	1			T2	41		T3	44		T5	235
fifo_depth[1]	auto[1]	auto[0]	auto[0]	44076	1			T2	15		T3	9		T5	1076
fifo_depth[1]	auto[1]	auto[0]	auto[1]	40376	1			T2	43		T3	68		T5	1598
fifo_depth[1]	auto[1]	auto[1]	auto[0]	42187	1			T2	4		T3	139		T5	1669
fifo_depth[1]	auto[1]	auto[1]	auto[1]	42063	1			T2	10		T3	206		T5	1427
fifo_depth[2]	auto[0]	auto[0]	auto[0]	17574	1			T2	11		T3	151		T5	642
fifo_depth[2]	auto[0]	auto[0]	auto[1]	15861	1			T2	27		T3	277		T5	515
fifo_depth[2]	auto[0]	auto[1]	auto[0]	178628	1			T2	543		T3	63		T4	544
fifo_depth[2]	auto[0]	auto[1]	auto[1]	16048	1			T2	17		T3	47		T5	287
fifo_depth[2]	auto[1]	auto[0]	auto[0]	40337	1			T2	2		T3	9		T5	1062
fifo_depth[2]	auto[1]	auto[0]	auto[1]	35436	1			T2	22		T3	69		T5	1634
fifo_depth[2]	auto[1]	auto[1]	auto[0]	37768	1			T2	1		T3	159		T5	1659
fifo_depth[2]	auto[1]	auto[1]	auto[1]	37943	1			T2	2		T3	236		T5	1458
fifo_depth[3]	auto[0]	auto[0]	auto[0]	14462	1			T2	7		T3	156		T5	653
fifo_depth[3]	auto[0]	auto[0]	auto[1]	13550	1			T2	10		T3	269		T5	509
fifo_depth[3]	auto[0]	auto[1]	auto[0]	134783	1			T2	150		T3	57		T4	120
fifo_depth[3]	auto[0]	auto[1]	auto[1]	13140	1			T2	3		T3	52		T5	314
fifo_depth[3]	auto[1]	auto[0]	auto[0]	34978	1			T3	14		T5	1051		T15	4
fifo_depth[3]	auto[1]	auto[0]	auto[1]	30536	1			T2	5		T3	61		T5	1595
fifo_depth[3]	auto[1]	auto[1]	auto[0]	33101	1			T2	3		T3	146		T5	1638
fifo_depth[3]	auto[1]	auto[1]	auto[1]	33576	1			T3	192		T5	1524		T15	2
fifo_depth[4]	auto[0]	auto[0]	auto[0]	16928	1			T2	18		T3	163		T5	1227
fifo_depth[4]	auto[0]	auto[0]	auto[1]	15807	1			T2	7		T3	263		T5	915
fifo_depth[4]	auto[0]	auto[1]	auto[0]	101349	1			T2	42		T3	57		T4	21
fifo_depth[4]	auto[0]	auto[1]	auto[1]	15824	1			T3	45		T5	573		T6	1
fifo_depth[4]	auto[1]	auto[0]	auto[0]	37022	1			T2	1		T3	12		T5	1049
fifo_depth[4]	auto[1]	auto[0]	auto[1]	31491	1			T2	3		T3	67		T5	1795
fifo_depth[4]	auto[1]	auto[1]	auto[0]	33544	1			T2	1		T3	171		T5	1648
fifo_depth[4]	auto[1]	auto[1]	auto[1]	35413	1			T3	225		T5	1609		T15	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	13686	1			T2	3		T3	162		T5	866
fifo_depth[5]	auto[0]	auto[0]	auto[1]	12692	1			T2	3		T3	253		T5	749
fifo_depth[5]	auto[0]	auto[1]	auto[0]	83313	1			T2	10		T3	59		T4	3
fifo_depth[5]	auto[0]	auto[1]	auto[1]	12512	1			T3	47		T5	442		T17	42
fifo_depth[5]	auto[1]	auto[0]	auto[0]	33108	1			T3	15		T5	1032		T15	7
fifo_depth[5]	auto[1]	auto[0]	auto[1]	27779	1			T2	1		T3	69		T5	1540
fifo_depth[5]	auto[1]	auto[1]	auto[0]	29995	1			T3	149		T5	1607		T17	26
fifo_depth[5]	auto[1]	auto[1]	auto[1]	31719	1			T3	188		T5	1526		T15	1
fifo_depth[6]	auto[0]	auto[0]	auto[0]	16062	1			T2	1		T3	168		T5	1132
fifo_depth[6]	auto[0]	auto[0]	auto[1]	14970	1			T2	3		T3	257		T5	921
fifo_depth[6]	auto[0]	auto[1]	auto[0]	74562	1			T2	1		T3	54		T4	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	15017	1			T3	33		T5	612		T17	28
fifo_depth[6]	auto[1]	auto[0]	auto[0]	34620	1			T3	7		T5	1244		T15	4
fifo_depth[6]	auto[1]	auto[0]	auto[1]	29401	1			T3	75		T5	1706		T6	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	31327	1			T2	1		T3	159		T5	1621
fifo_depth[6]	auto[1]	auto[1]	auto[1]	33335	1			T3	195		T5	1604		T15	1
fifo_depth[7]	auto[0]	auto[0]	auto[0]	13625	1			T2	1		T3	145		T5	781
fifo_depth[7]	auto[0]	auto[0]	auto[1]	12235	1			T2	1		T3	288		T5	735
fifo_depth[7]	auto[0]	auto[1]	auto[0]	59357	1			T3	59		T5	684		T17	4
fifo_depth[7]	auto[0]	auto[1]	auto[1]	12264	1			T3	42		T5	530		T17	21
fifo_depth[7]	auto[1]	auto[0]	auto[0]	31169	1			T3	12		T5	1129		T15	3
fifo_depth[7]	auto[1]	auto[0]	auto[1]	25743	1			T3	58		T5	1390		T15	3
fifo_depth[7]	auto[1]	auto[1]	auto[0]	28044	1			T3	146		T5	1473		T15	2
fifo_depth[7]	auto[1]	auto[1]	auto[1]	29447	1			T3	172		T5	1324		T15	2
fifo_depth[8]	auto[0]	auto[0]	auto[0]	18475	1			T2	5		T3	123		T5	1038
fifo_depth[8]	auto[0]	auto[0]	auto[1]	18613	1			T3	227		T5	1368		T17	6
fifo_depth[8]	auto[0]	auto[1]	auto[0]	51452	1			T3	45		T5	1020		T17	1
fifo_depth[8]	auto[0]	auto[1]	auto[1]	17584	1			T3	38		T5	804		T17	14
fifo_depth[8]	auto[1]	auto[0]	auto[0]	34506	1			T3	10		T5	1003		T17	9
fifo_depth[8]	auto[1]	auto[0]	auto[1]	29386	1			T3	37		T5	1498		T15	1
fifo_depth[8]	auto[1]	auto[1]	auto[0]	29808	1			T3	132		T5	1330		T17	28
fifo_depth[8]	auto[1]	auto[1]	auto[1]	35670	1			T3	161		T5	1716		T15	2
fifo_depth[9]	auto[0]	auto[0]	auto[0]	10658	1			T3	95		T5	632		T17	1
fifo_depth[9]	auto[0]	auto[0]	auto[1]	9945	1			T3	162		T5	1109		T8	1
fifo_depth[9]	auto[0]	auto[1]	auto[0]	32458	1			T3	41		T5	463		T7	203
fifo_depth[9]	auto[0]	auto[1]	auto[1]	9895	1			T3	24		T5	382		T17	7
fifo_depth[9]	auto[1]	auto[0]	auto[0]	22524	1			T3	9		T5	824		T64	68
fifo_depth[9]	auto[1]	auto[0]	auto[1]	17739	1			T3	34		T5	966		T15	1
fifo_depth[9]	auto[1]	auto[1]	auto[0]	19716	1			T3	76		T5	1056		T15	1
fifo_depth[9]	auto[1]	auto[1]	auto[1]	20246	1			T2	1		T3	133		T5	897
fifo_depth[10]	auto[0]	auto[0]	auto[0]	11359	1			T3	65		T5	756		T17	3
fifo_depth[10]	auto[0]	auto[0]	auto[1]	10984	1			T3	91		T5	974		T17	4
fifo_depth[10]	auto[0]	auto[1]	auto[0]	26377	1			T3	20		T5	651		T7	120
fifo_depth[10]	auto[0]	auto[1]	auto[1]	11949	1			T3	20		T5	489		T17	5
fifo_depth[10]	auto[1]	auto[0]	auto[0]	21172	1			T3	6		T5	621		T15	1
fifo_depth[10]	auto[1]	auto[0]	auto[1]	16385	1			T3	21		T5	1324		T15	3
fifo_depth[10]	auto[1]	auto[1]	auto[0]	17598	1			T3	56		T5	1095		T15	1
fifo_depth[10]	auto[1]	auto[1]	auto[1]	20590	1			T3	86		T5	1005		T17	1
fifo_depth[11]	auto[0]	auto[0]	auto[0]	7517	1			T3	19		T5	408		T17	2
fifo_depth[11]	auto[0]	auto[0]	auto[1]	6573	1			T3	45		T5	870		T64	9
fifo_depth[11]	auto[0]	auto[1]	auto[0]	15994	1			T3	19		T5	390		T7	65
fifo_depth[11]	auto[0]	auto[1]	auto[1]	7747	1			T3	12		T5	324		T65	13
fifo_depth[11]	auto[1]	auto[0]	auto[0]	13358	1			T3	4		T5	468		T17	1
fifo_depth[11]	auto[1]	auto[0]	auto[1]	9842	1			T3	11		T5	810		T15	2
fifo_depth[11]	auto[1]	auto[1]	auto[0]	11512	1			T3	32		T5	749		T15	1
fifo_depth[11]	auto[1]	auto[1]	auto[1]	11464	1			T3	41		T5	357		T64	94
fifo_depth[12]	auto[0]	auto[0]	auto[0]	14689	1			T3	22		T5	586		T65	129
fifo_depth[12]	auto[0]	auto[0]	auto[1]	13182	1			T3	19		T5	902		T8	1
fifo_depth[12]	auto[0]	auto[1]	auto[0]	19198	1			T3	7		T5	876		T7	37
fifo_depth[12]	auto[0]	auto[1]	auto[1]	15503	1			T3	3		T5	1023		T8	1
fifo_depth[12]	auto[1]	auto[0]	auto[0]	17176	1			T3	2		T5	300		T15	1
fifo_depth[12]	auto[1]	auto[0]	auto[1]	15875	1			T3	9		T5	837		T64	76
fifo_depth[12]	auto[1]	auto[1]	auto[0]	14995	1			T3	18		T5	765		T64	83
fifo_depth[12]	auto[1]	auto[1]	auto[1]	18082	1			T3	27		T5	761		T15	1
fifo_depth[13]	auto[0]	auto[0]	auto[0]	6606	1			T3	12		T5	332		T65	96
fifo_depth[13]	auto[0]	auto[0]	auto[1]	5131	1			T3	11		T5	688		T8	1
fifo_depth[13]	auto[0]	auto[1]	auto[0]	10052	1			T3	4		T5	271		T7	17
fifo_depth[13]	auto[0]	auto[1]	auto[1]	6723	1			T5	455		T65	8		T44	7
fifo_depth[13]	auto[1]	auto[0]	auto[0]	8274	1			T3	1		T5	260		T15	2
fifo_depth[13]	auto[1]	auto[0]	auto[1]	5463	1			T3	3		T5	516		T64	47
fifo_depth[13]	auto[1]	auto[1]	auto[0]	8807	1			T3	11		T5	664		T15	1
fifo_depth[13]	auto[1]	auto[1]	auto[1]	7677	1			T3	13		T5	188		T64	77
fifo_depth[14]	auto[0]	auto[0]	auto[0]	10797	1			T3	3		T5	411		T65	84
fifo_depth[14]	auto[0]	auto[0]	auto[1]	8939	1			T3	4		T5	677		T64	10
fifo_depth[14]	auto[0]	auto[1]	auto[0]	13122	1			T5	586		T7	6		T126	7
fifo_depth[14]	auto[0]	auto[1]	auto[1]	13627	1			T5	1267		T65	7		T38	1
fifo_depth[14]	auto[1]	auto[0]	auto[0]	11200	1			T5	203		T64	202		T65	35
fifo_depth[14]	auto[1]	auto[0]	auto[1]	10215	1			T5	680		T8	1		T64	152
fifo_depth[14]	auto[1]	auto[1]	auto[0]	10819	1			T3	4		T5	653		T15	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	12966	1			T3	6		T5	489		T64	71
fifo_depth[15]	auto[0]	auto[0]	auto[0]	6153	1			T3	1		T5	233		T8	1
fifo_depth[15]	auto[0]	auto[0]	auto[1]	4632	1			T3	2		T5	551		T8	2
fifo_depth[15]	auto[0]	auto[1]	auto[0]	7743	1			T5	178		T7	4		T8	1
fifo_depth[15]	auto[0]	auto[1]	auto[1]	7870	1			T5	942		T8	2		T65	8
fifo_depth[15]	auto[1]	auto[0]	auto[0]	5877	1			T5	153		T8	1		T64	188
fifo_depth[15]	auto[1]	auto[0]	auto[1]	4860	1			T5	287		T8	1		T64	82
fifo_depth[15]	auto[1]	auto[1]	auto[0]	7751	1			T3	1		T5	495		T15	1
fifo_depth[15]	auto[1]	auto[1]	auto[1]	7439	1			T3	3		T5	140		T64	67
fifo_depth[16]	auto[0]	auto[0]	auto[0]	26747	1			T5	425		T8	1		T65	426
fifo_depth[16]	auto[0]	auto[0]	auto[1]	19904	1			T5	1031		T64	293		T65	481
fifo_depth[16]	auto[0]	auto[1]	auto[0]	21850	1			T5	1192		T7	2		T8	1
fifo_depth[16]	auto[0]	auto[1]	auto[1]	21675	1			T5	1235		T65	207		T40	1
fifo_depth[16]	auto[1]	auto[0]	auto[0]	30276	1			T5	97		T8	1		T64	109
fifo_depth[16]	auto[1]	auto[0]	auto[1]	23123	1			T5	743		T8	1		T64	567
fifo_depth[16]	auto[1]	auto[1]	auto[0]	27310	1			T3	3		T5	2687		T8	1
fifo_depth[16]	auto[1]	auto[1]	auto[1]	29283	1			T5	1461		T8	1		T64	158