Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14558311	1			T2	191188		T3	13864		T4	138348
all_pins[1]	14558311	1			T2	191188		T3	13864		T4	138348
all_pins[2]	14558311	1			T2	191188		T3	13864		T4	138348

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30713272	1			T2	367602		T3	36508		T4	269566
values[0x1]	12961661	1			T2	205962		T3	5084		T4	145478
transitions[0x0=>0x1]	11242169	1			T2	170559		T3	5054		T4	122459
transitions[0x1=>0x0]	11242187	1			T2	170559		T3	5054		T4	122459

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14509808	1			T2	190693		T3	13826		T4	137960
all_pins[0]	values[0x1]	48503	1			T2	495		T3	38		T4	388
all_pins[0]	transitions[0x0=>0x1]	48442	1			T2	495		T3	38		T4	388
all_pins[0]	transitions[0x1=>0x0]	6045479	1			T2	109493		T4	63276		T5	54815
all_pins[1]	values[0x0]	7690675	1			T2	95214		T3	8818		T4	56534
all_pins[1]	values[0x1]	6867636	1			T2	95974		T3	5046		T4	81814
all_pins[1]	transitions[0x0=>0x1]	6829677	1			T2	95615		T3	5016		T4	81525
all_pins[1]	transitions[0x1=>0x0]	10544	1			T2	136		T3	8		T4	99
all_pins[2]	values[0x0]	8512789	1			T2	81695		T3	13864		T4	75072
all_pins[2]	values[0x1]	6045522	1			T2	109493		T4	63276		T5	54815
all_pins[2]	transitions[0x0=>0x1]	4364050	1			T2	74449		T4	40546		T5	51028
all_pins[2]	transitions[0x1=>0x0]	5186164	1			T2	60930		T3	5046		T4	59084