Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 898 1 T2 10 T5 10 T50 44
all_values[1] 898 1 T2 10 T5 10 T50 44
all_values[2] 898 1 T2 10 T5 10 T50 44


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1369 1 T2 14 T5 19 T50 50
auto[1] 1325 1 T2 16 T5 11 T50 82


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 993 1 T2 11 T5 11 T50 47
auto[1] 1701 1 T2 19 T5 19 T50 85


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1552 1 T2 19 T5 17 T50 72
auto[1] 1142 1 T2 11 T5 13 T50 60


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 179 1 T2 2 T5 1 T50 8
all_values[0] auto[0] auto[0] auto[1] 93 1 T5 2 T50 2 T11 1
all_values[0] auto[0] auto[1] auto[0] 173 1 T2 5 T5 2 T50 4
all_values[0] auto[0] auto[1] auto[1] 80 1 T5 1 T50 4 T11 3
all_values[0] auto[1] auto[0] auto[1] 178 1 T2 1 T5 1 T50 9
all_values[0] auto[1] auto[1] auto[1] 195 1 T2 2 T5 3 T50 17
all_values[1] auto[0] auto[0] auto[0] 170 1 T5 3 T50 6 T11 1
all_values[1] auto[0] auto[0] auto[1] 88 1 T2 2 T50 2 T11 1
all_values[1] auto[0] auto[1] auto[0] 153 1 T2 1 T5 2 T50 14
all_values[1] auto[0] auto[1] auto[1] 106 1 T2 2 T50 5 T11 6
all_values[1] auto[1] auto[0] auto[1] 189 1 T2 3 T5 5 T50 4
all_values[1] auto[1] auto[1] auto[1] 192 1 T2 2 T50 13 T11 9
all_values[2] auto[0] auto[0] auto[0] 176 1 T2 2 T5 1 T50 9
all_values[2] auto[0] auto[0] auto[1] 103 1 T2 3 T5 2 T50 3
all_values[2] auto[0] auto[1] auto[0] 142 1 T2 1 T5 2 T50 6
all_values[2] auto[0] auto[1] auto[1] 89 1 T2 1 T5 1 T50 9
all_values[2] auto[1] auto[0] auto[1] 193 1 T2 1 T5 4 T50 7
all_values[2] auto[1] auto[1] auto[1] 195 1 T2 2 T50 10 T11 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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