Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.70 98.36 96.53 100.00 87.50 95.83 99.49 99.17


Total test records in report: 725
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T544 /workspace/coverage/default/4.hmac_alert_test.3407239326 Feb 29 12:57:28 PM PST 24 Feb 29 12:57:29 PM PST 24 12862502 ps
T545 /workspace/coverage/default/33.hmac_wipe_secret.2006331304 Feb 29 12:58:30 PM PST 24 Feb 29 12:58:57 PM PST 24 2113726968 ps
T546 /workspace/coverage/default/1.hmac_stress_all.3409723694 Feb 29 12:57:45 PM PST 24 Feb 29 01:18:18 PM PST 24 26596116221 ps
T547 /workspace/coverage/default/41.hmac_alert_test.2965449017 Feb 29 12:58:13 PM PST 24 Feb 29 12:58:14 PM PST 24 13573677 ps
T55 /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2223006763 Feb 29 12:58:59 PM PST 24 Feb 29 01:07:27 PM PST 24 36216084026 ps
T548 /workspace/coverage/default/43.hmac_wipe_secret.3880223066 Feb 29 12:58:28 PM PST 24 Feb 29 12:59:41 PM PST 24 3334978083 ps
T103 /workspace/coverage/default/4.hmac_back_pressure.3831922536 Feb 29 12:57:42 PM PST 24 Feb 29 12:58:12 PM PST 24 3946360935 ps
T22 /workspace/coverage/default/4.hmac_sec_cm.147672687 Feb 29 12:57:36 PM PST 24 Feb 29 12:57:37 PM PST 24 163354105 ps
T549 /workspace/coverage/default/13.hmac_wipe_secret.288012585 Feb 29 12:57:37 PM PST 24 Feb 29 12:58:32 PM PST 24 6158711416 ps
T550 /workspace/coverage/default/47.hmac_burst_wr.1373587819 Feb 29 12:58:49 PM PST 24 Feb 29 12:59:37 PM PST 24 3809017515 ps
T551 /workspace/coverage/default/28.hmac_error.2597901495 Feb 29 12:57:58 PM PST 24 Feb 29 01:00:14 PM PST 24 49644336364 ps
T552 /workspace/coverage/default/38.hmac_stress_all.2738985551 Feb 29 12:58:24 PM PST 24 Feb 29 01:03:31 PM PST 24 100492129505 ps
T107 /workspace/coverage/default/32.hmac_stress_all.1247925760 Feb 29 12:58:19 PM PST 24 Feb 29 01:27:49 PM PST 24 140490356634 ps
T553 /workspace/coverage/default/19.hmac_test_sha_vectors.877495158 Feb 29 12:57:44 PM PST 24 Feb 29 01:05:28 PM PST 24 152705340302 ps
T554 /workspace/coverage/default/40.hmac_error.3686849528 Feb 29 12:58:22 PM PST 24 Feb 29 12:59:45 PM PST 24 5088941967 ps
T555 /workspace/coverage/default/45.hmac_burst_wr.1752083580 Feb 29 12:58:43 PM PST 24 Feb 29 12:58:56 PM PST 24 514286860 ps
T556 /workspace/coverage/default/8.hmac_test_hmac_vectors.2257468287 Feb 29 12:57:47 PM PST 24 Feb 29 12:57:48 PM PST 24 88704648 ps
T557 /workspace/coverage/default/13.hmac_datapath_stress.1634143893 Feb 29 12:57:41 PM PST 24 Feb 29 12:59:05 PM PST 24 1655644267 ps
T558 /workspace/coverage/default/43.hmac_test_sha_vectors.1475504455 Feb 29 12:59:58 PM PST 24 Feb 29 01:07:06 PM PST 24 56157396531 ps
T559 /workspace/coverage/default/7.hmac_test_hmac_vectors.1019587628 Feb 29 12:57:47 PM PST 24 Feb 29 12:57:48 PM PST 24 41678636 ps
T560 /workspace/coverage/default/15.hmac_error.2379252791 Feb 29 12:57:38 PM PST 24 Feb 29 12:59:24 PM PST 24 4374977163 ps
T561 /workspace/coverage/default/18.hmac_alert_test.2459005709 Feb 29 12:57:48 PM PST 24 Feb 29 12:57:48 PM PST 24 24600833 ps
T562 /workspace/coverage/default/17.hmac_stress_all.2613452845 Feb 29 12:57:48 PM PST 24 Feb 29 12:58:02 PM PST 24 2108228910 ps
T563 /workspace/coverage/default/9.hmac_test_hmac_vectors.2218012786 Feb 29 12:57:51 PM PST 24 Feb 29 12:57:52 PM PST 24 25859352 ps
T564 /workspace/coverage/default/25.hmac_burst_wr.1217540019 Feb 29 12:58:00 PM PST 24 Feb 29 12:58:06 PM PST 24 315391316 ps
T565 /workspace/coverage/default/9.hmac_stress_all.2309038753 Feb 29 12:57:59 PM PST 24 Feb 29 01:29:16 PM PST 24 74735138384 ps
T566 /workspace/coverage/default/20.hmac_back_pressure.1504777337 Feb 29 12:57:48 PM PST 24 Feb 29 12:58:06 PM PST 24 1041781516 ps
T567 /workspace/coverage/default/21.hmac_smoke.3340233410 Feb 29 12:58:03 PM PST 24 Feb 29 12:58:07 PM PST 24 1231649848 ps
T568 /workspace/coverage/default/17.hmac_burst_wr.1153066750 Feb 29 12:58:07 PM PST 24 Feb 29 12:58:28 PM PST 24 436138463 ps
T569 /workspace/coverage/default/48.hmac_smoke.1946590737 Feb 29 12:58:48 PM PST 24 Feb 29 12:58:52 PM PST 24 310734761 ps
T570 /workspace/coverage/default/2.hmac_smoke.1583145048 Feb 29 12:57:42 PM PST 24 Feb 29 12:57:45 PM PST 24 245619747 ps
T571 /workspace/coverage/default/6.hmac_error.867607807 Feb 29 12:57:42 PM PST 24 Feb 29 12:57:55 PM PST 24 2337247203 ps
T572 /workspace/coverage/default/11.hmac_alert_test.3289354015 Feb 29 12:57:49 PM PST 24 Feb 29 12:57:50 PM PST 24 13164437 ps
T573 /workspace/coverage/default/9.hmac_wipe_secret.3217370260 Feb 29 12:57:45 PM PST 24 Feb 29 12:58:24 PM PST 24 11639528127 ps
T574 /workspace/coverage/default/25.hmac_datapath_stress.1995508669 Feb 29 12:58:23 PM PST 24 Feb 29 12:59:31 PM PST 24 1166769006 ps
T575 /workspace/coverage/default/42.hmac_test_hmac_vectors.2973025400 Feb 29 12:58:18 PM PST 24 Feb 29 12:58:20 PM PST 24 49778659 ps
T576 /workspace/coverage/default/27.hmac_test_hmac_vectors.3027003683 Feb 29 12:58:20 PM PST 24 Feb 29 12:58:22 PM PST 24 156207076 ps
T577 /workspace/coverage/default/26.hmac_back_pressure.746876464 Feb 29 12:57:53 PM PST 24 Feb 29 12:58:10 PM PST 24 1729973311 ps
T578 /workspace/coverage/default/27.hmac_test_sha_vectors.1049293457 Feb 29 12:58:28 PM PST 24 Feb 29 01:05:59 PM PST 24 28074579378 ps
T579 /workspace/coverage/default/4.hmac_smoke.2839876861 Feb 29 12:57:34 PM PST 24 Feb 29 12:57:39 PM PST 24 686936906 ps
T580 /workspace/coverage/default/26.hmac_test_hmac_vectors.3296259587 Feb 29 12:58:04 PM PST 24 Feb 29 12:58:05 PM PST 24 332154484 ps
T581 /workspace/coverage/default/33.hmac_test_sha_vectors.530318607 Feb 29 12:58:19 PM PST 24 Feb 29 01:05:29 PM PST 24 182067086989 ps
T582 /workspace/coverage/default/44.hmac_burst_wr.3348681034 Feb 29 12:58:38 PM PST 24 Feb 29 12:59:23 PM PST 24 6114443795 ps
T583 /workspace/coverage/default/20.hmac_error.2959995360 Feb 29 12:57:53 PM PST 24 Feb 29 01:00:34 PM PST 24 24680061598 ps
T584 /workspace/coverage/default/10.hmac_alert_test.771044131 Feb 29 12:57:50 PM PST 24 Feb 29 12:57:51 PM PST 24 13297514 ps
T112 /workspace/coverage/default/33.hmac_datapath_stress.37654703 Feb 29 12:58:16 PM PST 24 Feb 29 12:59:29 PM PST 24 5052160586 ps
T585 /workspace/coverage/default/32.hmac_smoke.17629710 Feb 29 12:58:24 PM PST 24 Feb 29 12:58:28 PM PST 24 1479599376 ps
T586 /workspace/coverage/default/16.hmac_wipe_secret.2354483269 Feb 29 12:57:46 PM PST 24 Feb 29 12:58:39 PM PST 24 11971297887 ps
T587 /workspace/coverage/default/18.hmac_back_pressure.859392590 Feb 29 12:57:48 PM PST 24 Feb 29 12:57:49 PM PST 24 53918024 ps
T588 /workspace/coverage/default/29.hmac_test_sha_vectors.2780500148 Feb 29 12:58:09 PM PST 24 Feb 29 01:05:34 PM PST 24 26399217291 ps
T589 /workspace/coverage/default/31.hmac_alert_test.3552809722 Feb 29 12:58:20 PM PST 24 Feb 29 12:58:21 PM PST 24 28265847 ps
T590 /workspace/coverage/default/7.hmac_datapath_stress.4245019798 Feb 29 12:57:50 PM PST 24 Feb 29 12:59:50 PM PST 24 8832308964 ps
T591 /workspace/coverage/default/7.hmac_burst_wr.1020540679 Feb 29 12:57:39 PM PST 24 Feb 29 12:58:37 PM PST 24 4039789327 ps
T592 /workspace/coverage/default/21.hmac_test_sha_vectors.302404620 Feb 29 12:58:03 PM PST 24 Feb 29 01:04:28 PM PST 24 28955447488 ps
T593 /workspace/coverage/default/3.hmac_error.585497044 Feb 29 12:57:42 PM PST 24 Feb 29 12:59:44 PM PST 24 8292044256 ps
T594 /workspace/coverage/default/37.hmac_stress_all.2157499769 Feb 29 12:58:18 PM PST 24 Feb 29 01:18:29 PM PST 24 71648972385 ps
T595 /workspace/coverage/default/44.hmac_wipe_secret.4191415959 Feb 29 12:58:47 PM PST 24 Feb 29 12:59:48 PM PST 24 15549758992 ps
T596 /workspace/coverage/default/10.hmac_error.4083520122 Feb 29 12:57:59 PM PST 24 Feb 29 01:00:05 PM PST 24 37843847227 ps
T597 /workspace/coverage/default/9.hmac_burst_wr.2687611614 Feb 29 12:57:31 PM PST 24 Feb 29 12:57:34 PM PST 24 393151777 ps
T109 /workspace/coverage/default/45.hmac_stress_all.2122334561 Feb 29 12:58:37 PM PST 24 Feb 29 01:12:16 PM PST 24 63158174012 ps
T51 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2939515695 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 151869028 ps
T598 /workspace/coverage/cover_reg_top/15.hmac_intr_test.3549853870 Feb 29 12:44:36 PM PST 24 Feb 29 12:44:37 PM PST 24 42762099 ps
T599 /workspace/coverage/cover_reg_top/0.hmac_intr_test.178222413 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:10 PM PST 24 65778655 ps
T600 /workspace/coverage/cover_reg_top/9.hmac_intr_test.764095184 Feb 29 12:44:15 PM PST 24 Feb 29 12:44:16 PM PST 24 16635143 ps
T52 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.115085229 Feb 29 12:44:19 PM PST 24 Feb 29 12:44:21 PM PST 24 112929259 ps
T53 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2852020285 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 51453475 ps
T601 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.615482706 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:25 PM PST 24 424330980 ps
T47 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.251696365 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:27 PM PST 24 147942364 ps
T602 /workspace/coverage/cover_reg_top/12.hmac_intr_test.3689454393 Feb 29 12:44:49 PM PST 24 Feb 29 12:44:50 PM PST 24 16484019 ps
T48 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1596436363 Feb 29 12:44:19 PM PST 24 Feb 29 12:44:21 PM PST 24 262525584 ps
T603 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3994748038 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 58806118 ps
T604 /workspace/coverage/cover_reg_top/36.hmac_intr_test.2177624747 Feb 29 12:44:39 PM PST 24 Feb 29 12:44:40 PM PST 24 20516711 ps
T605 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3084370409 Feb 29 12:44:45 PM PST 24 Feb 29 12:44:45 PM PST 24 90727204 ps
T606 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1199646026 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:24 PM PST 24 215157913 ps
T607 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2962978744 Feb 29 12:44:22 PM PST 24 Feb 29 12:44:23 PM PST 24 151257032 ps
T608 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2832084200 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:15 PM PST 24 290814500 ps
T609 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2548230301 Feb 29 12:44:33 PM PST 24 Feb 29 12:44:34 PM PST 24 15687284 ps
T610 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2271470246 Feb 29 12:44:49 PM PST 24 Feb 29 12:44:50 PM PST 24 101525351 ps
T49 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1350918971 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:27 PM PST 24 58007349 ps
T611 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2746207669 Feb 29 12:44:21 PM PST 24 Feb 29 01:01:07 PM PST 24 233021149725 ps
T612 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3055727729 Feb 29 12:44:38 PM PST 24 Feb 29 12:44:39 PM PST 24 204138996 ps
T613 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3375049882 Feb 29 12:44:29 PM PST 24 Feb 29 12:44:31 PM PST 24 108330349 ps
T614 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1470630450 Feb 29 12:44:28 PM PST 24 Feb 29 12:44:32 PM PST 24 70970320 ps
T113 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1077237506 Feb 29 12:44:40 PM PST 24 Feb 29 12:44:41 PM PST 24 45320004 ps
T66 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.686785593 Feb 29 12:44:38 PM PST 24 Feb 29 12:44:39 PM PST 24 40541750 ps
T615 /workspace/coverage/cover_reg_top/35.hmac_intr_test.454892585 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:26 PM PST 24 195331133 ps
T616 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3606372248 Feb 29 12:44:35 PM PST 24 Feb 29 12:44:36 PM PST 24 53885934 ps
T617 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2766385725 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:14 PM PST 24 47877382 ps
T618 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.571534435 Feb 29 12:44:43 PM PST 24 Feb 29 12:50:18 PM PST 24 32763308270 ps
T619 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3578764474 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:26 PM PST 24 51310048 ps
T67 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2181066044 Feb 29 12:44:35 PM PST 24 Feb 29 12:44:35 PM PST 24 17989931 ps
T620 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063647229 Feb 29 12:44:27 PM PST 24 Feb 29 12:44:28 PM PST 24 113084578 ps
T68 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3847737619 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:12 PM PST 24 33230976 ps
T621 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.156593159 Feb 29 12:44:44 PM PST 24 Feb 29 12:44:44 PM PST 24 79767430 ps
T622 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3066308202 Feb 29 12:44:27 PM PST 24 Feb 29 12:44:29 PM PST 24 223567995 ps
T623 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3210222439 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:26 PM PST 24 229632685 ps
T624 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3485021408 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:25 PM PST 24 84873795 ps
T625 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3265959595 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:18 PM PST 24 117987431 ps
T118 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3389050614 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:23 PM PST 24 111485835 ps
T125 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1347540291 Feb 29 12:44:36 PM PST 24 Feb 29 12:44:38 PM PST 24 64066604 ps
T69 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2838119820 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:22 PM PST 24 45795200 ps
T114 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.847471793 Feb 29 12:44:29 PM PST 24 Feb 29 12:44:31 PM PST 24 557663221 ps
T626 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3620576389 Feb 29 12:44:15 PM PST 24 Feb 29 12:44:19 PM PST 24 1294187397 ps
T627 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1853247909 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:21 PM PST 24 44510108 ps
T628 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1925610732 Feb 29 12:44:35 PM PST 24 Feb 29 12:44:35 PM PST 24 35729725 ps
T629 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3113103430 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:26 PM PST 24 96524622 ps
T630 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1027504562 Feb 29 12:44:26 PM PST 24 Feb 29 12:44:29 PM PST 24 577955413 ps
T631 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3438577919 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 164585233 ps
T632 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4109005706 Feb 29 12:44:33 PM PST 24 Feb 29 12:44:34 PM PST 24 35112207 ps
T633 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2421645813 Feb 29 12:44:45 PM PST 24 Feb 29 12:44:45 PM PST 24 14615095 ps
T634 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3868102356 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:15 PM PST 24 78119165 ps
T635 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.190455493 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:15 PM PST 24 17718950 ps
T636 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.379835563 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:26 PM PST 24 182103505 ps
T637 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2720743499 Feb 29 12:44:48 PM PST 24 Feb 29 12:44:49 PM PST 24 17198888 ps
T119 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.825039088 Feb 29 12:44:16 PM PST 24 Feb 29 12:44:19 PM PST 24 1096683979 ps
T638 /workspace/coverage/cover_reg_top/26.hmac_intr_test.1408908436 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:25 PM PST 24 33327903 ps
T639 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3558339832 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:24 PM PST 24 14826882 ps
T640 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1468591601 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:16 PM PST 24 242681144 ps
T641 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.22965471 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 23083880 ps
T642 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.757517190 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 102278661 ps
T643 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3470488274 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:16 PM PST 24 39655481 ps
T644 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.215943817 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:16 PM PST 24 76184867 ps
T645 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1263082616 Feb 29 12:44:41 PM PST 24 Feb 29 12:44:42 PM PST 24 11561289 ps
T646 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3004224556 Feb 29 12:44:36 PM PST 24 Feb 29 12:44:38 PM PST 24 166706872 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1325298584 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:27 PM PST 24 770670370 ps
T648 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3842059142 Feb 29 12:44:29 PM PST 24 Feb 29 12:44:30 PM PST 24 40052883 ps
T70 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.665891158 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 14715548 ps
T649 /workspace/coverage/cover_reg_top/29.hmac_intr_test.3965986143 Feb 29 12:44:28 PM PST 24 Feb 29 12:44:29 PM PST 24 40221022 ps
T115 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3278425980 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:31 PM PST 24 113101333 ps
T650 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.77253138 Feb 29 12:44:47 PM PST 24 Feb 29 12:44:51 PM PST 24 366790536 ps
T651 /workspace/coverage/cover_reg_top/39.hmac_intr_test.3603664495 Feb 29 12:44:44 PM PST 24 Feb 29 12:44:44 PM PST 24 14156489 ps
T652 /workspace/coverage/cover_reg_top/14.hmac_intr_test.2276489402 Feb 29 12:44:43 PM PST 24 Feb 29 12:44:44 PM PST 24 16745219 ps
T653 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3197237747 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:28 PM PST 24 88233667 ps
T654 /workspace/coverage/cover_reg_top/6.hmac_intr_test.2360048106 Feb 29 12:44:26 PM PST 24 Feb 29 12:44:27 PM PST 24 13573752 ps
T655 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.909946976 Feb 29 12:44:19 PM PST 24 Feb 29 12:44:21 PM PST 24 55189228 ps
T656 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3218159755 Feb 29 12:44:48 PM PST 24 Feb 29 12:44:49 PM PST 24 17699266 ps
T657 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.351110378 Feb 29 12:44:41 PM PST 24 Feb 29 12:44:42 PM PST 24 10959886 ps
T658 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3128683037 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 26879527 ps
T659 /workspace/coverage/cover_reg_top/20.hmac_intr_test.4250412786 Feb 29 12:44:27 PM PST 24 Feb 29 12:44:28 PM PST 24 17703413 ps
T660 /workspace/coverage/cover_reg_top/45.hmac_intr_test.878472699 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:25 PM PST 24 63093162 ps
T120 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1548600365 Feb 29 12:44:28 PM PST 24 Feb 29 12:44:30 PM PST 24 152489636 ps
T661 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2854998468 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 20184673 ps
T123 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3945144704 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:24 PM PST 24 142071954 ps
T71 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3210037203 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:17 PM PST 24 302918405 ps
T662 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1648404334 Feb 29 12:44:35 PM PST 24 Feb 29 12:44:36 PM PST 24 24750007 ps
T663 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2712895491 Feb 29 12:44:46 PM PST 24 Feb 29 12:44:48 PM PST 24 65329840 ps
T664 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2904738251 Feb 29 12:44:22 PM PST 24 Feb 29 12:44:23 PM PST 24 15852117 ps
T665 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1901435453 Feb 29 12:44:40 PM PST 24 Feb 29 12:44:43 PM PST 24 68021673 ps
T666 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3486516400 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:23 PM PST 24 146410880 ps
T667 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.943764628 Feb 29 12:44:20 PM PST 24 Feb 29 12:44:21 PM PST 24 16954942 ps
T668 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1430025548 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:20 PM PST 24 24879154 ps
T669 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1908786095 Feb 29 12:44:43 PM PST 24 Feb 29 12:44:44 PM PST 24 30429117 ps
T670 /workspace/coverage/cover_reg_top/2.hmac_intr_test.734296675 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:15 PM PST 24 14271511 ps
T76 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1964868390 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:19 PM PST 24 5289597307 ps
T671 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2102395069 Feb 29 12:44:46 PM PST 24 Feb 29 12:44:46 PM PST 24 121197032 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_intr_test.3009579786 Feb 29 12:44:41 PM PST 24 Feb 29 12:44:42 PM PST 24 11802824 ps
T673 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1441503301 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 31883191 ps
T674 /workspace/coverage/cover_reg_top/18.hmac_intr_test.163552938 Feb 29 12:44:27 PM PST 24 Feb 29 12:44:28 PM PST 24 20545846 ps
T675 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2389004544 Feb 29 12:44:44 PM PST 24 Feb 29 12:44:44 PM PST 24 30279156 ps
T676 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1977631816 Feb 29 12:44:29 PM PST 24 Feb 29 12:44:32 PM PST 24 176252188 ps
T677 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2467431657 Feb 29 12:44:39 PM PST 24 Feb 29 12:44:40 PM PST 24 57725209 ps
T116 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2631366181 Feb 29 12:44:45 PM PST 24 Feb 29 12:44:46 PM PST 24 412615857 ps
T678 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3353508790 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:23 PM PST 24 57085903 ps
T679 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1540134018 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:15 PM PST 24 46767357 ps
T680 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1608250786 Feb 29 12:44:22 PM PST 24 Feb 29 12:44:25 PM PST 24 184608807 ps
T72 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4228513406 Feb 29 12:44:22 PM PST 24 Feb 29 12:44:23 PM PST 24 31050887 ps
T77 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2833983237 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:19 PM PST 24 136332883 ps
T681 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3293946366 Feb 29 12:44:40 PM PST 24 Feb 29 12:44:42 PM PST 24 99249848 ps
T73 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3011535156 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 38673546 ps
T121 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1430530023 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:16 PM PST 24 397108779 ps
T682 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.707604567 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:26 PM PST 24 164206528 ps
T683 /workspace/coverage/cover_reg_top/28.hmac_intr_test.926799563 Feb 29 12:44:43 PM PST 24 Feb 29 12:44:43 PM PST 24 15207363 ps
T684 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1119489398 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:26 PM PST 24 36951172 ps
T685 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2612616517 Feb 29 12:44:22 PM PST 24 Feb 29 12:44:23 PM PST 24 22118081 ps
T686 /workspace/coverage/cover_reg_top/21.hmac_intr_test.2646340726 Feb 29 12:44:50 PM PST 24 Feb 29 12:44:51 PM PST 24 17074804 ps
T74 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2710052278 Feb 29 12:44:26 PM PST 24 Feb 29 12:44:27 PM PST 24 14663420 ps
T687 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.512360229 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:14 PM PST 24 239736052 ps
T688 /workspace/coverage/cover_reg_top/31.hmac_intr_test.379891436 Feb 29 12:44:37 PM PST 24 Feb 29 12:44:38 PM PST 24 60176776 ps
T689 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2131623219 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:25 PM PST 24 50738437 ps
T690 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3982585085 Feb 29 12:44:48 PM PST 24 Feb 29 12:44:51 PM PST 24 125543919 ps
T79 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2630272570 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:21 PM PST 24 380792834 ps
T78 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2091737804 Feb 29 12:44:28 PM PST 24 Feb 29 12:44:34 PM PST 24 624277042 ps
T691 /workspace/coverage/cover_reg_top/3.hmac_intr_test.973446766 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:25 PM PST 24 13330951 ps
T692 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1901993700 Feb 29 12:44:10 PM PST 24 Feb 29 01:00:13 PM PST 24 108359055674 ps
T693 /workspace/coverage/cover_reg_top/10.hmac_intr_test.1385217628 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:19 PM PST 24 13849380 ps
T694 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2577724852 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:19 PM PST 24 13230272 ps
T695 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2170606621 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:27 PM PST 24 103179690 ps
T696 /workspace/coverage/cover_reg_top/30.hmac_intr_test.1484576614 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:25 PM PST 24 31425159 ps
T75 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3880849781 Feb 29 12:44:35 PM PST 24 Feb 29 12:44:37 PM PST 24 110488210 ps
T83 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3541220156 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 25632378 ps
T697 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4088013565 Feb 29 12:44:13 PM PST 24 Feb 29 12:44:14 PM PST 24 86675009 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2059459168 Feb 29 12:44:26 PM PST 24 Feb 29 12:44:27 PM PST 24 39601303 ps
T698 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3383370587 Feb 29 12:44:17 PM PST 24 Feb 29 12:44:19 PM PST 24 27912469 ps
T699 /workspace/coverage/cover_reg_top/37.hmac_intr_test.3472054780 Feb 29 12:44:33 PM PST 24 Feb 29 12:44:33 PM PST 24 21610379 ps
T700 /workspace/coverage/cover_reg_top/16.hmac_intr_test.389352976 Feb 29 12:44:24 PM PST 24 Feb 29 12:44:25 PM PST 24 13526742 ps
T701 /workspace/coverage/cover_reg_top/4.hmac_intr_test.679261574 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:12 PM PST 24 14422128 ps
T702 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.72727750 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:37 PM PST 24 121864222 ps
T703 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1143564685 Feb 29 12:44:33 PM PST 24 Feb 29 12:44:34 PM PST 24 69187481 ps
T124 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3292385796 Feb 29 12:44:44 PM PST 24 Feb 29 12:44:46 PM PST 24 317031784 ps
T704 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2939232761 Feb 29 12:44:20 PM PST 24 Feb 29 12:44:22 PM PST 24 52792322 ps
T705 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.985349106 Feb 29 12:44:40 PM PST 24 Feb 29 12:44:42 PM PST 24 39821697 ps
T706 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1402394143 Feb 29 12:44:40 PM PST 24 Feb 29 12:44:42 PM PST 24 306188234 ps
T81 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1897454421 Feb 29 12:44:32 PM PST 24 Feb 29 12:44:33 PM PST 24 80175770 ps
T707 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3117128840 Feb 29 12:44:33 PM PST 24 Feb 29 12:44:34 PM PST 24 270825558 ps
T708 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3652388664 Feb 29 12:44:32 PM PST 24 Feb 29 12:44:34 PM PST 24 226893977 ps
T709 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2483696818 Feb 29 12:44:24 PM PST 24 Feb 29 12:57:01 PM PST 24 56797751935 ps
T710 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3211007602 Feb 29 12:44:37 PM PST 24 Feb 29 12:44:38 PM PST 24 19345197 ps
T117 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1702194415 Feb 29 12:44:46 PM PST 24 Feb 29 12:44:48 PM PST 24 1064388625 ps
T711 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3144846305 Feb 29 12:44:45 PM PST 24 Feb 29 12:44:47 PM PST 24 65906625 ps
T712 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2551102827 Feb 29 12:44:47 PM PST 24 Feb 29 12:44:48 PM PST 24 22482906 ps
T713 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2180790068 Feb 29 12:44:39 PM PST 24 Feb 29 12:44:40 PM PST 24 26305135 ps
T714 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3567823581 Feb 29 12:44:19 PM PST 24 Feb 29 12:44:22 PM PST 24 163268542 ps
T715 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3233315358 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:16 PM PST 24 14444200 ps
T716 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3766184134 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:26 PM PST 24 171574196 ps
T122 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2050455593 Feb 29 12:44:49 PM PST 24 Feb 29 12:44:52 PM PST 24 167550791 ps
T717 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3748820 Feb 29 12:44:34 PM PST 24 Feb 29 12:44:35 PM PST 24 19372867 ps
T718 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1766410620 Feb 29 12:44:25 PM PST 24 Feb 29 12:44:26 PM PST 24 178343141 ps
T719 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3237611868 Feb 29 12:44:26 PM PST 24 Feb 29 12:44:29 PM PST 24 634934911 ps
T720 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1720657641 Feb 29 12:44:21 PM PST 24 Feb 29 12:44:26 PM PST 24 731962730 ps
T721 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.932978593 Feb 29 12:44:12 PM PST 24 Feb 29 12:44:13 PM PST 24 421533880 ps
T722 /workspace/coverage/cover_reg_top/46.hmac_intr_test.793123696 Feb 29 12:44:46 PM PST 24 Feb 29 12:44:47 PM PST 24 45632564 ps
T723 /workspace/coverage/cover_reg_top/13.hmac_intr_test.1563364758 Feb 29 12:44:46 PM PST 24 Feb 29 12:44:46 PM PST 24 12040497 ps
T724 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2366788103 Feb 29 12:44:41 PM PST 24 Feb 29 12:44:43 PM PST 24 265172117 ps
T725 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.992589715 Feb 29 12:44:14 PM PST 24 Feb 29 12:44:16 PM PST 24 205317314 ps
T82 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4213689868 Feb 29 12:44:23 PM PST 24 Feb 29 12:44:26 PM PST 24 169919517 ps

Test location /workspace/coverage/default/79.hmac_stress_all_with_rand_reset.2731401159
Short name T5
Test name
Test status
Simulation time 118364483404 ps
CPU time 1353.73 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 01:21:15 PM PST 24
Peak memory 228908 kb
Host smart-e09f2242-a59b-44c1-9979-354e0506f962
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731401159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.hmac_stress_all_with_rand_reset.2731401159
Directory /workspace/79.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.hmac_stress_all.62165188
Short name T2
Test name
Test status
Simulation time 135330115304 ps
CPU time 1137.96 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 01:17:13 PM PST 24
Peak memory 219280 kb
Host smart-36a0005d-393a-4773-a2d4-802a17361098
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62165188 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.62165188
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/187.hmac_stress_all_with_rand_reset.3573234235
Short name T35
Test name
Test status
Simulation time 41002887287 ps
CPU time 1030.83 seconds
Started Feb 29 12:58:58 PM PST 24
Finished Feb 29 01:16:09 PM PST 24
Peak memory 236384 kb
Host smart-7572eb0d-b4bd-4bc2-96fb-5ad55e86b175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3573234235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.hmac_stress_all_with_rand_reset.3573234235
Directory /workspace/187.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.251696365
Short name T47
Test name
Test status
Simulation time 147942364 ps
CPU time 1.76 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 198520 kb
Host smart-1630bb14-c421-4dd2-b334-e17e375acf2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251696365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.251696365
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.754139261
Short name T20
Test name
Test status
Simulation time 33317845 ps
CPU time 0.87 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:57:37 PM PST 24
Peak memory 217744 kb
Host smart-f6237aaa-72bf-4e99-a1b4-817dc74841cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754139261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.754139261
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2873385489
Short name T129
Test name
Test status
Simulation time 36565779 ps
CPU time 0.56 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 12:57:55 PM PST 24
Peak memory 194032 kb
Host smart-5052aa33-597d-494a-a3d1-231c6dfda224
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873385489 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2873385489
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.3210037203
Short name T71
Test name
Test status
Simulation time 302918405 ps
CPU time 2.53 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:17 PM PST 24
Peak memory 192644 kb
Host smart-b992d372-740d-4a23-a51e-30c850169e56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210037203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.3210037203
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/41.hmac_stress_all.4177063787
Short name T92
Test name
Test status
Simulation time 247022950097 ps
CPU time 1674.95 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 01:26:29 PM PST 24
Peak memory 215872 kb
Host smart-09dc707c-8f44-4121-a6f5-298394c15603
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177063787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.4177063787
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_stress_all.3770977489
Short name T95
Test name
Test status
Simulation time 33613999017 ps
CPU time 429.83 seconds
Started Feb 29 12:57:35 PM PST 24
Finished Feb 29 01:04:45 PM PST 24
Peak memory 239808 kb
Host smart-1bc04875-ca5b-4045-b5c6-993a9c5e6a79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770977489 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.3770977489
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.1430530023
Short name T121
Test name
Test status
Simulation time 397108779 ps
CPU time 2.27 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 198796 kb
Host smart-2db3610b-eddf-4e4a-a180-f5e52c77de3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430530023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.1430530023
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3152154847
Short name T93
Test name
Test status
Simulation time 83137355066 ps
CPU time 394.61 seconds
Started Feb 29 12:58:37 PM PST 24
Finished Feb 29 01:05:15 PM PST 24
Peak memory 240236 kb
Host smart-95b71ae7-e0d4-4acb-9e3a-20e8f576c14b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152154847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3152154847
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1702194415
Short name T117
Test name
Test status
Simulation time 1064388625 ps
CPU time 1.75 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 198688 kb
Host smart-efb5bb64-95ec-4826-a0f4-e1a22298ddde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702194415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1702194415
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/21.hmac_stress_all.4043278269
Short name T108
Test name
Test status
Simulation time 398742837370 ps
CPU time 1669.28 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 01:25:44 PM PST 24
Peak memory 199500 kb
Host smart-f8ec5532-c057-4fcf-8205-4d8b11f9f60f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043278269 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.4043278269
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.913661217
Short name T105
Test name
Test status
Simulation time 4498640349 ps
CPU time 38.94 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:59:05 PM PST 24
Peak memory 207628 kb
Host smart-07970c5a-a384-42b1-9850-6c85fa4f3c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913661217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.913661217
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_stress_all.1145740611
Short name T91
Test name
Test status
Simulation time 312707047615 ps
CPU time 1774.44 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 01:28:11 PM PST 24
Peak memory 199488 kb
Host smart-c6e8950c-f1e9-4030-bf75-2ee133a51306
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145740611 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.1145740611
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1247925760
Short name T107
Test name
Test status
Simulation time 140490356634 ps
CPU time 1769.3 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 01:27:49 PM PST 24
Peak memory 232232 kb
Host smart-afc1717b-ff2f-4d1d-8ff6-d81ac1c4d2f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247925760 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1247925760
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3831922536
Short name T103
Test name
Test status
Simulation time 3946360935 ps
CPU time 30.58 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 230208 kb
Host smart-ce229f97-b19b-46f1-8cc8-b3d9ffd9c5a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831922536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3831922536
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_stress_all.227462476
Short name T57
Test name
Test status
Simulation time 152125113370 ps
CPU time 1147.64 seconds
Started Feb 29 12:57:23 PM PST 24
Finished Feb 29 01:16:31 PM PST 24
Peak memory 215680 kb
Host smart-99eaff2e-02d8-4657-8691-754fcb28278c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227462476 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.227462476
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/57.hmac_stress_all_with_rand_reset.515396991
Short name T54
Test name
Test status
Simulation time 88324313868 ps
CPU time 4240.46 seconds
Started Feb 29 12:58:54 PM PST 24
Finished Feb 29 02:09:35 PM PST 24
Peak memory 256896 kb
Host smart-edfebfe7-67c9-4507-aea8-8e10ece6a7f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=515396991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.hmac_stress_all_with_rand_reset.515396991
Directory /workspace/57.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.4213689868
Short name T82
Test name
Test status
Simulation time 169919517 ps
CPU time 1.84 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 192644 kb
Host smart-6cfce159-5153-45d2-a885-fea3252a00fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213689868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.4213689868
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.2833983237
Short name T77
Test name
Test status
Simulation time 136332883 ps
CPU time 5.36 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 192608 kb
Host smart-cc37f13d-a8f3-4b07-b3c5-a646f4d3ca82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833983237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.2833983237
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.156593159
Short name T621
Test name
Test status
Simulation time 79767430 ps
CPU time 0.6 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 194344 kb
Host smart-1698bd8e-87b3-4e52-9f33-aa550c225ed1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156593159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.156593159
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2766385725
Short name T617
Test name
Test status
Simulation time 47877382 ps
CPU time 1.11 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 198880 kb
Host smart-bdbdceaf-d0a0-4c40-97cf-7cd1426e59eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766385725 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2766385725
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3383370587
Short name T698
Test name
Test status
Simulation time 27912469 ps
CPU time 0.61 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 194284 kb
Host smart-f8ba5a44-afdc-4f03-b7cb-8020cd43ce5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383370587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3383370587
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.178222413
Short name T599
Test name
Test status
Simulation time 65778655 ps
CPU time 0.6 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 184256 kb
Host smart-2eb5da31-476d-41a7-a24c-a11a855284c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178222413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.178222413
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1430025548
Short name T668
Test name
Test status
Simulation time 24879154 ps
CPU time 1.1 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 197312 kb
Host smart-1f642374-41bb-4dc2-a107-4b23924d0569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430025548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.1430025548
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2366788103
Short name T724
Test name
Test status
Simulation time 265172117 ps
CPU time 1.48 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:43 PM PST 24
Peak memory 199044 kb
Host smart-b412dbf9-00d2-451d-8e1d-8f83bf22140a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366788103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2366788103
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1540134018
Short name T679
Test name
Test status
Simulation time 46767357 ps
CPU time 1.21 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 198160 kb
Host smart-dbfb2c63-ebdc-4bc0-992f-e6f997c77b5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540134018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1540134018
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.3880849781
Short name T75
Test name
Test status
Simulation time 110488210 ps
CPU time 1.79 seconds
Started Feb 29 12:44:35 PM PST 24
Finished Feb 29 12:44:37 PM PST 24
Peak memory 192712 kb
Host smart-63fc11fe-f04e-42d4-ad83-f974118da613
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880849781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.3880849781
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.2091737804
Short name T78
Test name
Test status
Simulation time 624277042 ps
CPU time 6.72 seconds
Started Feb 29 12:44:28 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 192720 kb
Host smart-16c5594e-032e-4098-bdfa-4b71a873b7de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091737804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.2091737804
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3541220156
Short name T83
Test name
Test status
Simulation time 25632378 ps
CPU time 0.72 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 194616 kb
Host smart-04eb33ed-f777-4f1f-ad2d-32c7737df6b1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541220156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3541220156
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2746207669
Short name T611
Test name
Test status
Simulation time 233021149725 ps
CPU time 1005.96 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 01:01:07 PM PST 24
Peak memory 215484 kb
Host smart-d7f471b8-787f-44f1-9f7a-40e67dad947c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746207669 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2746207669
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.665891158
Short name T70
Test name
Test status
Simulation time 14715548 ps
CPU time 0.64 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 195120 kb
Host smart-c185baf8-200a-4b33-b02b-52b555879d95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665891158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.665891158
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.3009579786
Short name T672
Test name
Test status
Simulation time 11802824 ps
CPU time 0.62 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 184188 kb
Host smart-abb78361-7c7c-4167-993e-0382951eaf5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009579786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.3009579786
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2170606621
Short name T695
Test name
Test status
Simulation time 103179690 ps
CPU time 1.3 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 192648 kb
Host smart-1207fbaa-afa8-4bba-9335-9ed95b547617
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170606621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2170606621
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.992589715
Short name T725
Test name
Test status
Simulation time 205317314 ps
CPU time 2.34 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 199124 kb
Host smart-b9b62c56-222b-41b9-ac3c-65cdba7a750b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992589715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.992589715
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2631366181
Short name T116
Test name
Test status
Simulation time 412615857 ps
CPU time 1.74 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 198612 kb
Host smart-e0f2e478-5629-47e5-ac62-c988ad8f51c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631366181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2631366181
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3567823581
Short name T714
Test name
Test status
Simulation time 163268542 ps
CPU time 2.51 seconds
Started Feb 29 12:44:19 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 199188 kb
Host smart-57fe8d8e-edac-4cf8-b350-93f92c29d6a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567823581 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3567823581
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1119489398
Short name T684
Test name
Test status
Simulation time 36951172 ps
CPU time 0.59 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 194264 kb
Host smart-281d7e89-6dc0-41fb-82f9-729a3541aabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119489398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1119489398
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.1385217628
Short name T693
Test name
Test status
Simulation time 13849380 ps
CPU time 0.56 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 184164 kb
Host smart-5be9a363-3255-4cbf-939a-6356cdf6625e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385217628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.1385217628
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2939515695
Short name T51
Test name
Test status
Simulation time 151869028 ps
CPU time 1.09 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 197288 kb
Host smart-fa628093-6eba-4255-a747-2e8894ac713e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939515695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2939515695
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3486516400
Short name T666
Test name
Test status
Simulation time 146410880 ps
CPU time 1.79 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 199036 kb
Host smart-b7232d87-3696-4c82-a9a0-0de989cdcefa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486516400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3486516400
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.3945144704
Short name T123
Test name
Test status
Simulation time 142071954 ps
CPU time 1.66 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:24 PM PST 24
Peak memory 198664 kb
Host smart-08602e22-67b7-407c-b574-d524ba49cbf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945144704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.3945144704
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1027504562
Short name T630
Test name
Test status
Simulation time 577955413 ps
CPU time 2.18 seconds
Started Feb 29 12:44:26 PM PST 24
Finished Feb 29 12:44:29 PM PST 24
Peak memory 199036 kb
Host smart-b872d951-59fb-4ca1-a34b-5cd655b6b7aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027504562 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1027504562
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2577724852
Short name T694
Test name
Test status
Simulation time 13230272 ps
CPU time 0.59 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 194192 kb
Host smart-6b40fa76-ae1d-49fe-b3ee-ca365acda3f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577724852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2577724852
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3842059142
Short name T648
Test name
Test status
Simulation time 40052883 ps
CPU time 0.56 seconds
Started Feb 29 12:44:29 PM PST 24
Finished Feb 29 12:44:30 PM PST 24
Peak memory 184212 kb
Host smart-686b0928-0552-412a-8d74-b90fff84eaf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842059142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3842059142
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3606372248
Short name T616
Test name
Test status
Simulation time 53885934 ps
CPU time 0.78 seconds
Started Feb 29 12:44:35 PM PST 24
Finished Feb 29 12:44:36 PM PST 24
Peak memory 192572 kb
Host smart-d7b6bd2c-f21d-4f78-ab76-f5b1d02fd815
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606372248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3606372248
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.77253138
Short name T650
Test name
Test status
Simulation time 366790536 ps
CPU time 3.48 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 199184 kb
Host smart-7cc071fd-44e4-4310-b3bb-43a0d93edbe2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77253138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.77253138
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.1350918971
Short name T49
Test name
Test status
Simulation time 58007349 ps
CPU time 1.19 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 198368 kb
Host smart-9a94e393-37d6-404f-8123-299c1e6d5726
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350918971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.1350918971
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3652388664
Short name T708
Test name
Test status
Simulation time 226893977 ps
CPU time 1.11 seconds
Started Feb 29 12:44:32 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 198932 kb
Host smart-d5e9146a-f149-4f98-98b0-efb14b811d43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652388664 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3652388664
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4228513406
Short name T72
Test name
Test status
Simulation time 31050887 ps
CPU time 0.59 seconds
Started Feb 29 12:44:22 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 194408 kb
Host smart-a71fa19f-2a04-4e1d-9917-25954d8d5054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228513406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4228513406
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3689454393
Short name T602
Test name
Test status
Simulation time 16484019 ps
CPU time 0.6 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:50 PM PST 24
Peak memory 184224 kb
Host smart-29270071-65cd-4fad-bb7b-35281e98ea70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689454393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3689454393
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3578764474
Short name T619
Test name
Test status
Simulation time 51310048 ps
CPU time 1.15 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 197468 kb
Host smart-df9ecc53-67af-465f-b208-ab151f4e090a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578764474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3578764474
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3237611868
Short name T719
Test name
Test status
Simulation time 634934911 ps
CPU time 3.02 seconds
Started Feb 29 12:44:26 PM PST 24
Finished Feb 29 12:44:29 PM PST 24
Peak memory 199024 kb
Host smart-c0a47d81-a004-4c4c-bdc3-15e4b833048e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237611868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3237611868
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3066308202
Short name T622
Test name
Test status
Simulation time 223567995 ps
CPU time 1.23 seconds
Started Feb 29 12:44:27 PM PST 24
Finished Feb 29 12:44:29 PM PST 24
Peak memory 198572 kb
Host smart-2463006e-9154-416f-aaf7-fd8d1e7774a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066308202 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3066308202
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.115085229
Short name T52
Test name
Test status
Simulation time 112929259 ps
CPU time 2 seconds
Started Feb 29 12:44:19 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 199052 kb
Host smart-fbf0d7d1-4481-43da-a5af-b5d674bbd7a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115085229 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.115085229
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.686785593
Short name T66
Test name
Test status
Simulation time 40541750 ps
CPU time 0.74 seconds
Started Feb 29 12:44:38 PM PST 24
Finished Feb 29 12:44:39 PM PST 24
Peak memory 194872 kb
Host smart-e555b505-00c9-4ee0-9674-8b0c0ffd836b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686785593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.686785593
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.1563364758
Short name T723
Test name
Test status
Simulation time 12040497 ps
CPU time 0.62 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 184252 kb
Host smart-49da4c88-8c33-4cf0-a63a-06b3271df370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563364758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.1563364758
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2271470246
Short name T610
Test name
Test status
Simulation time 101525351 ps
CPU time 1.39 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:50 PM PST 24
Peak memory 197604 kb
Host smart-b918a2f1-8d42-4ca6-ab6e-55f2cbd90dcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271470246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2271470246
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3197237747
Short name T653
Test name
Test status
Simulation time 88233667 ps
CPU time 2.09 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:28 PM PST 24
Peak memory 199068 kb
Host smart-1c534da7-c28c-4619-9999-257f4b1fdee3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197237747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3197237747
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.757517190
Short name T642
Test name
Test status
Simulation time 102278661 ps
CPU time 1.11 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 198568 kb
Host smart-ae258f21-9d8e-44ba-8cc4-76b4186429ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757517190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.757517190
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.707604567
Short name T682
Test name
Test status
Simulation time 164206528 ps
CPU time 1.17 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 198840 kb
Host smart-6df6d189-50bc-4fda-adc0-d013beea4ba3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707604567 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.707604567
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2612616517
Short name T685
Test name
Test status
Simulation time 22118081 ps
CPU time 0.71 seconds
Started Feb 29 12:44:22 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 195188 kb
Host smart-58489905-018a-437a-bef0-327d05b488a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612616517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2612616517
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.2276489402
Short name T652
Test name
Test status
Simulation time 16745219 ps
CPU time 0.55 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 184200 kb
Host smart-f290a0f5-e771-4af1-ba1b-e0842142d65a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276489402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.2276489402
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3117128840
Short name T707
Test name
Test status
Simulation time 270825558 ps
CPU time 1.51 seconds
Started Feb 29 12:44:33 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 196784 kb
Host smart-a59377b9-871c-4771-9620-d32e2baebcfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117128840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3117128840
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1901435453
Short name T665
Test name
Test status
Simulation time 68021673 ps
CPU time 2.12 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:43 PM PST 24
Peak memory 199092 kb
Host smart-dc42509f-8f9a-4929-b20e-0764a3aea197
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901435453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1901435453
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1347540291
Short name T125
Test name
Test status
Simulation time 64066604 ps
CPU time 1.15 seconds
Started Feb 29 12:44:36 PM PST 24
Finished Feb 29 12:44:38 PM PST 24
Peak memory 198360 kb
Host smart-be9fb2ba-2706-44e7-b464-8993d2e34510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347540291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1347540291
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.1977631816
Short name T676
Test name
Test status
Simulation time 176252188 ps
CPU time 2.97 seconds
Started Feb 29 12:44:29 PM PST 24
Finished Feb 29 12:44:32 PM PST 24
Peak memory 199332 kb
Host smart-ed415d53-20ca-474d-9dcc-df305fec1a3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977631816 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.1977631816
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2181066044
Short name T67
Test name
Test status
Simulation time 17989931 ps
CPU time 0.65 seconds
Started Feb 29 12:44:35 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 194896 kb
Host smart-f1d27f68-159f-4fbd-97d4-ce9264c00cff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181066044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2181066044
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.3549853870
Short name T598
Test name
Test status
Simulation time 42762099 ps
CPU time 0.59 seconds
Started Feb 29 12:44:36 PM PST 24
Finished Feb 29 12:44:37 PM PST 24
Peak memory 184284 kb
Host smart-bb9f1bdf-801d-40fe-809b-92c570c0ad5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549853870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.3549853870
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.1648404334
Short name T662
Test name
Test status
Simulation time 24750007 ps
CPU time 1.03 seconds
Started Feb 29 12:44:35 PM PST 24
Finished Feb 29 12:44:36 PM PST 24
Peak memory 197220 kb
Host smart-a840768c-57b5-4ee1-bb9f-1b26bce81a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648404334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.1648404334
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1720657641
Short name T720
Test name
Test status
Simulation time 731962730 ps
CPU time 3.86 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 199020 kb
Host smart-5727be72-349b-4811-9fe6-42ddc6fe6df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720657641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1720657641
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.1548600365
Short name T120
Test name
Test status
Simulation time 152489636 ps
CPU time 1.74 seconds
Started Feb 29 12:44:28 PM PST 24
Finished Feb 29 12:44:30 PM PST 24
Peak memory 198544 kb
Host smart-773edb27-a14f-4c9c-a6fb-76e19bcb8479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548600365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.1548600365
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.379835563
Short name T636
Test name
Test status
Simulation time 182103505 ps
CPU time 1.57 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 199044 kb
Host smart-9bf7e226-10f6-4932-af8d-03a9a8fb7056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379835563 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.379835563
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1897454421
Short name T81
Test name
Test status
Simulation time 80175770 ps
CPU time 0.82 seconds
Started Feb 29 12:44:32 PM PST 24
Finished Feb 29 12:44:33 PM PST 24
Peak memory 195224 kb
Host smart-381fcc4b-3f2f-4ec8-94f7-680e89fbb617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897454421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1897454421
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.389352976
Short name T700
Test name
Test status
Simulation time 13526742 ps
CPU time 0.64 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184260 kb
Host smart-dab70e86-1b39-470a-87d4-280c16ee31ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389352976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.389352976
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.3144846305
Short name T711
Test name
Test status
Simulation time 65906625 ps
CPU time 1.39 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:47 PM PST 24
Peak memory 196932 kb
Host smart-43b78969-121f-4085-9d68-3e06e9fe9fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144846305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.3144846305
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.72727750
Short name T702
Test name
Test status
Simulation time 121864222 ps
CPU time 2.74 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:37 PM PST 24
Peak memory 199004 kb
Host smart-10a4d35e-bca1-42d0-a219-66b4268f03a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72727750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.72727750
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.847471793
Short name T114
Test name
Test status
Simulation time 557663221 ps
CPU time 1.27 seconds
Started Feb 29 12:44:29 PM PST 24
Finished Feb 29 12:44:31 PM PST 24
Peak memory 198476 kb
Host smart-22f98daa-9627-4ca6-8759-b9fb703cbece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847471793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.847471793
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.985349106
Short name T705
Test name
Test status
Simulation time 39821697 ps
CPU time 1.08 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 198880 kb
Host smart-3ee66862-59bb-4d46-ad4e-89da8a207207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985349106 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.985349106
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3084370409
Short name T605
Test name
Test status
Simulation time 90727204 ps
CPU time 0.77 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:45 PM PST 24
Peak memory 195256 kb
Host smart-dc6b0576-d1d8-4b02-9467-3de8023991bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084370409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3084370409
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2904738251
Short name T664
Test name
Test status
Simulation time 15852117 ps
CPU time 0.51 seconds
Started Feb 29 12:44:22 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 184292 kb
Host smart-909f068c-62ab-4831-9d17-521c07c348a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904738251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2904738251
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.1063647229
Short name T620
Test name
Test status
Simulation time 113084578 ps
CPU time 0.9 seconds
Started Feb 29 12:44:27 PM PST 24
Finished Feb 29 12:44:28 PM PST 24
Peak memory 196320 kb
Host smart-e68cf311-538e-4400-9146-3c79a358b787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063647229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.1063647229
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1608250786
Short name T680
Test name
Test status
Simulation time 184608807 ps
CPU time 1.41 seconds
Started Feb 29 12:44:22 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 199116 kb
Host smart-71d5e2d9-73e8-42af-9e83-7d17263a88b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608250786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1608250786
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3982585085
Short name T690
Test name
Test status
Simulation time 125543919 ps
CPU time 3 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 199100 kb
Host smart-bfeeb960-fac4-4c6f-9f37-fbea78b47d92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982585085 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3982585085
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.351110378
Short name T657
Test name
Test status
Simulation time 10959886 ps
CPU time 0.64 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 194656 kb
Host smart-bb3dfbb2-335d-48a9-8f2a-ba71fc1209eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351110378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.351110378
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.163552938
Short name T674
Test name
Test status
Simulation time 20545846 ps
CPU time 0.65 seconds
Started Feb 29 12:44:27 PM PST 24
Finished Feb 29 12:44:28 PM PST 24
Peak memory 184192 kb
Host smart-5431c9ac-62f4-4c9f-8b8f-98d07a1f0768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163552938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.163552938
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3004224556
Short name T646
Test name
Test status
Simulation time 166706872 ps
CPU time 1.08 seconds
Started Feb 29 12:44:36 PM PST 24
Finished Feb 29 12:44:38 PM PST 24
Peak memory 197300 kb
Host smart-bc4738b8-fd87-4b83-97a6-0978458e2b57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004224556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3004224556
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1402394143
Short name T706
Test name
Test status
Simulation time 306188234 ps
CPU time 1.7 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 199056 kb
Host smart-00dbbdcb-0313-4852-8cc5-47e6bc0b27b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402394143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1402394143
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.3292385796
Short name T124
Test name
Test status
Simulation time 317031784 ps
CPU time 1.61 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 198352 kb
Host smart-aa0017ee-cb7c-4990-9fbb-2d4e496d1698
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292385796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.3292385796
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.571534435
Short name T618
Test name
Test status
Simulation time 32763308270 ps
CPU time 334.24 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:50:18 PM PST 24
Peak memory 207424 kb
Host smart-f3453f23-7ff3-449f-b8a0-2e16f94cff2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571534435 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.571534435
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2180790068
Short name T713
Test name
Test status
Simulation time 26305135 ps
CPU time 0.59 seconds
Started Feb 29 12:44:39 PM PST 24
Finished Feb 29 12:44:40 PM PST 24
Peak memory 194104 kb
Host smart-882775b7-048d-4842-8bd3-7ac92efc3530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180790068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2180790068
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2389004544
Short name T675
Test name
Test status
Simulation time 30279156 ps
CPU time 0.55 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 184208 kb
Host smart-e94629d1-d4bb-4af8-a934-d92e7aa59e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389004544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2389004544
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3210222439
Short name T623
Test name
Test status
Simulation time 229632685 ps
CPU time 0.84 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 192476 kb
Host smart-cc48325f-19c7-4d49-a81f-5fcabeb0e509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210222439 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3210222439
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3375049882
Short name T613
Test name
Test status
Simulation time 108330349 ps
CPU time 1.43 seconds
Started Feb 29 12:44:29 PM PST 24
Finished Feb 29 12:44:31 PM PST 24
Peak memory 199044 kb
Host smart-6c4f1022-0bb9-405a-894e-86a1b4e0372a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375049882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3375049882
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.3766184134
Short name T716
Test name
Test status
Simulation time 171574196 ps
CPU time 1.92 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 192716 kb
Host smart-f02078c6-ea46-4768-93f0-4ad1e8b648ca
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766184134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.3766184134
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3620576389
Short name T626
Test name
Test status
Simulation time 1294187397 ps
CPU time 3.49 seconds
Started Feb 29 12:44:15 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 192696 kb
Host smart-d0003104-dddf-4ad9-b989-3dab6eb0b3ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620576389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3620576389
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.932978593
Short name T721
Test name
Test status
Simulation time 421533880 ps
CPU time 0.75 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 194792 kb
Host smart-6f1d8b9f-ad81-4e5d-aac5-7bf0e5496e4e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932978593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.932978593
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.909946976
Short name T655
Test name
Test status
Simulation time 55189228 ps
CPU time 1.44 seconds
Started Feb 29 12:44:19 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 199116 kb
Host smart-f688305e-4fb0-4b33-911c-e05520bf782e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909946976 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.909946976
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.943764628
Short name T667
Test name
Test status
Simulation time 16954942 ps
CPU time 0.75 seconds
Started Feb 29 12:44:20 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 195180 kb
Host smart-ee3a21eb-4973-426c-a98c-09ad65f46a9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943764628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.943764628
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.734296675
Short name T670
Test name
Test status
Simulation time 14271511 ps
CPU time 0.57 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 184148 kb
Host smart-471c18bc-543f-46f7-b158-bb5e9a86c65f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734296675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.734296675
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3438577919
Short name T631
Test name
Test status
Simulation time 164585233 ps
CPU time 1.05 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 192696 kb
Host smart-ba4bd2e2-f391-4fcf-a45f-d865ee6ba85f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438577919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3438577919
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.1853247909
Short name T627
Test name
Test status
Simulation time 44510108 ps
CPU time 2.47 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 199244 kb
Host smart-98feb885-f442-49b0-b429-ab3a389f77e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853247909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.1853247909
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3389050614
Short name T118
Test name
Test status
Simulation time 111485835 ps
CPU time 1.88 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 198768 kb
Host smart-e78008f4-6615-4e99-bb4c-c6b5fb336b6b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389050614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3389050614
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.4250412786
Short name T659
Test name
Test status
Simulation time 17703413 ps
CPU time 0.61 seconds
Started Feb 29 12:44:27 PM PST 24
Finished Feb 29 12:44:28 PM PST 24
Peak memory 184248 kb
Host smart-c51e7a9d-66d9-4dd8-be98-142e06bec00e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250412786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.4250412786
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.2646340726
Short name T686
Test name
Test status
Simulation time 17074804 ps
CPU time 0.62 seconds
Started Feb 29 12:44:50 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 184288 kb
Host smart-89eedac3-acfd-4f9b-a8e5-0f41f56d2b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646340726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.2646340726
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2102395069
Short name T671
Test name
Test status
Simulation time 121197032 ps
CPU time 0.57 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 184252 kb
Host smart-cf43b976-9b68-46b4-97ad-a4e1cf74b511
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102395069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2102395069
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2720743499
Short name T637
Test name
Test status
Simulation time 17198888 ps
CPU time 0.61 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 184296 kb
Host smart-68a39d9b-9438-4998-8f7c-68b499504bff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720743499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2720743499
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4109005706
Short name T632
Test name
Test status
Simulation time 35112207 ps
CPU time 0.6 seconds
Started Feb 29 12:44:33 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 184144 kb
Host smart-9c3af908-6f1d-46fb-8edf-0481423a445b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109005706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4109005706
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3055727729
Short name T612
Test name
Test status
Simulation time 204138996 ps
CPU time 0.6 seconds
Started Feb 29 12:44:38 PM PST 24
Finished Feb 29 12:44:39 PM PST 24
Peak memory 184256 kb
Host smart-e810ea0d-fb63-4a1b-9dc4-98ba3531e5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055727729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3055727729
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.1408908436
Short name T638
Test name
Test status
Simulation time 33327903 ps
CPU time 0.55 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184160 kb
Host smart-75b9d659-0d09-4080-847a-01373a185bc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408908436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.1408908436
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1263082616
Short name T645
Test name
Test status
Simulation time 11561289 ps
CPU time 0.55 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 184240 kb
Host smart-cc08fcc4-dd4f-4612-b312-aa894c8caa03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263082616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1263082616
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.926799563
Short name T683
Test name
Test status
Simulation time 15207363 ps
CPU time 0.61 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:43 PM PST 24
Peak memory 184256 kb
Host smart-5e0e9b8b-7efc-4f85-a1ce-5760ced9b9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926799563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.926799563
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.3965986143
Short name T649
Test name
Test status
Simulation time 40221022 ps
CPU time 0.54 seconds
Started Feb 29 12:44:28 PM PST 24
Finished Feb 29 12:44:29 PM PST 24
Peak memory 184152 kb
Host smart-24b85132-09c4-4030-8051-dffa1f8e7d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965986143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.3965986143
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2852020285
Short name T53
Test name
Test status
Simulation time 51453475 ps
CPU time 1.83 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 192716 kb
Host smart-98845012-223c-4964-a209-b1c258d78686
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852020285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2852020285
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.2630272570
Short name T79
Test name
Test status
Simulation time 380792834 ps
CPU time 7.83 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 184524 kb
Host smart-07d235f8-d873-4484-b7ac-9d98582c59a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630272570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.2630272570
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3011535156
Short name T73
Test name
Test status
Simulation time 38673546 ps
CPU time 0.75 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 194752 kb
Host smart-1525068f-642c-4b1d-aa96-bd295a2ba0dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011535156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3011535156
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.615482706
Short name T601
Test name
Test status
Simulation time 424330980 ps
CPU time 1.53 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 199096 kb
Host smart-374bb5fe-08b1-44fd-9278-0c8346d43925
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615482706 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.615482706
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3233315358
Short name T715
Test name
Test status
Simulation time 14444200 ps
CPU time 0.65 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 194776 kb
Host smart-26057a1a-0789-4ceb-8991-1845c43d8ca6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233315358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3233315358
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.973446766
Short name T691
Test name
Test status
Simulation time 13330951 ps
CPU time 0.55 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184160 kb
Host smart-c9bcd949-f011-4c00-8df4-7d7cd3d6343c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973446766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.973446766
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3994748038
Short name T603
Test name
Test status
Simulation time 58806118 ps
CPU time 0.92 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 192484 kb
Host smart-ade0ff96-a25c-4613-8c1f-ad6dd94cc2c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994748038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3994748038
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1325298584
Short name T647
Test name
Test status
Simulation time 770670370 ps
CPU time 3.59 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 199104 kb
Host smart-b8b17400-66ec-4fe7-83cc-422aa9b1c74f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325298584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1325298584
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.1484576614
Short name T696
Test name
Test status
Simulation time 31425159 ps
CPU time 0.55 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184208 kb
Host smart-769fcaef-8e97-4089-a80b-81ae37a0e963
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484576614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.1484576614
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.379891436
Short name T688
Test name
Test status
Simulation time 60176776 ps
CPU time 0.53 seconds
Started Feb 29 12:44:37 PM PST 24
Finished Feb 29 12:44:38 PM PST 24
Peak memory 184152 kb
Host smart-54c7876b-9f0d-46fd-b454-44e35370fd0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379891436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.379891436
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3748820
Short name T717
Test name
Test status
Simulation time 19372867 ps
CPU time 0.63 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 184256 kb
Host smart-3d610cb6-66f6-4f97-ab4d-352ddc29dd1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3748820
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2854998468
Short name T661
Test name
Test status
Simulation time 20184673 ps
CPU time 0.61 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 184236 kb
Host smart-2f3628d8-53d3-4855-8504-4611608126e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854998468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2854998468
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1925610732
Short name T628
Test name
Test status
Simulation time 35729725 ps
CPU time 0.55 seconds
Started Feb 29 12:44:35 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 184152 kb
Host smart-3a03be64-65f1-40d0-bf09-49d4e5190d62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925610732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1925610732
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.454892585
Short name T615
Test name
Test status
Simulation time 195331133 ps
CPU time 0.58 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 184168 kb
Host smart-5f64e850-a484-4f53-832a-3333cfdd40cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454892585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.454892585
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.2177624747
Short name T604
Test name
Test status
Simulation time 20516711 ps
CPU time 0.55 seconds
Started Feb 29 12:44:39 PM PST 24
Finished Feb 29 12:44:40 PM PST 24
Peak memory 184296 kb
Host smart-ba995fc6-6ac0-4607-a172-55f59b79146d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177624747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.2177624747
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.3472054780
Short name T699
Test name
Test status
Simulation time 21610379 ps
CPU time 0.58 seconds
Started Feb 29 12:44:33 PM PST 24
Finished Feb 29 12:44:33 PM PST 24
Peak memory 184136 kb
Host smart-797980b1-9023-4a47-b60b-5009ac3fa040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472054780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.3472054780
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3113103430
Short name T629
Test name
Test status
Simulation time 96524622 ps
CPU time 0.6 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 184192 kb
Host smart-b201384f-f635-4263-ab20-191bc9080fbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113103430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3113103430
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.3603664495
Short name T651
Test name
Test status
Simulation time 14156489 ps
CPU time 0.58 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 184208 kb
Host smart-400e04ae-fbeb-45d0-b690-1c2196bd96e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603664495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.3603664495
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1964868390
Short name T76
Test name
Test status
Simulation time 5289597307 ps
CPU time 3.72 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 192752 kb
Host smart-4a2afdd0-ac21-4c65-8459-10d5301b7266
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964868390 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1964868390
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.4088013565
Short name T697
Test name
Test status
Simulation time 86675009 ps
CPU time 0.63 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 194264 kb
Host smart-bc023c21-4b12-4c8e-84d6-1006fa9cd886
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088013565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.4088013565
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1199646026
Short name T606
Test name
Test status
Simulation time 215157913 ps
CPU time 1.12 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:24 PM PST 24
Peak memory 198928 kb
Host smart-d8ebfcb0-b4a3-46c3-8afb-ad52d8df8b64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199646026 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1199646026
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2059459168
Short name T80
Test name
Test status
Simulation time 39601303 ps
CPU time 0.65 seconds
Started Feb 29 12:44:26 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 194292 kb
Host smart-a5c11d3e-c4b0-475e-9d03-91b4a79d5fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059459168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2059459168
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.679261574
Short name T701
Test name
Test status
Simulation time 14422128 ps
CPU time 0.55 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 184188 kb
Host smart-9b674216-0ea4-48de-a05c-abb9a118cd4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679261574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.679261574
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2962978744
Short name T607
Test name
Test status
Simulation time 151257032 ps
CPU time 1.13 seconds
Started Feb 29 12:44:22 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 192660 kb
Host smart-97d404bf-32bd-4952-b9a3-91d2a7568e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962978744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2962978744
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.1468591601
Short name T640
Test name
Test status
Simulation time 242681144 ps
CPU time 3.32 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 199056 kb
Host smart-e0e2a013-0e75-427a-835d-c0ef9ba20f9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468591601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.1468591601
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3353508790
Short name T678
Test name
Test status
Simulation time 57085903 ps
CPU time 1.18 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:23 PM PST 24
Peak memory 198508 kb
Host smart-23a2a8c8-eb53-463f-b812-65471fb937ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353508790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3353508790
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2421645813
Short name T633
Test name
Test status
Simulation time 14615095 ps
CPU time 0.54 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:45 PM PST 24
Peak memory 184144 kb
Host smart-34a4811f-2316-4783-a0cd-b91b77a628e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421645813 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2421645813
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3218159755
Short name T656
Test name
Test status
Simulation time 17699266 ps
CPU time 0.61 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 184308 kb
Host smart-b8878c3a-664c-4ab9-a4b9-12186d9081de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218159755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3218159755
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2551102827
Short name T712
Test name
Test status
Simulation time 22482906 ps
CPU time 0.58 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 184304 kb
Host smart-f2e03e9f-9fec-406b-80f3-785e7b96e117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551102827 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2551102827
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2467431657
Short name T677
Test name
Test status
Simulation time 57725209 ps
CPU time 0.58 seconds
Started Feb 29 12:44:39 PM PST 24
Finished Feb 29 12:44:40 PM PST 24
Peak memory 184208 kb
Host smart-75e25026-1d68-4624-8093-b7a1e7197f73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467431657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2467431657
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1908786095
Short name T669
Test name
Test status
Simulation time 30429117 ps
CPU time 0.56 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 184200 kb
Host smart-23e9bfb9-f937-4a7d-b743-f4540c6ab7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908786095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1908786095
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.878472699
Short name T660
Test name
Test status
Simulation time 63093162 ps
CPU time 0.58 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184112 kb
Host smart-07541251-ed32-457e-8c79-e7dccdc91996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878472699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.878472699
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.793123696
Short name T722
Test name
Test status
Simulation time 45632564 ps
CPU time 0.56 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:47 PM PST 24
Peak memory 184276 kb
Host smart-0de87fc7-5b21-4bda-80c1-bdb4089c11a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793123696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.793123696
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1441503301
Short name T673
Test name
Test status
Simulation time 31883191 ps
CPU time 0.59 seconds
Started Feb 29 12:44:34 PM PST 24
Finished Feb 29 12:44:35 PM PST 24
Peak memory 184188 kb
Host smart-f2ab5a1c-c6f7-47c0-9210-384f3c72e725
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441503301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1441503301
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2548230301
Short name T609
Test name
Test status
Simulation time 15687284 ps
CPU time 0.6 seconds
Started Feb 29 12:44:33 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 184192 kb
Host smart-cbd94af4-9b76-4679-b290-cf06d4bd4bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548230301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2548230301
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3211007602
Short name T710
Test name
Test status
Simulation time 19345197 ps
CPU time 0.55 seconds
Started Feb 29 12:44:37 PM PST 24
Finished Feb 29 12:44:38 PM PST 24
Peak memory 184124 kb
Host smart-ea13672c-77c6-4cbf-8d32-be8d366dc18f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211007602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3211007602
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.2483696818
Short name T709
Test name
Test status
Simulation time 56797751935 ps
CPU time 755.88 seconds
Started Feb 29 12:44:24 PM PST 24
Finished Feb 29 12:57:01 PM PST 24
Peak memory 215268 kb
Host smart-5491172d-d46f-4264-b76d-e35dd0e780aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483696818 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.2483696818
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1143564685
Short name T703
Test name
Test status
Simulation time 69187481 ps
CPU time 0.6 seconds
Started Feb 29 12:44:33 PM PST 24
Finished Feb 29 12:44:34 PM PST 24
Peak memory 194620 kb
Host smart-25e221d6-da20-40ef-be40-e57c73bda1dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143564685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1143564685
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3558339832
Short name T639
Test name
Test status
Simulation time 14826882 ps
CPU time 0.64 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:24 PM PST 24
Peak memory 184144 kb
Host smart-be5d3df1-165e-4118-ba71-8c75b21988f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558339832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3558339832
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2712895491
Short name T663
Test name
Test status
Simulation time 65329840 ps
CPU time 1.32 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 197400 kb
Host smart-e8256475-de72-4660-bf6e-5a8ff9bd9bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712895491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2712895491
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.22965471
Short name T641
Test name
Test status
Simulation time 23083880 ps
CPU time 1.24 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 199116 kb
Host smart-f6dc271c-6445-4c64-a90c-a18f1bb6b1d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22965471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.22965471
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3278425980
Short name T115
Test name
Test status
Simulation time 113101333 ps
CPU time 1.22 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:31 PM PST 24
Peak memory 198508 kb
Host smart-f3d3e5f8-245c-4d91-a184-8dd21eee72b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278425980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3278425980
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3470488274
Short name T643
Test name
Test status
Simulation time 39655481 ps
CPU time 2.31 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 199032 kb
Host smart-cedf0d81-95cb-4d15-8ac6-f0001989d8d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470488274 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3470488274
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3847737619
Short name T68
Test name
Test status
Simulation time 33230976 ps
CPU time 0.59 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 194684 kb
Host smart-8fcfdede-7001-405f-b31d-1886722bec26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847737619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3847737619
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2360048106
Short name T654
Test name
Test status
Simulation time 13573752 ps
CPU time 0.71 seconds
Started Feb 29 12:44:26 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 184260 kb
Host smart-76ac9b0e-4293-45bc-9a84-52e9f9de7a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360048106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2360048106
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3128683037
Short name T658
Test name
Test status
Simulation time 26879527 ps
CPU time 0.76 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:13 PM PST 24
Peak memory 195760 kb
Host smart-5b9f7a5e-1558-4007-8d37-b916a963c384
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128683037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3128683037
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3485021408
Short name T624
Test name
Test status
Simulation time 84873795 ps
CPU time 1.41 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 199108 kb
Host smart-643e8bbc-68eb-4958-b4cc-f4e08751e9c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485021408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3485021408
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.1077237506
Short name T113
Test name
Test status
Simulation time 45320004 ps
CPU time 1.14 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:41 PM PST 24
Peak memory 198480 kb
Host smart-8b788f17-7847-405f-9bd3-aa9885e63734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077237506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.1077237506
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.3293946366
Short name T681
Test name
Test status
Simulation time 99249848 ps
CPU time 1.73 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 199116 kb
Host smart-8313eb8d-c4cb-4a1d-b3ec-074579c0477f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293946366 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.3293946366
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.190455493
Short name T635
Test name
Test status
Simulation time 17718950 ps
CPU time 0.62 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 194428 kb
Host smart-f5ac3984-75d8-4783-91d5-a41cc54555a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190455493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.190455493
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1766410620
Short name T718
Test name
Test status
Simulation time 178343141 ps
CPU time 0.62 seconds
Started Feb 29 12:44:25 PM PST 24
Finished Feb 29 12:44:26 PM PST 24
Peak memory 184208 kb
Host smart-953a39b5-4378-4aca-991b-6d6d4c8ae59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766410620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1766410620
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3868102356
Short name T634
Test name
Test status
Simulation time 78119165 ps
CPU time 0.95 seconds
Started Feb 29 12:44:14 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 192740 kb
Host smart-a9e85352-4421-4de0-8f96-5758c6a2d381
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868102356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3868102356
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1470630450
Short name T614
Test name
Test status
Simulation time 70970320 ps
CPU time 3.49 seconds
Started Feb 29 12:44:28 PM PST 24
Finished Feb 29 12:44:32 PM PST 24
Peak memory 199176 kb
Host smart-f3c786c0-c095-4b3f-9c41-ef0106b10a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470630450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1470630450
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2050455593
Short name T122
Test name
Test status
Simulation time 167550791 ps
CPU time 2.55 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:52 PM PST 24
Peak memory 198720 kb
Host smart-3d00a4b0-efed-4e03-8e6f-91046f10e857
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050455593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2050455593
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.215943817
Short name T644
Test name
Test status
Simulation time 76184867 ps
CPU time 2 seconds
Started Feb 29 12:44:13 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 199088 kb
Host smart-a43b5ba9-ac06-4a6a-8630-3735fdc20c6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215943817 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.215943817
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2710052278
Short name T74
Test name
Test status
Simulation time 14663420 ps
CPU time 0.67 seconds
Started Feb 29 12:44:26 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 194892 kb
Host smart-9b0160d0-08fd-4579-8d25-d93259626a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710052278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2710052278
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2131623219
Short name T689
Test name
Test status
Simulation time 50738437 ps
CPU time 0.54 seconds
Started Feb 29 12:44:23 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 184204 kb
Host smart-92fd0c20-2147-40cc-bd5a-9331bd8ac195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131623219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2131623219
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2939232761
Short name T704
Test name
Test status
Simulation time 52792322 ps
CPU time 1.28 seconds
Started Feb 29 12:44:20 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 192688 kb
Host smart-bebe1d33-2dad-4a24-a84a-99e7d87d6fc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939232761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2939232761
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.512360229
Short name T687
Test name
Test status
Simulation time 239736052 ps
CPU time 2.74 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 199048 kb
Host smart-57f2309a-82aa-4a96-9f45-22201c3c7621
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512360229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.512360229
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.825039088
Short name T119
Test name
Test status
Simulation time 1096683979 ps
CPU time 2.33 seconds
Started Feb 29 12:44:16 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 198892 kb
Host smart-11e1f85e-6667-465d-9400-270edb725ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825039088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.825039088
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1901993700
Short name T692
Test name
Test status
Simulation time 108359055674 ps
CPU time 962.63 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 01:00:13 PM PST 24
Peak memory 219516 kb
Host smart-d8c6f9dc-9a8e-43f1-bf0e-bc51892636bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901993700 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1901993700
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2838119820
Short name T69
Test name
Test status
Simulation time 45795200 ps
CPU time 0.68 seconds
Started Feb 29 12:44:21 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 195188 kb
Host smart-c341ce68-88f4-496a-a9f9-221c27c3683c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838119820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2838119820
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.764095184
Short name T600
Test name
Test status
Simulation time 16635143 ps
CPU time 0.57 seconds
Started Feb 29 12:44:15 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 184188 kb
Host smart-d9183a41-775c-4754-a665-f777d779abaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764095184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.764095184
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3265959595
Short name T625
Test name
Test status
Simulation time 117987431 ps
CPU time 0.82 seconds
Started Feb 29 12:44:17 PM PST 24
Finished Feb 29 12:44:18 PM PST 24
Peak memory 195824 kb
Host smart-6eea269b-db88-42cb-93d6-c4a9ee351e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265959595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3265959595
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2832084200
Short name T608
Test name
Test status
Simulation time 290814500 ps
CPU time 3.06 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 199128 kb
Host smart-8486dbb1-03a7-4a6f-aa39-51d025416256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832084200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2832084200
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1596436363
Short name T48
Test name
Test status
Simulation time 262525584 ps
CPU time 1.73 seconds
Started Feb 29 12:44:19 PM PST 24
Finished Feb 29 12:44:21 PM PST 24
Peak memory 198740 kb
Host smart-b2952214-844a-4496-b820-70bab8bd7cd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596436363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1596436363
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.871389671
Short name T176
Test name
Test status
Simulation time 27668290 ps
CPU time 0.59 seconds
Started Feb 29 12:57:39 PM PST 24
Finished Feb 29 12:57:39 PM PST 24
Peak memory 193816 kb
Host smart-b6e30eef-bd39-43f0-92a9-2a0fadd5f171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871389671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.871389671
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.3965008165
Short name T323
Test name
Test status
Simulation time 2889546746 ps
CPU time 26 seconds
Started Feb 29 12:57:40 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 215364 kb
Host smart-42db0a45-4f19-42dd-9695-7943d2f2d67d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3965008165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.3965008165
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3546960463
Short name T277
Test name
Test status
Simulation time 7339462769 ps
CPU time 15.74 seconds
Started Feb 29 12:57:20 PM PST 24
Finished Feb 29 12:57:35 PM PST 24
Peak memory 199532 kb
Host smart-550d8cba-8e35-48a1-9f9e-c478871112b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546960463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3546960463
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2805563209
Short name T358
Test name
Test status
Simulation time 1401943557 ps
CPU time 34.33 seconds
Started Feb 29 12:57:25 PM PST 24
Finished Feb 29 12:58:00 PM PST 24
Peak memory 199464 kb
Host smart-cc0314a4-e94b-4b33-831b-62f12e1fa266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805563209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2805563209
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2997286075
Short name T526
Test name
Test status
Simulation time 2736168901 ps
CPU time 17.24 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:58:00 PM PST 24
Peak memory 199480 kb
Host smart-e455410f-2a6f-4dc4-8340-e631616064ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997286075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2997286075
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1967544968
Short name T189
Test name
Test status
Simulation time 3685965989 ps
CPU time 25.27 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:58:03 PM PST 24
Peak memory 199460 kb
Host smart-117948ba-1278-45d1-a982-81fc7dc7e994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967544968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1967544968
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2114443365
Short name T384
Test name
Test status
Simulation time 266756170 ps
CPU time 2.96 seconds
Started Feb 29 12:57:22 PM PST 24
Finished Feb 29 12:57:25 PM PST 24
Peak memory 199460 kb
Host smart-93930aa3-de42-4c6e-92a8-6267ef1315c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114443365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2114443365
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3698547792
Short name T482
Test name
Test status
Simulation time 81164057005 ps
CPU time 349.7 seconds
Started Feb 29 12:57:27 PM PST 24
Finished Feb 29 01:03:17 PM PST 24
Peak memory 227152 kb
Host smart-2a8cf88e-b952-47d9-afbc-64ea413111ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698547792 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3698547792
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1509613620
Short name T267
Test name
Test status
Simulation time 51510306 ps
CPU time 0.96 seconds
Started Feb 29 12:57:32 PM PST 24
Finished Feb 29 12:57:33 PM PST 24
Peak memory 197052 kb
Host smart-47bd5329-5147-4732-9b39-f674c7781345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509613620 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.1509613620
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3789368353
Short name T28
Test name
Test status
Simulation time 47476814118 ps
CPU time 364.62 seconds
Started Feb 29 12:57:24 PM PST 24
Finished Feb 29 01:03:29 PM PST 24
Peak memory 199488 kb
Host smart-3044d810-02e5-41ff-bc8a-68d7a06816c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789368353 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.hmac_test_sha_vectors.3789368353
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3350655092
Short name T519
Test name
Test status
Simulation time 6246710259 ps
CPU time 77.03 seconds
Started Feb 29 12:57:21 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199496 kb
Host smart-ffb4f614-66df-401e-ab78-1dbbeb0a6c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350655092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3350655092
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2410581281
Short name T490
Test name
Test status
Simulation time 35865531 ps
CPU time 0.57 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 194060 kb
Host smart-0309312e-42a0-4b18-b1c9-07e2c3ca20e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410581281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2410581281
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3820276650
Short name T43
Test name
Test status
Simulation time 1156664789 ps
CPU time 36.73 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 223552 kb
Host smart-d229014e-099c-40f7-99bd-eeae62a9cff1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3820276650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3820276650
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.298871980
Short name T230
Test name
Test status
Simulation time 1077730612 ps
CPU time 14.6 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 199404 kb
Host smart-a9a9c922-c719-4b8e-91d0-336600f8a5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298871980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.298871980
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.4022912473
Short name T461
Test name
Test status
Simulation time 2132391395 ps
CPU time 29.06 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:58:23 PM PST 24
Peak memory 199384 kb
Host smart-457d788f-3cf1-481d-bc5e-fdc9c3660403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4022912473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.4022912473
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.4151703759
Short name T263
Test name
Test status
Simulation time 18828186321 ps
CPU time 150.31 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 01:00:18 PM PST 24
Peak memory 199596 kb
Host smart-91d63d59-56f0-4a04-88ef-b5bbd249cd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151703759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.4151703759
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1469292660
Short name T401
Test name
Test status
Simulation time 974779699 ps
CPU time 12.54 seconds
Started Feb 29 12:57:28 PM PST 24
Finished Feb 29 12:57:41 PM PST 24
Peak memory 199500 kb
Host smart-bdeb37b2-46ca-4328-8e1f-d4a7ed5997a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469292660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1469292660
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.534981127
Short name T21
Test name
Test status
Simulation time 104705201 ps
CPU time 0.93 seconds
Started Feb 29 12:57:34 PM PST 24
Finished Feb 29 12:57:35 PM PST 24
Peak memory 217832 kb
Host smart-cae27dac-389d-46d3-bf42-2a1f06925346
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534981127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.534981127
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3479466856
Short name T345
Test name
Test status
Simulation time 180870689 ps
CPU time 3.97 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:57:40 PM PST 24
Peak memory 199448 kb
Host smart-c3b0fab7-2715-4f7b-a3a1-cfe42cdc0c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479466856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3479466856
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3409723694
Short name T546
Test name
Test status
Simulation time 26596116221 ps
CPU time 1233.01 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 01:18:18 PM PST 24
Peak memory 209060 kb
Host smart-b7d63bda-bc0e-4347-93d1-31d7a6090b41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409723694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3409723694
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.409864439
Short name T508
Test name
Test status
Simulation time 575117460 ps
CPU time 0.92 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:57:44 PM PST 24
Peak memory 197228 kb
Host smart-4af12b02-f3a1-4fb7-a749-34f2426b8835
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409864439 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.hmac_test_hmac_vectors.409864439
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.561382152
Short name T343
Test name
Test status
Simulation time 170474163089 ps
CPU time 512.1 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 01:06:13 PM PST 24
Peak memory 199404 kb
Host smart-69a461e2-dfb0-47b7-baac-531320efedab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561382152 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_sha_vectors.561382152
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1251525319
Short name T421
Test name
Test status
Simulation time 12953006895 ps
CPU time 38 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:58:09 PM PST 24
Peak memory 199468 kb
Host smart-f84e6789-36f6-46fd-a1ca-bceb4c10c2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251525319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1251525319
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.771044131
Short name T584
Test name
Test status
Simulation time 13297514 ps
CPU time 0.56 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 193756 kb
Host smart-4ec6f17a-6cb0-40e0-bf37-6f08f9b05282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771044131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.771044131
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3048689553
Short name T437
Test name
Test status
Simulation time 563308937 ps
CPU time 22.12 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:58:05 PM PST 24
Peak memory 231632 kb
Host smart-c19f1a58-4550-495a-ab57-2ef47b968ad8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3048689553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3048689553
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.3901575046
Short name T540
Test name
Test status
Simulation time 670310808 ps
CPU time 31.5 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:58:16 PM PST 24
Peak memory 199396 kb
Host smart-c05e7eb7-3210-469b-8b8a-75750957aec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901575046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.3901575046
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2860233375
Short name T480
Test name
Test status
Simulation time 1224323620 ps
CPU time 15.01 seconds
Started Feb 29 12:57:33 PM PST 24
Finished Feb 29 12:57:48 PM PST 24
Peak memory 199512 kb
Host smart-0a923e2a-f6af-48f6-9f0e-e431f0f4cf79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2860233375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2860233375
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4083520122
Short name T596
Test name
Test status
Simulation time 37843847227 ps
CPU time 126.17 seconds
Started Feb 29 12:57:59 PM PST 24
Finished Feb 29 01:00:05 PM PST 24
Peak memory 199528 kb
Host smart-91d18b18-c26c-44f7-93e1-f28078fd93da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083520122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4083520122
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3381352469
Short name T248
Test name
Test status
Simulation time 591183504 ps
CPU time 21.47 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:58:05 PM PST 24
Peak memory 199424 kb
Host smart-6fce543f-5d6b-4951-8f88-89b17e946d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381352469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3381352469
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.911310819
Short name T386
Test name
Test status
Simulation time 2662751677 ps
CPU time 2.86 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:47 PM PST 24
Peak memory 199492 kb
Host smart-ad67ee3e-5285-4cca-80f8-b832c6ea003c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911310819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.911310819
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3241723665
Short name T541
Test name
Test status
Simulation time 645355476833 ps
CPU time 752.6 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 01:10:23 PM PST 24
Peak memory 232148 kb
Host smart-cea4a887-6efe-435c-b685-8e910c5ae040
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241723665 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3241723665
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2188081309
Short name T212
Test name
Test status
Simulation time 122971555 ps
CPU time 1.18 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:57:49 PM PST 24
Peak memory 198992 kb
Host smart-053fdd3f-a9ea-4f04-8683-2d8a40525893
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188081309 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2188081309
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.3824110708
Short name T184
Test name
Test status
Simulation time 155015909698 ps
CPU time 463.39 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 01:05:35 PM PST 24
Peak memory 199364 kb
Host smart-32638c19-130e-4a3d-8c95-457f930a3909
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824110708 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.hmac_test_sha_vectors.3824110708
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.263810553
Short name T356
Test name
Test status
Simulation time 598881555 ps
CPU time 18.27 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:58:09 PM PST 24
Peak memory 199392 kb
Host smart-4f593d7f-905c-4521-b9c8-cbc1e9ca386b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263810553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.263810553
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/104.hmac_stress_all_with_rand_reset.3371848936
Short name T12
Test name
Test status
Simulation time 18455713623 ps
CPU time 420.23 seconds
Started Feb 29 12:58:54 PM PST 24
Finished Feb 29 01:05:55 PM PST 24
Peak memory 207716 kb
Host smart-0a90f981-846d-43b0-900c-77c6fd7b7693
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3371848936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.hmac_stress_all_with_rand_reset.3371848936
Directory /workspace/104.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3289354015
Short name T572
Test name
Test status
Simulation time 13164437 ps
CPU time 0.56 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:57:50 PM PST 24
Peak memory 194032 kb
Host smart-0838ad02-b546-48f8-950a-f198fb5dfa1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289354015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3289354015
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.3745421524
Short name T319
Test name
Test status
Simulation time 4289668057 ps
CPU time 23.09 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:58:11 PM PST 24
Peak memory 215680 kb
Host smart-a56e0078-d626-47b6-a01d-1c7dad9c1843
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745421524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.3745421524
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.1577604120
Short name T397
Test name
Test status
Simulation time 24085725233 ps
CPU time 47.46 seconds
Started Feb 29 12:57:46 PM PST 24
Finished Feb 29 12:58:34 PM PST 24
Peak memory 199504 kb
Host smart-85690f8a-7d1c-4320-818d-1fbc6b966caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577604120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.1577604120
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.1980838493
Short name T472
Test name
Test status
Simulation time 1180993510 ps
CPU time 63.85 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:58:54 PM PST 24
Peak memory 199444 kb
Host smart-2fa4691e-6b4f-4ec5-a044-b08c77a22b91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1980838493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.1980838493
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2453720326
Short name T354
Test name
Test status
Simulation time 3770309977 ps
CPU time 97.12 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:59:15 PM PST 24
Peak memory 199472 kb
Host smart-b499457a-7ce2-4e01-813e-ccb7857d9f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453720326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2453720326
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.4002467347
Short name T369
Test name
Test status
Simulation time 16392660919 ps
CPU time 105.54 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:59:33 PM PST 24
Peak memory 199476 kb
Host smart-c8b826de-e5a1-419e-adb6-7057183da7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002467347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.4002467347
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.400049848
Short name T408
Test name
Test status
Simulation time 212916423 ps
CPU time 2.78 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:57:45 PM PST 24
Peak memory 199392 kb
Host smart-b8086334-9c81-4278-9a24-5cdf5ca67441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400049848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.400049848
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.784797099
Short name T346
Test name
Test status
Simulation time 59813486589 ps
CPU time 762.34 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 01:10:23 PM PST 24
Peak memory 232264 kb
Host smart-d0406892-d202-4679-919e-6bf5d797f848
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784797099 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.784797099
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.626859155
Short name T24
Test name
Test status
Simulation time 415997089 ps
CPU time 1.08 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:57:54 PM PST 24
Peak memory 198384 kb
Host smart-06e295aa-ec9d-4f3f-a415-e76a598a9557
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626859155 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.hmac_test_hmac_vectors.626859155
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.25680685
Short name T539
Test name
Test status
Simulation time 128420068233 ps
CPU time 465.67 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 01:05:33 PM PST 24
Peak memory 199404 kb
Host smart-cc2c67cd-2633-4be3-b17a-fad01ef03bf3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25680685 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 11.hmac_test_sha_vectors.25680685
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.967157780
Short name T233
Test name
Test status
Simulation time 1679049347 ps
CPU time 23.28 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:58:18 PM PST 24
Peak memory 199376 kb
Host smart-b7bdd0a3-d5a2-4b85-8f90-c4295b21e94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967157780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.967157780
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.572290848
Short name T487
Test name
Test status
Simulation time 36506080 ps
CPU time 0.59 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:44 PM PST 24
Peak memory 194016 kb
Host smart-37576005-dae0-4bce-80a5-f0691dcf0afa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572290848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.572290848
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2983827218
Short name T420
Test name
Test status
Simulation time 1945906497 ps
CPU time 30.67 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 216708 kb
Host smart-669adc47-5ccd-49f9-aedd-5f6e5b362b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983827218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2983827218
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2959238804
Short name T198
Test name
Test status
Simulation time 1217366909 ps
CPU time 28.25 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:58:19 PM PST 24
Peak memory 199392 kb
Host smart-39125e03-5566-434e-8441-6d2b749032c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959238804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2959238804
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.1545103416
Short name T391
Test name
Test status
Simulation time 7608037573 ps
CPU time 80.56 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:59:18 PM PST 24
Peak memory 199488 kb
Host smart-7a94d93f-aa48-49d4-b8fc-67526a90b520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545103416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.1545103416
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.1704207550
Short name T457
Test name
Test status
Simulation time 7580878837 ps
CPU time 125.56 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 01:00:01 PM PST 24
Peak memory 199400 kb
Host smart-1c9e6933-411a-4aa8-be06-bbbcbd32a126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704207550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.1704207550
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.893527991
Short name T155
Test name
Test status
Simulation time 2675993247 ps
CPU time 19.98 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:16 PM PST 24
Peak memory 199444 kb
Host smart-8199838c-0d05-4761-bdc0-3d6ff15160cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893527991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.893527991
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4052324745
Short name T303
Test name
Test status
Simulation time 353985096 ps
CPU time 3.91 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:57:53 PM PST 24
Peak memory 199404 kb
Host smart-66067d32-e1ab-45b9-b62b-f156c9dd4f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052324745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4052324745
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1938325689
Short name T90
Test name
Test status
Simulation time 553387091051 ps
CPU time 1748.31 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 01:26:53 PM PST 24
Peak memory 199468 kb
Host smart-9abcf1b4-6671-4f22-8199-64ea0fcae172
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938325689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1938325689
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2922938599
Short name T534
Test name
Test status
Simulation time 54405765 ps
CPU time 0.97 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:57:46 PM PST 24
Peak memory 198096 kb
Host smart-52253f13-3e9a-444e-a237-d51c8e55145d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922938599 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.2922938599
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.1788491744
Short name T412
Test name
Test status
Simulation time 15600979138 ps
CPU time 370.26 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 01:04:05 PM PST 24
Peak memory 199476 kb
Host smart-496814ef-2afa-469e-a5d7-b8f4f6c31ab4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788491744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_sha_vectors.1788491744
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.130530937
Short name T379
Test name
Test status
Simulation time 630519160 ps
CPU time 29.62 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 199324 kb
Host smart-5c573d9f-2ecf-4096-a1cb-1e0dc4a91205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130530937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.130530937
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/124.hmac_stress_all_with_rand_reset.1910156011
Short name T11
Test name
Test status
Simulation time 20784468296 ps
CPU time 660.38 seconds
Started Feb 29 12:58:56 PM PST 24
Finished Feb 29 01:09:56 PM PST 24
Peak memory 216008 kb
Host smart-6927a77d-decc-4d22-932a-db89adf47b4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910156011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.hmac_stress_all_with_rand_reset.1910156011
Directory /workspace/124.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.919987497
Short name T473
Test name
Test status
Simulation time 604424453 ps
CPU time 19.05 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 199416 kb
Host smart-aafda3ed-803d-445b-9831-290cc165d55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=919987497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.919987497
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.4225839716
Short name T372
Test name
Test status
Simulation time 24967510809 ps
CPU time 37.62 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 199496 kb
Host smart-ae0f22c7-4f0c-4f34-abf4-f99908edc7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225839716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.4225839716
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.1634143893
Short name T557
Test name
Test status
Simulation time 1655644267 ps
CPU time 83.87 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:59:05 PM PST 24
Peak memory 199476 kb
Host smart-21aa4b61-5f27-4199-b29f-64c192fe2361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634143893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.1634143893
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1745307335
Short name T89
Test name
Test status
Simulation time 138078068421 ps
CPU time 136.17 seconds
Started Feb 29 12:57:35 PM PST 24
Finished Feb 29 12:59:51 PM PST 24
Peak memory 199352 kb
Host smart-376bf44d-a2c9-4518-ae74-3e32124019b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745307335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1745307335
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2644067422
Short name T32
Test name
Test status
Simulation time 17492649953 ps
CPU time 72.77 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:59:03 PM PST 24
Peak memory 199524 kb
Host smart-ac77cc72-e83b-4788-9e20-50b1bdc537c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644067422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2644067422
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3650139632
Short name T538
Test name
Test status
Simulation time 110870831 ps
CPU time 1.83 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:57:58 PM PST 24
Peak memory 199432 kb
Host smart-88c28d9b-0bd3-4230-a6f1-a1a4b62c6ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650139632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3650139632
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1030129438
Short name T26
Test name
Test status
Simulation time 23388479488 ps
CPU time 597.11 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 01:07:48 PM PST 24
Peak memory 199440 kb
Host smart-e7cfdf59-75f8-4040-be37-e48aa34de59f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030129438 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1030129438
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_stress_all_with_rand_reset.2291935235
Short name T34
Test name
Test status
Simulation time 40184853193 ps
CPU time 1794.02 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 01:27:50 PM PST 24
Peak memory 257144 kb
Host smart-c7a537e2-24e4-4ef6-85ba-1ba57144ef95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291935235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all_with_rand_reset.2291935235
Directory /workspace/13.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.2791260813
Short name T241
Test name
Test status
Simulation time 204600150 ps
CPU time 1.08 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:45 PM PST 24
Peak memory 198108 kb
Host smart-3ff9e150-72b4-49e0-aa40-c8333c4985c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791260813 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.2791260813
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.2179022874
Short name T462
Test name
Test status
Simulation time 31589941650 ps
CPU time 377.01 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 01:03:59 PM PST 24
Peak memory 199628 kb
Host smart-606de8fb-c75a-4d24-ad06-7f0404e876ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179022874 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.hmac_test_sha_vectors.2179022874
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.288012585
Short name T549
Test name
Test status
Simulation time 6158711416 ps
CPU time 54.77 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199684 kb
Host smart-e3c35214-5e68-46b5-aa60-718eaf718222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288012585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.288012585
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/136.hmac_stress_all_with_rand_reset.3734488666
Short name T36
Test name
Test status
Simulation time 35862635584 ps
CPU time 1199.87 seconds
Started Feb 29 12:58:52 PM PST 24
Finished Feb 29 01:18:52 PM PST 24
Peak memory 215996 kb
Host smart-b100a035-5207-4c4b-8827-f46609a844af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734488666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.hmac_stress_all_with_rand_reset.3734488666
Directory /workspace/136.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2148491522
Short name T1
Test name
Test status
Simulation time 12464882 ps
CPU time 0.56 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:57:58 PM PST 24
Peak memory 193776 kb
Host smart-ff0dc8e2-17ec-4d01-a6cb-1c7b1956add3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148491522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2148491522
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2374269919
Short name T235
Test name
Test status
Simulation time 3399916017 ps
CPU time 23.97 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 224140 kb
Host smart-2d2169eb-3818-411d-aa6f-397cafb64d72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2374269919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2374269919
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3351841661
Short name T17
Test name
Test status
Simulation time 12098513277 ps
CPU time 28.05 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 199548 kb
Host smart-b9e86491-5cb7-4e6d-bcfa-1d96b207a986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351841661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3351841661
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1000487266
Short name T324
Test name
Test status
Simulation time 1826722069 ps
CPU time 47.79 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:55 PM PST 24
Peak memory 199432 kb
Host smart-f7b047d7-36a1-4ba3-a267-02294ec5de20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1000487266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1000487266
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1936548003
Short name T200
Test name
Test status
Simulation time 65746578730 ps
CPU time 105.4 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:59:38 PM PST 24
Peak memory 199484 kb
Host smart-2636ce8d-cd83-4fc4-8f62-a57c9cb63f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936548003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1936548003
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.821621251
Short name T201
Test name
Test status
Simulation time 14769601461 ps
CPU time 98.8 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:59:36 PM PST 24
Peak memory 199404 kb
Host smart-3196e5c4-af60-4b02-a74b-8c1c3f40181c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821621251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.821621251
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.3612681232
Short name T203
Test name
Test status
Simulation time 272576643 ps
CPU time 3.59 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:57:52 PM PST 24
Peak memory 199380 kb
Host smart-961f3299-7ec8-457f-9f66-56bcd53db028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612681232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.3612681232
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.3017785033
Short name T166
Test name
Test status
Simulation time 129410533364 ps
CPU time 1523.01 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 01:23:12 PM PST 24
Peak memory 207716 kb
Host smart-0517284b-ac00-4eef-9e0d-9bee8894964e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017785033 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.3017785033
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2705520860
Short name T270
Test name
Test status
Simulation time 106008332 ps
CPU time 0.89 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:03 PM PST 24
Peak memory 196552 kb
Host smart-94e0854c-0d6b-48cf-a5db-9694be755448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705520860 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2705520860
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1008308718
Short name T515
Test name
Test status
Simulation time 33912641960 ps
CPU time 371.17 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 01:04:07 PM PST 24
Peak memory 199444 kb
Host smart-1c878671-da76-46ee-8808-e602abba0d7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008308718 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_sha_vectors.1008308718
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1319970128
Short name T431
Test name
Test status
Simulation time 5012725959 ps
CPU time 31.45 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 199508 kb
Host smart-90dadcb9-9d08-45d3-99fe-2fdb1d302729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319970128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1319970128
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.564468422
Short name T33
Test name
Test status
Simulation time 52111132988 ps
CPU time 368.31 seconds
Started Feb 29 12:58:56 PM PST 24
Finished Feb 29 01:05:04 PM PST 24
Peak memory 234480 kb
Host smart-3c35528a-f266-462a-a5c1-9eaf14b5a197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564468422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.564468422
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3022483887
Short name T328
Test name
Test status
Simulation time 54457218 ps
CPU time 0.55 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:57:48 PM PST 24
Peak memory 193784 kb
Host smart-41977224-4839-49d7-a86a-9ab0497f4921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022483887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3022483887
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.1750338322
Short name T529
Test name
Test status
Simulation time 759559703 ps
CPU time 25.06 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 207624 kb
Host smart-f300723b-c6dd-4fb5-acea-22fae6bbd56f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750338322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.1750338322
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1731102966
Short name T211
Test name
Test status
Simulation time 20338689 ps
CPU time 0.66 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:57:57 PM PST 24
Peak memory 195472 kb
Host smart-a75fb24d-646d-46cc-928f-ddb41691367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731102966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1731102966
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2668172729
Short name T193
Test name
Test status
Simulation time 3081852368 ps
CPU time 37.93 seconds
Started Feb 29 12:58:01 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199464 kb
Host smart-840752b3-31db-4451-9a75-a28894455e79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2668172729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2668172729
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2379252791
Short name T560
Test name
Test status
Simulation time 4374977163 ps
CPU time 105.97 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:59:24 PM PST 24
Peak memory 199516 kb
Host smart-9e04631f-afd7-4c4a-b66f-d629df75abea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379252791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2379252791
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2531512266
Short name T156
Test name
Test status
Simulation time 9154497463 ps
CPU time 32.16 seconds
Started Feb 29 12:57:39 PM PST 24
Finished Feb 29 12:58:11 PM PST 24
Peak memory 199704 kb
Host smart-a6d6cc3f-8355-42b5-afd8-ced0b7c6ccac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531512266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2531512266
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1420706058
Short name T151
Test name
Test status
Simulation time 216993183 ps
CPU time 1.76 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:57:54 PM PST 24
Peak memory 199348 kb
Host smart-ee5395ce-6992-49ef-8c89-58a168fd597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420706058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1420706058
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.4138133163
Short name T64
Test name
Test status
Simulation time 2198790732 ps
CPU time 54.17 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:58:51 PM PST 24
Peak memory 199548 kb
Host smart-abe4e5a9-084f-4597-a372-2b269119a733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138133163 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.4138133163
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.3682197518
Short name T202
Test name
Test status
Simulation time 132696483 ps
CPU time 1.32 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:03 PM PST 24
Peak memory 198020 kb
Host smart-c1656837-3ecb-4caf-b842-ddd0e811b787
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682197518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.3682197518
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.567578336
Short name T7
Test name
Test status
Simulation time 13427289213 ps
CPU time 455.56 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 01:05:28 PM PST 24
Peak memory 199520 kb
Host smart-c95782de-850d-4a74-9b66-9a50f1d8ee10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567578336 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 15.hmac_test_sha_vectors.567578336
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4146358084
Short name T425
Test name
Test status
Simulation time 23004196955 ps
CPU time 55.61 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:58:50 PM PST 24
Peak memory 199444 kb
Host smart-d48196bb-a223-441f-96cd-1741512b4487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146358084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4146358084
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.4022447175
Short name T163
Test name
Test status
Simulation time 17832194 ps
CPU time 0.54 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 194004 kb
Host smart-154c7c72-f626-47af-96eb-92caf04629ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022447175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.4022447175
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2750437357
Short name T450
Test name
Test status
Simulation time 1065643742 ps
CPU time 33.32 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 212952 kb
Host smart-34dd370b-fcad-4c2d-a06d-10d5ba3f5246
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2750437357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2750437357
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2582428374
Short name T174
Test name
Test status
Simulation time 878149196 ps
CPU time 15.93 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 199436 kb
Host smart-a8bfd03a-bce6-4b1f-8424-023c002c1cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582428374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2582428374
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.2213643401
Short name T506
Test name
Test status
Simulation time 198379475 ps
CPU time 10.5 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 199392 kb
Host smart-38239a98-b199-4afe-aa82-b8f9e59ee15a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2213643401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.2213643401
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.2837422644
Short name T251
Test name
Test status
Simulation time 1654561908 ps
CPU time 42.2 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 199416 kb
Host smart-7cdaf07a-2b9a-4eba-82c2-438fcc857152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837422644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.2837422644
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3791541917
Short name T245
Test name
Test status
Simulation time 531257512 ps
CPU time 9.66 seconds
Started Feb 29 12:57:58 PM PST 24
Finished Feb 29 12:58:08 PM PST 24
Peak memory 199364 kb
Host smart-b7de4da8-e144-4fae-b98c-7001bc13e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791541917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3791541917
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1462703138
Short name T172
Test name
Test status
Simulation time 666666588 ps
CPU time 2.14 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:57:59 PM PST 24
Peak memory 199588 kb
Host smart-8ad87028-7d08-4054-90a3-c0525054f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462703138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1462703138
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1209157813
Short name T227
Test name
Test status
Simulation time 22493696509 ps
CPU time 424.13 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 01:04:59 PM PST 24
Peak memory 240520 kb
Host smart-1b7003e2-b8a0-4106-a651-264d83234bdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209157813 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1209157813
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2560726888
Short name T310
Test name
Test status
Simulation time 324968603 ps
CPU time 1.13 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 12:57:55 PM PST 24
Peak memory 198164 kb
Host smart-5eda1fe8-820c-48a0-bbc8-bb77fcd3d791
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560726888 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2560726888
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1110991950
Short name T393
Test name
Test status
Simulation time 138929968794 ps
CPU time 468.78 seconds
Started Feb 29 12:57:58 PM PST 24
Finished Feb 29 01:05:47 PM PST 24
Peak memory 199340 kb
Host smart-8abe10ed-1b70-4444-95f6-194e08b0efb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110991950 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.hmac_test_sha_vectors.1110991950
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.2354483269
Short name T586
Test name
Test status
Simulation time 11971297887 ps
CPU time 52.9 seconds
Started Feb 29 12:57:46 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199408 kb
Host smart-27fe496d-08e6-4b72-91b1-0abdb898581b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354483269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.2354483269
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2518561287
Short name T152
Test name
Test status
Simulation time 54784809 ps
CPU time 0.54 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:58:11 PM PST 24
Peak memory 193776 kb
Host smart-e8701201-03c9-4ccc-9bee-2dc303cbd421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518561287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2518561287
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3330106286
Short name T416
Test name
Test status
Simulation time 2081211943 ps
CPU time 41.04 seconds
Started Feb 29 12:58:09 PM PST 24
Finished Feb 29 12:58:50 PM PST 24
Peak memory 233124 kb
Host smart-6d62e0d8-f2dc-4994-b018-dfd3cc00379b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330106286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3330106286
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1153066750
Short name T568
Test name
Test status
Simulation time 436138463 ps
CPU time 20.56 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:28 PM PST 24
Peak memory 199424 kb
Host smart-6c9273ca-dffb-4425-9791-5e0a1ddbfddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153066750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1153066750
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.354300847
Short name T371
Test name
Test status
Simulation time 357944990 ps
CPU time 19.27 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 199460 kb
Host smart-186903a5-a418-4db4-8aa0-58325fc1641d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354300847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.354300847
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.480947670
Short name T88
Test name
Test status
Simulation time 3259654589 ps
CPU time 169.26 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 01:00:38 PM PST 24
Peak memory 199524 kb
Host smart-8e2066e8-f8f0-4a2f-a0ce-a04a935e1f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480947670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.480947670
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3820623224
Short name T513
Test name
Test status
Simulation time 13409241062 ps
CPU time 30.67 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 199468 kb
Host smart-20f52722-2172-4348-94b1-094a4f534311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820623224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3820623224
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.544952539
Short name T514
Test name
Test status
Simulation time 578600877 ps
CPU time 2.37 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 12:58:21 PM PST 24
Peak memory 199408 kb
Host smart-ec41bd3b-eeb1-412d-b764-ba7f085eca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544952539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.544952539
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.2613452845
Short name T562
Test name
Test status
Simulation time 2108228910 ps
CPU time 13.67 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:02 PM PST 24
Peak memory 199396 kb
Host smart-d4ae7561-e339-494d-bc4f-128eda2fa106
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613452845 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.2613452845
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2652326586
Short name T153
Test name
Test status
Simulation time 63866514 ps
CPU time 1.17 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:57:57 PM PST 24
Peak memory 198372 kb
Host smart-8354c10e-6092-44bc-bfd6-d40db1b6adca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652326586 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.2652326586
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.2458633968
Short name T145
Test name
Test status
Simulation time 74744620884 ps
CPU time 496.04 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 01:06:21 PM PST 24
Peak memory 199520 kb
Host smart-294cbc20-0110-49a6-9d6e-7ece06b64bbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458633968 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_sha_vectors.2458633968
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3720910689
Short name T458
Test name
Test status
Simulation time 10928107525 ps
CPU time 45.38 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:34 PM PST 24
Peak memory 199536 kb
Host smart-646ea6b9-0992-483b-a25e-6784be0e595d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720910689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3720910689
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/178.hmac_stress_all_with_rand_reset.2223006763
Short name T55
Test name
Test status
Simulation time 36216084026 ps
CPU time 507.94 seconds
Started Feb 29 12:58:59 PM PST 24
Finished Feb 29 01:07:27 PM PST 24
Peak memory 231636 kb
Host smart-95b029bc-9fea-435d-a8bd-c54edbc09419
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2223006763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.hmac_stress_all_with_rand_reset.2223006763
Directory /workspace/178.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2459005709
Short name T561
Test name
Test status
Simulation time 24600833 ps
CPU time 0.56 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:57:48 PM PST 24
Peak memory 193796 kb
Host smart-23d9ca7e-b87f-4084-b000-3ad5c90c3068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459005709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2459005709
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.859392590
Short name T587
Test name
Test status
Simulation time 53918024 ps
CPU time 1.54 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:57:49 PM PST 24
Peak memory 199340 kb
Host smart-9f5ef267-1043-418e-8820-ed61f6d5db87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859392590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.859392590
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.128201999
Short name T305
Test name
Test status
Simulation time 6185699879 ps
CPU time 14.82 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:59 PM PST 24
Peak memory 199420 kb
Host smart-9feb7af1-b08d-4906-bc3d-ed0241d616a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128201999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.128201999
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.31077481
Short name T348
Test name
Test status
Simulation time 5244037202 ps
CPU time 69.52 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:58:54 PM PST 24
Peak memory 199468 kb
Host smart-30d4426a-5fed-4bac-bb1c-cab6448cb13b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31077481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.31077481
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.580284217
Short name T410
Test name
Test status
Simulation time 254880127 ps
CPU time 13.19 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 199424 kb
Host smart-c957d933-cdc1-45e8-9863-8cce55e95c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580284217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.580284217
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2822429495
Short name T355
Test name
Test status
Simulation time 3050675011 ps
CPU time 83.63 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:59:21 PM PST 24
Peak memory 199580 kb
Host smart-52b211b0-3b2f-4a30-9b9b-7a34d391701c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822429495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2822429495
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3696360988
Short name T282
Test name
Test status
Simulation time 127632691 ps
CPU time 3.03 seconds
Started Feb 29 12:57:59 PM PST 24
Finished Feb 29 12:58:02 PM PST 24
Peak memory 199200 kb
Host smart-dad4abd3-7e3b-4feb-9d94-1660af614bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696360988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3696360988
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.2201559331
Short name T336
Test name
Test status
Simulation time 18258655582 ps
CPU time 837.47 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 01:11:54 PM PST 24
Peak memory 224076 kb
Host smart-4215e627-e3f3-4759-b1dc-2c090068cd35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201559331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.2201559331
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2243116598
Short name T188
Test name
Test status
Simulation time 37261160 ps
CPU time 1.12 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:43 PM PST 24
Peak memory 198504 kb
Host smart-e5df0559-3149-4fb6-a325-dc2db472c63a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243116598 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.2243116598
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.1931266710
Short name T197
Test name
Test status
Simulation time 192432402396 ps
CPU time 449.21 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 01:05:26 PM PST 24
Peak memory 199428 kb
Host smart-73936b69-ff0c-4a77-b376-e7b157c7b8da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931266710 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.hmac_test_sha_vectors.1931266710
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2114238818
Short name T435
Test name
Test status
Simulation time 34863967976 ps
CPU time 83.03 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:59:16 PM PST 24
Peak memory 199488 kb
Host smart-15673b7d-d610-44df-b5b5-b4fbfabc6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114238818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2114238818
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.4221496204
Short name T400
Test name
Test status
Simulation time 13520326 ps
CPU time 0.55 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:57:54 PM PST 24
Peak memory 193988 kb
Host smart-508dd9e2-415c-4e47-bfd5-acd89e96c8a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221496204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.4221496204
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3452220692
Short name T205
Test name
Test status
Simulation time 990089902 ps
CPU time 33.72 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 220944 kb
Host smart-212e1f0e-7d84-464d-af47-41c74192f8b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3452220692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3452220692
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.988851672
Short name T504
Test name
Test status
Simulation time 995796286 ps
CPU time 22.56 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:58:08 PM PST 24
Peak memory 199476 kb
Host smart-49062b59-7324-430b-bdcb-34eeea907814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988851672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.988851672
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4117883690
Short name T460
Test name
Test status
Simulation time 295439041 ps
CPU time 8.47 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:58:01 PM PST 24
Peak memory 199476 kb
Host smart-606049ff-e701-4c2e-9735-4d05cc1984f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4117883690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4117883690
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3753053660
Short name T485
Test name
Test status
Simulation time 3373602178 ps
CPU time 38.15 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 199436 kb
Host smart-71c76be7-aea9-4be2-924c-48f4d06ed9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753053660 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3753053660
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1709019013
Short name T510
Test name
Test status
Simulation time 64677558746 ps
CPU time 51.03 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199484 kb
Host smart-343adc02-903e-4406-a2de-774db075b133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709019013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1709019013
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.938773319
Short name T404
Test name
Test status
Simulation time 185116033 ps
CPU time 4.02 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:57:59 PM PST 24
Peak memory 199432 kb
Host smart-c1df0a87-035c-4208-a145-1ff02f5acc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938773319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.938773319
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.2042688413
Short name T342
Test name
Test status
Simulation time 47935207371 ps
CPU time 815.27 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 01:11:18 PM PST 24
Peak memory 218012 kb
Host smart-90df68b6-83dd-4a47-8882-bebb2d583ea3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042688413 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.2042688413
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.174482835
Short name T214
Test name
Test status
Simulation time 160541540 ps
CPU time 1.03 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:04 PM PST 24
Peak memory 197932 kb
Host smart-40d48764-f447-4b18-95fe-70bedea86a46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174482835 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.hmac_test_hmac_vectors.174482835
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.877495158
Short name T553
Test name
Test status
Simulation time 152705340302 ps
CPU time 463.66 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 01:05:28 PM PST 24
Peak memory 199424 kb
Host smart-6709e813-aac1-4e22-8537-4735ddc8f980
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877495158 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.hmac_test_sha_vectors.877495158
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.4230621364
Short name T240
Test name
Test status
Simulation time 3841668405 ps
CPU time 46.21 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 199500 kb
Host smart-86454557-79d5-4f2c-9c25-1885dc15a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230621364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.4230621364
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1391496706
Short name T496
Test name
Test status
Simulation time 13303054 ps
CPU time 0.58 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 193816 kb
Host smart-49090558-3149-4142-8171-29a21b9dd7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391496706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1391496706
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.10716778
Short name T439
Test name
Test status
Simulation time 1561570925 ps
CPU time 9.7 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:57:53 PM PST 24
Peak memory 214848 kb
Host smart-12b836b0-0a16-482f-8ea0-7ffa84549ecf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10716778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.10716778
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.1893142573
Short name T527
Test name
Test status
Simulation time 3159469856 ps
CPU time 31.9 seconds
Started Feb 29 12:57:35 PM PST 24
Finished Feb 29 12:58:08 PM PST 24
Peak memory 199580 kb
Host smart-f2789a05-9fbe-4626-80af-41c37df3fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893142573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.1893142573
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.1058390174
Short name T525
Test name
Test status
Simulation time 1334711245 ps
CPU time 72.77 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:58:54 PM PST 24
Peak memory 199440 kb
Host smart-5fc37fa0-8b0c-49da-b964-3c3c7951176b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1058390174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.1058390174
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1537798429
Short name T321
Test name
Test status
Simulation time 816413171 ps
CPU time 39.73 seconds
Started Feb 29 12:57:32 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 199384 kb
Host smart-532aaaf6-15dc-4266-a679-b92784401cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537798429 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1537798429
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2777171504
Short name T316
Test name
Test status
Simulation time 14852015939 ps
CPU time 39.22 seconds
Started Feb 29 12:57:27 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 199516 kb
Host smart-5fb7c567-28a2-4c2e-88b1-1604abecc597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777171504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2777171504
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1883098006
Short name T18
Test name
Test status
Simulation time 83576705 ps
CPU time 0.89 seconds
Started Feb 29 12:57:29 PM PST 24
Finished Feb 29 12:57:30 PM PST 24
Peak memory 216660 kb
Host smart-bf1fd5bd-c92a-44bb-8a3b-8feabfb984a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883098006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1883098006
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1583145048
Short name T570
Test name
Test status
Simulation time 245619747 ps
CPU time 2.75 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:57:45 PM PST 24
Peak memory 199404 kb
Host smart-a4983d5a-cc18-4c7f-8664-44cedfffe50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583145048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1583145048
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2588181078
Short name T489
Test name
Test status
Simulation time 223126791 ps
CPU time 1.24 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:57:52 PM PST 24
Peak memory 198644 kb
Host smart-f31e3ac3-4231-451e-bcdb-0c2960cbccf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588181078 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2588181078
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2031044667
Short name T367
Test name
Test status
Simulation time 44366630105 ps
CPU time 468.81 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 01:05:30 PM PST 24
Peak memory 199304 kb
Host smart-9740c4da-b502-4ccd-b2a1-741e9be3c477
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031044667 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.hmac_test_sha_vectors.2031044667
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3456666935
Short name T290
Test name
Test status
Simulation time 10213623771 ps
CPU time 71.59 seconds
Started Feb 29 12:57:22 PM PST 24
Finished Feb 29 12:58:34 PM PST 24
Peak memory 199496 kb
Host smart-dbe25912-cd04-4ed1-9251-3d52796e9d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456666935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3456666935
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.821416372
Short name T543
Test name
Test status
Simulation time 35640176 ps
CPU time 0.56 seconds
Started Feb 29 12:58:01 PM PST 24
Finished Feb 29 12:58:02 PM PST 24
Peak memory 193816 kb
Host smart-6a7e453f-1ddd-4075-9aa9-9d4a9b06ff5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821416372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.821416372
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.1504777337
Short name T566
Test name
Test status
Simulation time 1041781516 ps
CPU time 16.99 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 207612 kb
Host smart-0d9f7cfb-702a-47cb-b20a-5d245cd52c84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504777337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.1504777337
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.2756394481
Short name T196
Test name
Test status
Simulation time 2805786907 ps
CPU time 44.11 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199408 kb
Host smart-b25bf205-cee0-419c-a663-93d8f58b1700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756394481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.2756394481
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3013088280
Short name T191
Test name
Test status
Simulation time 17900720 ps
CPU time 0.6 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 194860 kb
Host smart-2433bbb0-bd1a-4f49-852c-8a2dcd65ffe4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3013088280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3013088280
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.2959995360
Short name T583
Test name
Test status
Simulation time 24680061598 ps
CPU time 160.72 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 01:00:34 PM PST 24
Peak memory 199480 kb
Host smart-70a10945-45a2-4331-bbca-14b81e7b9487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959995360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.2959995360
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2799882866
Short name T353
Test name
Test status
Simulation time 8206674317 ps
CPU time 35.04 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:31 PM PST 24
Peak memory 199752 kb
Host smart-54c76859-4508-43d0-9f61-a35179696b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799882866 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2799882866
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4039910272
Short name T264
Test name
Test status
Simulation time 168492509 ps
CPU time 1.51 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:56 PM PST 24
Peak memory 199444 kb
Host smart-618d2dcf-6f4f-483a-966f-8280c02f9c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039910272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4039910272
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.186560746
Short name T61
Test name
Test status
Simulation time 127082962724 ps
CPU time 1405.5 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 01:21:09 PM PST 24
Peak memory 199548 kb
Host smart-eb43b74c-ec86-4f33-a5b0-51c9e79fd827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186560746 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.186560746
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.3498195631
Short name T164
Test name
Test status
Simulation time 56225235 ps
CPU time 1.18 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:57:50 PM PST 24
Peak memory 198288 kb
Host smart-3c5017c2-666e-4f10-ab3e-b7109ff00752
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498195631 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.3498195631
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3939261924
Short name T347
Test name
Test status
Simulation time 98991369454 ps
CPU time 414.92 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 01:04:42 PM PST 24
Peak memory 199380 kb
Host smart-0559a291-6cbf-42a2-858d-17393aef2191
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939261924 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_sha_vectors.3939261924
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1011643670
Short name T337
Test name
Test status
Simulation time 10675252297 ps
CPU time 74.07 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 12:59:07 PM PST 24
Peak memory 199480 kb
Host smart-3fde6db8-cc8f-479e-aa58-5784a9bfc227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011643670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1011643670
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2192584715
Short name T138
Test name
Test status
Simulation time 89656771 ps
CPU time 0.58 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 194056 kb
Host smart-448d5ee0-af1a-4285-9272-a7c0a9414b4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192584715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2192584715
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1262761096
Short name T341
Test name
Test status
Simulation time 503277072 ps
CPU time 3.72 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:57:49 PM PST 24
Peak memory 199432 kb
Host smart-9a1898ef-ec1d-47cd-8696-3bff06ba3e60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1262761096 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1262761096
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2076591225
Short name T302
Test name
Test status
Simulation time 497167273 ps
CPU time 23.28 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 199300 kb
Host smart-f906b221-7145-4081-bf36-e1bbef5c0d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076591225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2076591225
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.2955354637
Short name T417
Test name
Test status
Simulation time 4344989217 ps
CPU time 117.21 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:59:48 PM PST 24
Peak memory 199472 kb
Host smart-4326c00e-842e-4034-be29-9829a31c4562
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955354637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.2955354637
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.2764614450
Short name T398
Test name
Test status
Simulation time 10361932651 ps
CPU time 129.75 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 01:00:04 PM PST 24
Peak memory 199532 kb
Host smart-c228a55e-7cdd-428a-abdd-fa0f518071d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764614450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.2764614450
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.2043539307
Short name T364
Test name
Test status
Simulation time 5091190759 ps
CPU time 78.43 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 12:59:15 PM PST 24
Peak memory 199516 kb
Host smart-6f3ce863-6bee-4c9f-a68a-ceb77ceab1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043539307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.2043539307
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3340233410
Short name T567
Test name
Test status
Simulation time 1231649848 ps
CPU time 3.88 seconds
Started Feb 29 12:58:03 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 199464 kb
Host smart-e1d8b14f-e4c5-4311-a618-958c750ea7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340233410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3340233410
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.4011484939
Short name T465
Test name
Test status
Simulation time 60622104 ps
CPU time 1.12 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:57:54 PM PST 24
Peak memory 197772 kb
Host smart-19eb67a0-b5e8-4c80-a119-d032bd5f1d1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011484939 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.4011484939
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.302404620
Short name T592
Test name
Test status
Simulation time 28955447488 ps
CPU time 384.35 seconds
Started Feb 29 12:58:03 PM PST 24
Finished Feb 29 01:04:28 PM PST 24
Peak memory 199428 kb
Host smart-55b25bc3-7337-4d5f-b70f-6591f9ec77cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302404620 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.hmac_test_sha_vectors.302404620
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2631294527
Short name T180
Test name
Test status
Simulation time 10069407446 ps
CPU time 41.63 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199500 kb
Host smart-07d0fef5-4264-4501-9324-7fbf4702c770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631294527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2631294527
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3372495718
Short name T10
Test name
Test status
Simulation time 16017240 ps
CPU time 0.56 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 193820 kb
Host smart-785dff10-b265-4d0f-a8a0-4c7326f986dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372495718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3372495718
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.406597446
Short name T468
Test name
Test status
Simulation time 3759197935 ps
CPU time 38.95 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:45 PM PST 24
Peak memory 226848 kb
Host smart-9dc69183-0ae2-4b32-a948-554a2e30d632
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406597446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.406597446
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1024238770
Short name T454
Test name
Test status
Simulation time 2788566005 ps
CPU time 26.83 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:49 PM PST 24
Peak memory 199472 kb
Host smart-9bdb5821-0e70-481b-acdc-d215e57771f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024238770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1024238770
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3290774332
Short name T453
Test name
Test status
Simulation time 1545291083 ps
CPU time 84.86 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:59:40 PM PST 24
Peak memory 199388 kb
Host smart-6f6ad5da-ad07-47f2-ac82-54e133fe52ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290774332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3290774332
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1645119596
Short name T331
Test name
Test status
Simulation time 8771949783 ps
CPU time 158.27 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 199468 kb
Host smart-6a04f1ff-9791-40f0-b589-5c2f6abe833d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645119596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1645119596
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.633747871
Short name T279
Test name
Test status
Simulation time 8939444941 ps
CPU time 28.05 seconds
Started Feb 29 12:58:20 PM PST 24
Finished Feb 29 12:58:49 PM PST 24
Peak memory 199456 kb
Host smart-3675dbaf-6a97-4999-913f-f7279aebf009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633747871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.633747871
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.1380872907
Short name T297
Test name
Test status
Simulation time 621115323 ps
CPU time 2.45 seconds
Started Feb 29 12:58:01 PM PST 24
Finished Feb 29 12:58:04 PM PST 24
Peak memory 199448 kb
Host smart-6744b9f1-bab9-4e43-8939-84d1bd1f9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380872907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.1380872907
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2744667931
Short name T429
Test name
Test status
Simulation time 22666412927 ps
CPU time 1106.49 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 01:16:35 PM PST 24
Peak memory 227096 kb
Host smart-904691fc-1e79-4a81-ab63-75128ac1a580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744667931 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2744667931
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3909981744
Short name T242
Test name
Test status
Simulation time 111862383 ps
CPU time 1.11 seconds
Started Feb 29 12:57:59 PM PST 24
Finished Feb 29 12:58:00 PM PST 24
Peak memory 198036 kb
Host smart-75bde762-5f0c-4a28-88e2-6caf87e9008a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909981744 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3909981744
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3058811315
Short name T484
Test name
Test status
Simulation time 132997523486 ps
CPU time 442.62 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 01:05:43 PM PST 24
Peak memory 199612 kb
Host smart-7199ae95-9d79-439f-ac56-f4cea61bf26b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058811315 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_sha_vectors.3058811315
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.2345551263
Short name T223
Test name
Test status
Simulation time 986137569 ps
CPU time 4.52 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:07 PM PST 24
Peak memory 199508 kb
Host smart-a3fc4107-b1a9-47cc-b663-bf67a3a7532f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345551263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.2345551263
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2307239263
Short name T444
Test name
Test status
Simulation time 12547274 ps
CPU time 0.55 seconds
Started Feb 29 12:58:11 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 193800 kb
Host smart-4a30259a-519e-4485-88bc-789f2db82958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307239263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2307239263
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.2612364667
Short name T403
Test name
Test status
Simulation time 1315548207 ps
CPU time 49.16 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 12:58:58 PM PST 24
Peak memory 227104 kb
Host smart-2dc7e289-b92e-4300-8cff-ecd2a1ad48b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2612364667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.2612364667
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1178130919
Short name T442
Test name
Test status
Simulation time 2270269622 ps
CPU time 21.68 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199508 kb
Host smart-22e0ef83-6fd4-44c2-bb1c-88a29086d00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178130919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1178130919
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.1360991434
Short name T315
Test name
Test status
Simulation time 3537958948 ps
CPU time 45.3 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:52 PM PST 24
Peak memory 199396 kb
Host smart-eba61041-5c86-475b-8745-534fa0ad5ded
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360991434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.1360991434
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.700224257
Short name T521
Test name
Test status
Simulation time 14145364174 ps
CPU time 43.56 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:59:07 PM PST 24
Peak memory 199356 kb
Host smart-264a890a-cd22-4bb9-926b-8dcfa89fbddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700224257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.700224257
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1141579716
Short name T438
Test name
Test status
Simulation time 1596712054 ps
CPU time 29.82 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199480 kb
Host smart-9c660581-0d41-47df-bea2-6929a2653e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141579716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1141579716
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.171617704
Short name T286
Test name
Test status
Simulation time 272567714 ps
CPU time 1.65 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:04 PM PST 24
Peak memory 199368 kb
Host smart-7377f10c-7d8f-40c3-8605-c8b9561ea17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171617704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.171617704
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.2552263039
Short name T329
Test name
Test status
Simulation time 46153870773 ps
CPU time 554.74 seconds
Started Feb 29 12:57:57 PM PST 24
Finished Feb 29 01:07:13 PM PST 24
Peak memory 199520 kb
Host smart-063614b4-1ac3-4d49-9c64-ceeff1733ad2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552263039 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.2552263039
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.201047230
Short name T374
Test name
Test status
Simulation time 152496804 ps
CPU time 0.93 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:09 PM PST 24
Peak memory 197668 kb
Host smart-ccf01151-57a8-4c79-86e1-cd4af5a99782
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201047230 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.201047230
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.4067789915
Short name T252
Test name
Test status
Simulation time 32268056625 ps
CPU time 401.43 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 01:05:03 PM PST 24
Peak memory 199452 kb
Host smart-5bef5f22-b54e-4f87-a924-648d2d7c2942
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067789915 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_sha_vectors.4067789915
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2633581162
Short name T494
Test name
Test status
Simulation time 15931350472 ps
CPU time 71.72 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:59:22 PM PST 24
Peak memory 199500 kb
Host smart-5e12f9cd-7f94-43d3-90aa-7248079d7b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633581162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2633581162
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.831207532
Short name T128
Test name
Test status
Simulation time 35536211 ps
CPU time 0.56 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:58:11 PM PST 24
Peak memory 194004 kb
Host smart-62537fee-34dc-4cfa-bf79-116255302aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831207532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.831207532
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1393936043
Short name T283
Test name
Test status
Simulation time 4280397845 ps
CPU time 31.36 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 224116 kb
Host smart-c8481eab-ea76-4f46-971a-3242a25a3368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393936043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1393936043
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1850679277
Short name T301
Test name
Test status
Simulation time 10205236581 ps
CPU time 35.85 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:58:51 PM PST 24
Peak memory 199440 kb
Host smart-ac0722b6-1209-4e14-8d9b-a1b23bb665bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850679277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1850679277
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.3524579755
Short name T221
Test name
Test status
Simulation time 495347070 ps
CPU time 6.4 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:03 PM PST 24
Peak memory 199420 kb
Host smart-5847b447-3b72-40eb-988d-072e542b8f2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3524579755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.3524579755
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.2058452689
Short name T399
Test name
Test status
Simulation time 270263301 ps
CPU time 3.9 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:11 PM PST 24
Peak memory 199268 kb
Host smart-7db973dd-f974-44c1-b488-b482e4cd0e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058452689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.2058452689
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1722814725
Short name T451
Test name
Test status
Simulation time 2577960193 ps
CPU time 35.8 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199560 kb
Host smart-890cebf0-5933-4492-a909-3e29f9bf5618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722814725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1722814725
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1561737968
Short name T179
Test name
Test status
Simulation time 1111208244 ps
CPU time 3.61 seconds
Started Feb 29 12:58:09 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 199420 kb
Host smart-378d13c4-bcd4-4afb-9da9-2a79ade34bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561737968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1561737968
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.3643575263
Short name T102
Test name
Test status
Simulation time 14567008713 ps
CPU time 717.69 seconds
Started Feb 29 12:58:03 PM PST 24
Finished Feb 29 01:10:01 PM PST 24
Peak memory 207728 kb
Host smart-2399f43d-7da2-41e4-9407-5f48038cc22b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643575263 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.3643575263
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.1763051348
Short name T411
Test name
Test status
Simulation time 53877715 ps
CPU time 0.98 seconds
Started Feb 29 12:58:12 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 196956 kb
Host smart-92b8af9e-5ee0-45fc-a335-875083aef071
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763051348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.1763051348
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.1366627905
Short name T46
Test name
Test status
Simulation time 38951557514 ps
CPU time 358.1 seconds
Started Feb 29 12:58:09 PM PST 24
Finished Feb 29 01:04:08 PM PST 24
Peak memory 199432 kb
Host smart-33b49c5c-1791-41f2-9217-cc04e886b399
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366627905 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_sha_vectors.1366627905
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3523270077
Short name T190
Test name
Test status
Simulation time 3133204676 ps
CPU time 39.67 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:45 PM PST 24
Peak memory 199504 kb
Host smart-ea34e9f4-8b32-455b-a10c-1c4c63d3e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523270077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3523270077
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.3188214063
Short name T9
Test name
Test status
Simulation time 84289997 ps
CPU time 0.58 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:26 PM PST 24
Peak memory 194036 kb
Host smart-22ba2572-a53e-4e1c-9cbd-6a3b0793b3b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188214063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.3188214063
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1936658830
Short name T294
Test name
Test status
Simulation time 11022317754 ps
CPU time 42.2 seconds
Started Feb 29 12:57:52 PM PST 24
Finished Feb 29 12:58:35 PM PST 24
Peak memory 222756 kb
Host smart-7674f170-c3f5-4e1d-a838-24409650cbe2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1936658830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1936658830
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1217540019
Short name T564
Test name
Test status
Simulation time 315391316 ps
CPU time 6.12 seconds
Started Feb 29 12:58:00 PM PST 24
Finished Feb 29 12:58:06 PM PST 24
Peak memory 199408 kb
Host smart-71e2d75f-73ae-430a-bcba-9059c18bba26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217540019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1217540019
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1995508669
Short name T574
Test name
Test status
Simulation time 1166769006 ps
CPU time 67.37 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:59:31 PM PST 24
Peak memory 199508 kb
Host smart-27758df8-3f40-4da2-8ca5-d593684cf6e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1995508669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1995508669
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.1826281730
Short name T409
Test name
Test status
Simulation time 17434348440 ps
CPU time 74.56 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:31 PM PST 24
Peak memory 199464 kb
Host smart-32d61c51-5b52-4c85-8e4a-37ab17664329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826281730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.1826281730
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1559837389
Short name T533
Test name
Test status
Simulation time 1613894109 ps
CPU time 19.28 seconds
Started Feb 29 12:58:12 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199420 kb
Host smart-cf941f1c-1466-43b6-8e12-3e8ee9e3436e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559837389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1559837389
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.3718753195
Short name T273
Test name
Test status
Simulation time 795715544 ps
CPU time 1.79 seconds
Started Feb 29 12:58:00 PM PST 24
Finished Feb 29 12:58:03 PM PST 24
Peak memory 199184 kb
Host smart-600e8ab9-1339-400a-afa4-35ff8a1f3aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718753195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.3718753195
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.4228516238
Short name T84
Test name
Test status
Simulation time 70691841339 ps
CPU time 1156.81 seconds
Started Feb 29 12:58:09 PM PST 24
Finished Feb 29 01:17:27 PM PST 24
Peak memory 199556 kb
Host smart-1ba0a99a-4a6e-41e4-b713-bf54b5d2610c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228516238 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.4228516238
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.240190411
Short name T236
Test name
Test status
Simulation time 668428160 ps
CPU time 0.89 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 196556 kb
Host smart-f31cb846-99ea-4812-8187-9d13f674fbee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240190411 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.240190411
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.3727621973
Short name T350
Test name
Test status
Simulation time 7250927995 ps
CPU time 368.9 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 01:04:28 PM PST 24
Peak memory 199404 kb
Host smart-9930633d-95cd-451f-960d-e4f52555f3f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727621973 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_sha_vectors.3727621973
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3601653950
Short name T213
Test name
Test status
Simulation time 9835514223 ps
CPU time 42.7 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:48 PM PST 24
Peak memory 199472 kb
Host smart-269a7412-e1f5-4a4a-bc18-7f1e6bf725f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601653950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3601653950
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3098677492
Short name T293
Test name
Test status
Simulation time 41932085 ps
CPU time 0.54 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:57:56 PM PST 24
Peak memory 193776 kb
Host smart-cb5a684b-5a6b-4428-82ae-a54128a73737
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098677492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3098677492
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.746876464
Short name T577
Test name
Test status
Simulation time 1729973311 ps
CPU time 16.23 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:58:10 PM PST 24
Peak memory 220984 kb
Host smart-cd8227c0-d78b-4648-a306-7d876073dcd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=746876464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.746876464
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.1713970506
Short name T312
Test name
Test status
Simulation time 2393196982 ps
CPU time 37.08 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:59:03 PM PST 24
Peak memory 199496 kb
Host smart-6e209e9d-3e9c-450a-9843-7bd8fa111fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713970506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.1713970506
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1317231125
Short name T111
Test name
Test status
Simulation time 2268415215 ps
CPU time 122.67 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 199536 kb
Host smart-3ed41b09-b5ed-482b-b71f-bdf6a723b303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1317231125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1317231125
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.1604515936
Short name T531
Test name
Test status
Simulation time 1117980653 ps
CPU time 58.9 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 12:59:19 PM PST 24
Peak memory 199484 kb
Host smart-1ab61f73-393a-47ba-a31d-55186d13ae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604515936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.1604515936
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3173231095
Short name T377
Test name
Test status
Simulation time 2404654350 ps
CPU time 30.32 seconds
Started Feb 29 12:58:11 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 199500 kb
Host smart-3829564d-1a77-4d58-8a2e-9012be359678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173231095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3173231095
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.3825532856
Short name T271
Test name
Test status
Simulation time 173375331 ps
CPU time 2.4 seconds
Started Feb 29 12:58:11 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 199420 kb
Host smart-669917c8-5c66-4ff9-a32a-7260dae5e8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825532856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.3825532856
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3743600848
Short name T98
Test name
Test status
Simulation time 982913975508 ps
CPU time 1563.68 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 01:23:59 PM PST 24
Peak memory 240412 kb
Host smart-569f62da-f587-4664-a99b-9e9f2ee8a678
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743600848 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3743600848
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3296259587
Short name T580
Test name
Test status
Simulation time 332154484 ps
CPU time 1.06 seconds
Started Feb 29 12:58:04 PM PST 24
Finished Feb 29 12:58:05 PM PST 24
Peak memory 198248 kb
Host smart-d9bf83a5-9252-473b-8c90-eb478614ae50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296259587 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.3296259587
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.2445133298
Short name T182
Test name
Test status
Simulation time 7494863240 ps
CPU time 361.12 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 01:04:17 PM PST 24
Peak memory 199420 kb
Host smart-2f6bf08b-2bab-49a6-ae7e-3839db82b4fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445133298 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_sha_vectors.2445133298
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3737200461
Short name T13
Test name
Test status
Simulation time 1526521791 ps
CPU time 3.65 seconds
Started Feb 29 12:57:56 PM PST 24
Finished Feb 29 12:58:00 PM PST 24
Peak memory 199444 kb
Host smart-c484de5f-2651-41ec-b59c-a3c9a964d17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737200461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3737200461
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1559400812
Short name T395
Test name
Test status
Simulation time 36724558 ps
CPU time 0.55 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 193812 kb
Host smart-703fc9e9-1a1e-4c2f-9090-7615698098c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559400812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1559400812
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3080625732
Short name T335
Test name
Test status
Simulation time 151017724 ps
CPU time 1.62 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 12:58:09 PM PST 24
Peak memory 199448 kb
Host smart-3266d004-6682-4aac-ad0e-5d5cc62b186a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080625732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3080625732
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.1430678922
Short name T284
Test name
Test status
Simulation time 4703941531 ps
CPU time 31.78 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 199380 kb
Host smart-a94df235-f445-43ec-98ca-379b0d921acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430678922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.1430678922
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3679170009
Short name T311
Test name
Test status
Simulation time 12490083105 ps
CPU time 126.54 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 01:00:24 PM PST 24
Peak memory 199488 kb
Host smart-f9e9069c-0b3b-43bf-b33e-b119b54b5444
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679170009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3679170009
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.3418930654
Short name T87
Test name
Test status
Simulation time 7151803063 ps
CPU time 27.04 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 12:58:47 PM PST 24
Peak memory 199484 kb
Host smart-f2cedfbd-5ce1-4967-ac1f-465dfc192398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418930654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.3418930654
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.1206396892
Short name T427
Test name
Test status
Simulation time 3053957887 ps
CPU time 57.67 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:59:15 PM PST 24
Peak memory 199472 kb
Host smart-c49e45cc-3948-486c-bccf-4706a96f15d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206396892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.1206396892
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1995648491
Short name T415
Test name
Test status
Simulation time 444094306 ps
CPU time 2.73 seconds
Started Feb 29 12:58:02 PM PST 24
Finished Feb 29 12:58:05 PM PST 24
Peak memory 199328 kb
Host smart-1568477c-5b3f-40a9-ba12-dd9e6a508a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995648491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1995648491
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3027003683
Short name T576
Test name
Test status
Simulation time 156207076 ps
CPU time 1.11 seconds
Started Feb 29 12:58:20 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 198432 kb
Host smart-732d3530-75cf-4399-bd75-35fb18e04672
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027003683 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3027003683
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.1049293457
Short name T578
Test name
Test status
Simulation time 28074579378 ps
CPU time 451 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 01:05:59 PM PST 24
Peak memory 199408 kb
Host smart-3146a51a-01b9-4e31-bd4c-2375dd768099
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049293457 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_sha_vectors.1049293457
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3937994920
Short name T229
Test name
Test status
Simulation time 2842216461 ps
CPU time 49.08 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:59:13 PM PST 24
Peak memory 199500 kb
Host smart-a213155a-a56f-40b7-92c5-36b75a3459b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937994920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3937994920
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.2090810116
Short name T428
Test name
Test status
Simulation time 42614642 ps
CPU time 0.58 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 194832 kb
Host smart-3f47b32c-0adc-4d37-8045-e8eb94a96d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090810116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.2090810116
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2702895114
Short name T380
Test name
Test status
Simulation time 529248610 ps
CPU time 18.53 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:58:45 PM PST 24
Peak memory 214960 kb
Host smart-332f618e-f3e3-48bc-a65d-759d37eeffdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2702895114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2702895114
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1334554047
Short name T491
Test name
Test status
Simulation time 2444518325 ps
CPU time 30.71 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 12:58:51 PM PST 24
Peak memory 199496 kb
Host smart-b0daf22a-52ba-433f-9f68-cca3f768002b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334554047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1334554047
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.4112801193
Short name T183
Test name
Test status
Simulation time 1548877764 ps
CPU time 22.34 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 199420 kb
Host smart-3d770e83-fe7f-4e1d-a37a-3ce64de5ae70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112801193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.4112801193
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2597901495
Short name T551
Test name
Test status
Simulation time 49644336364 ps
CPU time 135.96 seconds
Started Feb 29 12:57:58 PM PST 24
Finished Feb 29 01:00:14 PM PST 24
Peak memory 199480 kb
Host smart-4b07f972-9647-43e3-9a00-e3188f991d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597901495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2597901495
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1459282843
Short name T449
Test name
Test status
Simulation time 7713743945 ps
CPU time 35.13 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 199516 kb
Host smart-09f5772d-2b19-44ad-aecb-5e748db0397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459282843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1459282843
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3363750991
Short name T326
Test name
Test status
Simulation time 389814824 ps
CPU time 4.19 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 199388 kb
Host smart-e1ff3099-4a68-4fdf-8b07-32f38496e266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363750991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3363750991
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.4022943211
Short name T97
Test name
Test status
Simulation time 57531228260 ps
CPU time 1335.3 seconds
Started Feb 29 12:58:07 PM PST 24
Finished Feb 29 01:20:23 PM PST 24
Peak memory 240512 kb
Host smart-037e18b3-19b8-4b1f-bc30-488afcb52539
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022943211 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.4022943211
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2940485280
Short name T159
Test name
Test status
Simulation time 144956696 ps
CPU time 0.93 seconds
Started Feb 29 12:58:04 PM PST 24
Finished Feb 29 12:58:05 PM PST 24
Peak memory 197280 kb
Host smart-6f86b4b3-e732-4532-b605-3863fde740ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940485280 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.2940485280
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.2123961932
Short name T127
Test name
Test status
Simulation time 121277400005 ps
CPU time 446.81 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 01:05:36 PM PST 24
Peak memory 199476 kb
Host smart-3e4166c3-d02c-4934-aed0-981be4782095
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123961932 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_sha_vectors.2123961932
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.55834558
Short name T292
Test name
Test status
Simulation time 6938615849 ps
CPU time 22.68 seconds
Started Feb 29 12:57:58 PM PST 24
Finished Feb 29 12:58:21 PM PST 24
Peak memory 199372 kb
Host smart-a144ec18-0d02-410d-87cd-c81165bf6054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55834558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.55834558
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2420426295
Short name T483
Test name
Test status
Simulation time 35371374 ps
CPU time 0.55 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 193760 kb
Host smart-b42506ea-f2fc-4ca5-b36f-2dd8a2a6926b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420426295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2420426295
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2472774546
Short name T359
Test name
Test status
Simulation time 1055622226 ps
CPU time 39.3 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:54 PM PST 24
Peak memory 224760 kb
Host smart-7456e3c0-85bb-4fc5-acce-eda03cf1081a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2472774546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2472774546
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3428544522
Short name T154
Test name
Test status
Simulation time 1875770462 ps
CPU time 9.99 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 199360 kb
Host smart-6178cd80-0751-4a8f-bcac-69a93cb94a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428544522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3428544522
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3292752994
Short name T405
Test name
Test status
Simulation time 1151590913 ps
CPU time 59.39 seconds
Started Feb 29 12:58:13 PM PST 24
Finished Feb 29 12:59:13 PM PST 24
Peak memory 199432 kb
Host smart-982cbc78-743d-43f6-93fb-3145bbc87baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3292752994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3292752994
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.284022246
Short name T171
Test name
Test status
Simulation time 20836818935 ps
CPU time 102.26 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 01:00:11 PM PST 24
Peak memory 199480 kb
Host smart-4affd7cc-0ef4-4be4-8b65-470c3a8650ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284022246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.284022246
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.3363434442
Short name T104
Test name
Test status
Simulation time 3040435503 ps
CPU time 52.75 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 12:59:33 PM PST 24
Peak memory 199488 kb
Host smart-2aacf7d8-28dd-444b-95b0-5d46abba3a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363434442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.3363434442
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1518503942
Short name T218
Test name
Test status
Simulation time 55356545 ps
CPU time 0.75 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 195600 kb
Host smart-73e1d69b-5b3e-47ea-bbc9-e3fc6007d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518503942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1518503942
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.914117776
Short name T265
Test name
Test status
Simulation time 201448564786 ps
CPU time 1044.07 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 01:15:40 PM PST 24
Peak memory 231800 kb
Host smart-4e7eb06e-4232-466e-bbbb-67061d78806b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914117776 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.914117776
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.642834126
Short name T257
Test name
Test status
Simulation time 60907348 ps
CPU time 1.09 seconds
Started Feb 29 12:58:20 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 198352 kb
Host smart-7f9d26aa-1456-46c0-869d-39ab044104ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642834126 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_hmac_vectors.642834126
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.2780500148
Short name T588
Test name
Test status
Simulation time 26399217291 ps
CPU time 444.14 seconds
Started Feb 29 12:58:09 PM PST 24
Finished Feb 29 01:05:34 PM PST 24
Peak memory 199384 kb
Host smart-49c5c6b2-23be-454c-979c-341c1672abbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780500148 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.hmac_test_sha_vectors.2780500148
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2002419685
Short name T505
Test name
Test status
Simulation time 10725550623 ps
CPU time 43.78 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:58 PM PST 24
Peak memory 199504 kb
Host smart-38455620-31fb-4e5b-aeb6-6770fdd68b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002419685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2002419685
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.3101379882
Short name T173
Test name
Test status
Simulation time 19880602 ps
CPU time 0.54 seconds
Started Feb 29 12:57:34 PM PST 24
Finished Feb 29 12:57:35 PM PST 24
Peak memory 194016 kb
Host smart-faeafeb2-1a2e-4851-832f-6727aa4d2abc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101379882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.3101379882
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.671434363
Short name T38
Test name
Test status
Simulation time 3100483619 ps
CPU time 19.71 seconds
Started Feb 29 12:57:30 PM PST 24
Finished Feb 29 12:57:50 PM PST 24
Peak memory 207924 kb
Host smart-215974b6-f5ce-409e-ad0f-3ccfee60c9fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671434363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.671434363
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.2773056957
Short name T325
Test name
Test status
Simulation time 4029387201 ps
CPU time 42.87 seconds
Started Feb 29 12:57:25 PM PST 24
Finished Feb 29 12:58:08 PM PST 24
Peak memory 199508 kb
Host smart-2c32f0aa-22f5-49ce-bd01-c84bbc192823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773056957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.2773056957
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1405699458
Short name T41
Test name
Test status
Simulation time 2434422000 ps
CPU time 61.89 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199460 kb
Host smart-a0a10060-c858-4504-8999-3193d42f5bb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405699458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1405699458
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.585497044
Short name T593
Test name
Test status
Simulation time 8292044256 ps
CPU time 122.52 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:59:44 PM PST 24
Peak memory 199524 kb
Host smart-ccd4c9ba-ed7a-4ec0-8395-f6f84d036b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585497044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.585497044
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1177230777
Short name T162
Test name
Test status
Simulation time 15128787222 ps
CPU time 45.2 seconds
Started Feb 29 12:57:27 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 199480 kb
Host smart-07ef195a-6b80-402c-9e65-e880d8e4e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177230777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1177230777
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.179800583
Short name T19
Test name
Test status
Simulation time 155408014 ps
CPU time 0.78 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:57:38 PM PST 24
Peak memory 216752 kb
Host smart-5faf5666-023e-4c34-97ef-b7bc5e071ff8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179800583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.179800583
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.3780579422
Short name T524
Test name
Test status
Simulation time 1039425855 ps
CPU time 1.83 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:57:40 PM PST 24
Peak memory 199380 kb
Host smart-19141fcd-77bf-4a6c-87f6-6305c4c90911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780579422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3780579422
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2015545801
Short name T517
Test name
Test status
Simulation time 3465057750 ps
CPU time 24.22 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:58:02 PM PST 24
Peak memory 199508 kb
Host smart-ad754e4f-bb9a-4bd8-a755-e91bb436f5f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015545801 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2015545801
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.2024578984
Short name T432
Test name
Test status
Simulation time 105846213 ps
CPU time 1.18 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:57:38 PM PST 24
Peak memory 197128 kb
Host smart-14e08d8c-e187-440c-883e-5f1dea0e5945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024578984 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.hmac_test_hmac_vectors.2024578984
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.1890840240
Short name T170
Test name
Test status
Simulation time 6971141340 ps
CPU time 350.64 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 01:03:22 PM PST 24
Peak memory 199336 kb
Host smart-d0d97083-abd0-4fa6-81af-716aa2a427d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890840240 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_sha_vectors.1890840240
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2325770990
Short name T385
Test name
Test status
Simulation time 4937691196 ps
CPU time 62.06 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:58:45 PM PST 24
Peak memory 199464 kb
Host smart-384e98e3-038b-4614-9a66-05d2f27e9ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325770990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2325770990
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.2483741934
Short name T351
Test name
Test status
Simulation time 18643800 ps
CPU time 0.55 seconds
Started Feb 29 12:58:11 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 193996 kb
Host smart-e30cba1b-f9f0-4e18-8456-3b26fa5919f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483741934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.2483741934
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3927484502
Short name T389
Test name
Test status
Simulation time 6904355119 ps
CPU time 19.38 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:33 PM PST 24
Peak memory 215904 kb
Host smart-4af4e429-82c4-4d91-bc4c-2fa1c4a8e0eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3927484502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3927484502
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1331695158
Short name T418
Test name
Test status
Simulation time 3503486149 ps
CPU time 27.82 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:55 PM PST 24
Peak memory 199380 kb
Host smart-d02e2eb6-8b7b-43b5-b3a9-9fdc68104c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331695158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1331695158
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.2700301415
Short name T42
Test name
Test status
Simulation time 8474571034 ps
CPU time 112.45 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 01:00:17 PM PST 24
Peak memory 199440 kb
Host smart-369c04b5-6bc3-4ede-bf91-af40715ac42f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2700301415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.2700301415
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3011280484
Short name T361
Test name
Test status
Simulation time 5066089892 ps
CPU time 89.89 seconds
Started Feb 29 12:58:13 PM PST 24
Finished Feb 29 12:59:43 PM PST 24
Peak memory 199460 kb
Host smart-84b921db-d3b8-47cd-b146-b3a4c4a6a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011280484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3011280484
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3733500718
Short name T413
Test name
Test status
Simulation time 2383866198 ps
CPU time 59.58 seconds
Started Feb 29 12:58:04 PM PST 24
Finished Feb 29 12:59:03 PM PST 24
Peak memory 199476 kb
Host smart-b8c4bfeb-9b12-49b1-a40b-a80c42ed1abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733500718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3733500718
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2541966514
Short name T287
Test name
Test status
Simulation time 145522583 ps
CPU time 0.96 seconds
Started Feb 29 12:58:10 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 197296 kb
Host smart-11a78fdd-631a-4bc7-b0d0-33dd9bce365b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541966514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2541966514
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1511792715
Short name T63
Test name
Test status
Simulation time 73423185145 ps
CPU time 873.91 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 01:12:58 PM PST 24
Peak memory 199540 kb
Host smart-141cc50c-60cf-4c07-bcca-080551b170b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511792715 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1511792715
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.524922076
Short name T530
Test name
Test status
Simulation time 217577470 ps
CPU time 1.14 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:58:16 PM PST 24
Peak memory 198288 kb
Host smart-3710c7e1-6577-4fd0-b62a-218a4df890ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524922076 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_hmac_vectors.524922076
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1091978039
Short name T16
Test name
Test status
Simulation time 97213073642 ps
CPU time 551.58 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 01:07:34 PM PST 24
Peak memory 199420 kb
Host smart-143d7006-9e19-43ed-b949-ab968cb43bbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091978039 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.hmac_test_sha_vectors.1091978039
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.1151612715
Short name T497
Test name
Test status
Simulation time 3123283052 ps
CPU time 50.32 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:07 PM PST 24
Peak memory 199536 kb
Host smart-96ed1183-6871-4fac-bd18-93a760db8a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151612715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.1151612715
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3552809722
Short name T589
Test name
Test status
Simulation time 28265847 ps
CPU time 0.57 seconds
Started Feb 29 12:58:20 PM PST 24
Finished Feb 29 12:58:21 PM PST 24
Peak memory 193760 kb
Host smart-83af332a-094d-468a-9157-40991fa15ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552809722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3552809722
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2757144608
Short name T243
Test name
Test status
Simulation time 1910682144 ps
CPU time 26.73 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:52 PM PST 24
Peak memory 199396 kb
Host smart-07b09e28-d18a-4094-a3ec-b3e16eefa182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757144608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2757144608
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3974924333
Short name T507
Test name
Test status
Simulation time 2085828728 ps
CPU time 55.07 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:59:19 PM PST 24
Peak memory 199384 kb
Host smart-fcd8e7e7-e855-4508-b7ec-48dc035fc903
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974924333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3974924333
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.264213118
Short name T255
Test name
Test status
Simulation time 1064151158 ps
CPU time 56.5 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:59:21 PM PST 24
Peak memory 199428 kb
Host smart-554724fa-2dc5-4804-80df-e8845c6c6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264213118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.264213118
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3939862675
Short name T498
Test name
Test status
Simulation time 1689525836 ps
CPU time 43.15 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:59:09 PM PST 24
Peak memory 199500 kb
Host smart-eb3c5d69-9dd4-4c17-84ea-8b2340c840e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939862675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3939862675
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2881474417
Short name T368
Test name
Test status
Simulation time 527834508 ps
CPU time 1.84 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:58:19 PM PST 24
Peak memory 199408 kb
Host smart-59588bbf-9f3a-45c7-828a-d1ed1fa695d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881474417 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2881474417
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3485470424
Short name T388
Test name
Test status
Simulation time 58499839 ps
CPU time 1.21 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 198144 kb
Host smart-4d468416-b8a6-4882-befe-cded9bb4a415
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485470424 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3485470424
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2342223967
Short name T363
Test name
Test status
Simulation time 2081332138 ps
CPU time 15.61 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:58:41 PM PST 24
Peak memory 199392 kb
Host smart-0271892c-eedf-4374-a0f8-c3a49ec2135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342223967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2342223967
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.292196271
Short name T25
Test name
Test status
Simulation time 12080800 ps
CPU time 0.57 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 193860 kb
Host smart-e2cb0c7a-46e6-4484-a702-1f0218fd1370
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292196271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.292196271
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3021660799
Short name T8
Test name
Test status
Simulation time 5297373988 ps
CPU time 56.73 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:59:26 PM PST 24
Peak memory 222340 kb
Host smart-b28e32bf-6a7a-42e3-83a1-6342e01dd263
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021660799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3021660799
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3035673174
Short name T65
Test name
Test status
Simulation time 380849143 ps
CPU time 8.68 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:58:34 PM PST 24
Peak memory 199488 kb
Host smart-392378be-6a0a-494d-9e71-f73180925f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035673174 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3035673174
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1699142046
Short name T168
Test name
Test status
Simulation time 1785207427 ps
CPU time 88.12 seconds
Started Feb 29 12:58:30 PM PST 24
Finished Feb 29 12:59:59 PM PST 24
Peak memory 199464 kb
Host smart-b084db78-2972-4716-a064-d4d886c01e9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1699142046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1699142046
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3250590556
Short name T486
Test name
Test status
Simulation time 12320373635 ps
CPU time 81.34 seconds
Started Feb 29 12:58:04 PM PST 24
Finished Feb 29 12:59:26 PM PST 24
Peak memory 199528 kb
Host smart-ae13cd5a-cbd7-4b81-a00d-a6fdad74d792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250590556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3250590556
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3478857568
Short name T327
Test name
Test status
Simulation time 4603867524 ps
CPU time 62.48 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:59:27 PM PST 24
Peak memory 199500 kb
Host smart-d30a4e58-89f1-4333-b35d-64542f3abc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478857568 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3478857568
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.17629710
Short name T585
Test name
Test status
Simulation time 1479599376 ps
CPU time 3.95 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:58:28 PM PST 24
Peak memory 199408 kb
Host smart-0573a270-952d-4403-b27c-322df05b2794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17629710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.17629710
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.624649281
Short name T376
Test name
Test status
Simulation time 38828253 ps
CPU time 0.94 seconds
Started Feb 29 12:58:12 PM PST 24
Finished Feb 29 12:58:13 PM PST 24
Peak memory 197436 kb
Host smart-ea817886-7565-4e4e-9d48-d379a218a243
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624649281 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.624649281
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.801230485
Short name T142
Test name
Test status
Simulation time 26759522634 ps
CPU time 435 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 01:05:34 PM PST 24
Peak memory 199412 kb
Host smart-d91a0ccf-c536-4984-856b-bfa3dc1cbd9a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801230485 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.hmac_test_sha_vectors.801230485
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1143179121
Short name T274
Test name
Test status
Simulation time 2605622338 ps
CPU time 33.2 seconds
Started Feb 29 12:58:30 PM PST 24
Finished Feb 29 12:59:03 PM PST 24
Peak memory 199452 kb
Host smart-c5328f08-2c77-45c6-be4d-19222e3e79bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143179121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1143179121
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1635201555
Short name T161
Test name
Test status
Simulation time 10858730 ps
CPU time 0.57 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:28 PM PST 24
Peak memory 193768 kb
Host smart-a23a66ff-d1b9-47cf-9187-2933e5979691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635201555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1635201555
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3918176445
Short name T106
Test name
Test status
Simulation time 4227034431 ps
CPU time 33.46 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:58:48 PM PST 24
Peak memory 215144 kb
Host smart-5f37cbd1-7d34-4143-b7de-a8cddde43587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918176445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3918176445
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.2761138166
Short name T167
Test name
Test status
Simulation time 416830573 ps
CPU time 1.06 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 199236 kb
Host smart-07d97e10-4ae7-48a1-85a3-3f2f99a01599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761138166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.2761138166
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.37654703
Short name T112
Test name
Test status
Simulation time 5052160586 ps
CPU time 72.35 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:29 PM PST 24
Peak memory 199396 kb
Host smart-58827c31-14ab-437b-9736-ffd8e18f4b98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=37654703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.37654703
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1383928345
Short name T175
Test name
Test status
Simulation time 1226152743 ps
CPU time 6.13 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 199324 kb
Host smart-125a9f02-f8ff-46c8-92cd-578c35ebeed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383928345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1383928345
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.466503457
Short name T94
Test name
Test status
Simulation time 3389721307 ps
CPU time 48.38 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:10 PM PST 24
Peak memory 199580 kb
Host smart-d52173c3-5d49-45be-a65b-777c640bc49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466503457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.466503457
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3478985469
Short name T157
Test name
Test status
Simulation time 114322373 ps
CPU time 2.93 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 199340 kb
Host smart-0e4acf5c-3c58-4ffd-81b5-9a4d5e0d20db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478985469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3478985469
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.131119703
Short name T59
Test name
Test status
Simulation time 1005208624803 ps
CPU time 790.6 seconds
Started Feb 29 12:58:31 PM PST 24
Finished Feb 29 01:11:42 PM PST 24
Peak memory 199636 kb
Host smart-22a481ad-4147-4c36-8ca3-f2faa4c15be6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131119703 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.131119703
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2652923173
Short name T340
Test name
Test status
Simulation time 64495596 ps
CPU time 1.15 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 198596 kb
Host smart-62360827-3129-4415-9be0-c9f5d563fc64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652923173 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2652923173
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.530318607
Short name T581
Test name
Test status
Simulation time 182067086989 ps
CPU time 429.03 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 01:05:29 PM PST 24
Peak memory 199428 kb
Host smart-525811e3-309b-4a42-858c-2cba014be18c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530318607 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.hmac_test_sha_vectors.530318607
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2006331304
Short name T545
Test name
Test status
Simulation time 2113726968 ps
CPU time 27.16 seconds
Started Feb 29 12:58:30 PM PST 24
Finished Feb 29 12:58:57 PM PST 24
Peak memory 199392 kb
Host smart-eacf92c0-6306-40a1-a419-d4bae368945e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006331304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2006331304
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3482876936
Short name T502
Test name
Test status
Simulation time 26447175 ps
CPU time 0.62 seconds
Started Feb 29 12:58:12 PM PST 24
Finished Feb 29 12:58:13 PM PST 24
Peak memory 194772 kb
Host smart-675b30ef-1514-4287-85e2-844414ae8d31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482876936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3482876936
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2102506613
Short name T266
Test name
Test status
Simulation time 1759426981 ps
CPU time 14.6 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 215024 kb
Host smart-6b78f4ba-4cff-4413-a0b2-04b1ea958f86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2102506613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2102506613
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.920736471
Short name T467
Test name
Test status
Simulation time 3753781705 ps
CPU time 92.58 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:49 PM PST 24
Peak memory 199564 kb
Host smart-5a93b3c9-2f33-4282-8e41-e096ee10772e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920736471 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.920736471
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.4294125687
Short name T470
Test name
Test status
Simulation time 1307663267 ps
CPU time 62.9 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 12:59:18 PM PST 24
Peak memory 199308 kb
Host smart-48a2a4e4-6ab2-44df-b26e-757a457bf947
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294125687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.4294125687
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3201993347
Short name T239
Test name
Test status
Simulation time 10336256852 ps
CPU time 93.18 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 01:00:01 PM PST 24
Peak memory 199516 kb
Host smart-f16daa1b-08b9-4932-8144-62979ba105b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201993347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3201993347
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2336235347
Short name T308
Test name
Test status
Simulation time 2678823979 ps
CPU time 37.46 seconds
Started Feb 29 12:58:08 PM PST 24
Finished Feb 29 12:58:46 PM PST 24
Peak memory 199612 kb
Host smart-ff8e2cbd-5f88-469c-beee-a586799c302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336235347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2336235347
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3252556160
Short name T15
Test name
Test status
Simulation time 271983759 ps
CPU time 3.23 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:58:36 PM PST 24
Peak memory 199516 kb
Host smart-b8a8ed8b-6e8d-48e0-ad6f-3ddaf20c866c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252556160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3252556160
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.2984921006
Short name T226
Test name
Test status
Simulation time 96946795747 ps
CPU time 1512.03 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 01:23:38 PM PST 24
Peak memory 240108 kb
Host smart-1d739a41-c8c2-49f6-a53a-06d07e6fbe01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984921006 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.2984921006
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3241606205
Short name T135
Test name
Test status
Simulation time 241813427 ps
CPU time 0.9 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 196692 kb
Host smart-36862acd-2478-4405-bb22-15330489e836
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241606205 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3241606205
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.32306467
Short name T253
Test name
Test status
Simulation time 2891574789 ps
CPU time 24.23 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:49 PM PST 24
Peak memory 199444 kb
Host smart-c3819c2e-0c14-4a0b-b903-eb43a06bceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32306467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.32306467
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3061243171
Short name T295
Test name
Test status
Simulation time 17559564 ps
CPU time 0.55 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 193680 kb
Host smart-507925c1-cd0f-415f-b905-d4ba1992517e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061243171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3061243171
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.835981519
Short name T488
Test name
Test status
Simulation time 1126506391 ps
CPU time 37.29 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:59:02 PM PST 24
Peak memory 221868 kb
Host smart-572a9c90-b1f9-47ad-be2c-40b947551725
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=835981519 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.835981519
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2498425877
Short name T208
Test name
Test status
Simulation time 11186869691 ps
CPU time 37.56 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 12:59:01 PM PST 24
Peak memory 199352 kb
Host smart-9c3cf6ae-ae65-4108-8920-094968e4b00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498425877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2498425877
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3125706530
Short name T85
Test name
Test status
Simulation time 2510868554 ps
CPU time 66.43 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:59:28 PM PST 24
Peak memory 199512 kb
Host smart-211aa96e-da7f-4973-8cba-4ee3245cdaef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3125706530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3125706530
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.2646037304
Short name T139
Test name
Test status
Simulation time 17596254891 ps
CPU time 104.31 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 01:00:03 PM PST 24
Peak memory 199400 kb
Host smart-9dfa2335-ca94-4b04-8bc6-2a534906e4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646037304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.2646037304
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3309069150
Short name T276
Test name
Test status
Simulation time 73429237748 ps
CPU time 101.29 seconds
Started Feb 29 12:58:12 PM PST 24
Finished Feb 29 12:59:53 PM PST 24
Peak memory 199448 kb
Host smart-963eada8-5a4f-4018-a187-2d1a45ad9dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309069150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3309069150
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.280760413
Short name T307
Test name
Test status
Simulation time 707237172 ps
CPU time 2.25 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:25 PM PST 24
Peak memory 199456 kb
Host smart-830bc9b3-78d0-46bd-8c4d-e52ae5946995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280760413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.280760413
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3162980773
Short name T177
Test name
Test status
Simulation time 33314353713 ps
CPU time 1202.97 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 01:18:31 PM PST 24
Peak memory 227512 kb
Host smart-af45b012-f5aa-46d1-9d7e-586bc2e01345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162980773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3162980773
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.559082905
Short name T422
Test name
Test status
Simulation time 82861634 ps
CPU time 1.22 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 12:58:25 PM PST 24
Peak memory 198036 kb
Host smart-c7121cfc-27cf-467d-be25-e5c6924bd376
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559082905 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.559082905
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.3655954129
Short name T39
Test name
Test status
Simulation time 45187830546 ps
CPU time 382.03 seconds
Started Feb 29 12:58:14 PM PST 24
Finished Feb 29 01:04:36 PM PST 24
Peak memory 199436 kb
Host smart-2e2c5546-3d26-4bb7-b752-e54e26bfb5ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655954129 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_sha_vectors.3655954129
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.573473734
Short name T14
Test name
Test status
Simulation time 4076535653 ps
CPU time 13.49 seconds
Started Feb 29 12:58:17 PM PST 24
Finished Feb 29 12:58:31 PM PST 24
Peak memory 199516 kb
Host smart-dab35440-c80a-4037-872f-a72e70a9e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573473734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.573473734
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.4029167751
Short name T219
Test name
Test status
Simulation time 56221936 ps
CPU time 0.62 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:23 PM PST 24
Peak memory 193820 kb
Host smart-d61c71a8-35a3-4fba-acf1-e05bb37bb5f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029167751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.4029167751
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1499997311
Short name T509
Test name
Test status
Simulation time 2141137719 ps
CPU time 34.73 seconds
Started Feb 29 12:58:13 PM PST 24
Finished Feb 29 12:58:53 PM PST 24
Peak memory 217816 kb
Host smart-b17511f3-eb64-4b44-a12b-3cf9f7f18d6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1499997311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1499997311
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3579282348
Short name T272
Test name
Test status
Simulation time 344893120 ps
CPU time 1.69 seconds
Started Feb 29 12:58:19 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 199292 kb
Host smart-45805e5c-1e28-442d-835c-168d932ef478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579282348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3579282348
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3100980199
Short name T96
Test name
Test status
Simulation time 1838629592 ps
CPU time 93.35 seconds
Started Feb 29 12:58:30 PM PST 24
Finished Feb 29 01:00:03 PM PST 24
Peak memory 199424 kb
Host smart-b72ddaa9-55fd-4392-8b0e-c0869a4caa36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3100980199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3100980199
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2769659821
Short name T481
Test name
Test status
Simulation time 439515575 ps
CPU time 5.64 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 199412 kb
Host smart-71db97b2-e153-459d-a2f2-9db08896a166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769659821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2769659821
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2311119800
Short name T349
Test name
Test status
Simulation time 166478443 ps
CPU time 7.64 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 199396 kb
Host smart-64225da6-9097-4836-a9e9-d6e7a63c78b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311119800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2311119800
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2160016626
Short name T280
Test name
Test status
Simulation time 685103793 ps
CPU time 3.94 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 12:58:23 PM PST 24
Peak memory 199396 kb
Host smart-da169b21-6fa0-4431-9266-ec6ef01db9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160016626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2160016626
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3088416012
Short name T314
Test name
Test status
Simulation time 65731369512 ps
CPU time 1027.84 seconds
Started Feb 29 12:58:15 PM PST 24
Finished Feb 29 01:15:23 PM PST 24
Peak memory 199452 kb
Host smart-faa6c305-d84c-400f-a9b1-2e42d757fac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088416012 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3088416012
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1567407873
Short name T222
Test name
Test status
Simulation time 97669766 ps
CPU time 0.88 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 197852 kb
Host smart-92b46de5-0560-4011-8f27-883eab3eb5ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567407873 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1567407873
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.2486658289
Short name T132
Test name
Test status
Simulation time 107263652408 ps
CPU time 417 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 01:05:22 PM PST 24
Peak memory 199248 kb
Host smart-958fc8e2-34a0-4500-8c9a-b8a8ca94b33e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486658289 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.hmac_test_sha_vectors.2486658289
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.2658448250
Short name T144
Test name
Test status
Simulation time 91181663458 ps
CPU time 71.17 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:59:36 PM PST 24
Peak memory 199316 kb
Host smart-8bc31c65-1428-4bb8-936e-f33a496733cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658448250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.2658448250
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.486172017
Short name T479
Test name
Test status
Simulation time 25840851 ps
CPU time 0.57 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 193792 kb
Host smart-b356d7d5-113a-4479-9add-f11d814d52e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486172017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.486172017
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.188138535
Short name T185
Test name
Test status
Simulation time 3458524862 ps
CPU time 28.44 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:56 PM PST 24
Peak memory 218784 kb
Host smart-8861aeef-1c77-41d7-b102-be3b76a22ac7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=188138535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.188138535
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2653817308
Short name T140
Test name
Test status
Simulation time 537907628 ps
CPU time 23.39 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 199360 kb
Host smart-f3847643-d3b8-4adf-8eeb-b2fa92e5886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653817308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2653817308
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1007361280
Short name T456
Test name
Test status
Simulation time 12013429984 ps
CPU time 150.1 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 01:00:51 PM PST 24
Peak memory 199360 kb
Host smart-05ec2e9b-5d05-4616-8076-02c14c736fa6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1007361280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1007361280
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.73845320
Short name T149
Test name
Test status
Simulation time 2840854475 ps
CPU time 41.25 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:59:06 PM PST 24
Peak memory 199472 kb
Host smart-2f572aca-4eec-4ffa-b9a6-402b414834a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73845320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.73845320
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1588841363
Short name T464
Test name
Test status
Simulation time 20682510912 ps
CPU time 64.6 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:59:30 PM PST 24
Peak memory 199448 kb
Host smart-8c608343-e1da-4af6-ad7b-791b0311ce10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588841363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1588841363
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.476904009
Short name T499
Test name
Test status
Simulation time 215341461 ps
CPU time 1.44 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:58:26 PM PST 24
Peak memory 199064 kb
Host smart-7ca81866-13df-425a-b571-f6580d9f30e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476904009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.476904009
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2157499769
Short name T594
Test name
Test status
Simulation time 71648972385 ps
CPU time 1210.74 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 01:18:29 PM PST 24
Peak memory 225848 kb
Host smart-b109f91d-ea0f-43ed-93f6-958fd8eebde0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157499769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2157499769
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.4265246242
Short name T215
Test name
Test status
Simulation time 53417005 ps
CPU time 0.9 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 12:58:33 PM PST 24
Peak memory 196896 kb
Host smart-82e812cc-95ae-4751-ab79-04894466c742
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265246242 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.4265246242
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.2669381794
Short name T475
Test name
Test status
Simulation time 140161855454 ps
CPU time 459.79 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 01:06:01 PM PST 24
Peak memory 199468 kb
Host smart-fc7101fa-3681-4949-a432-f1277fa865bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669381794 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.hmac_test_sha_vectors.2669381794
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.733485980
Short name T137
Test name
Test status
Simulation time 3358887343 ps
CPU time 40.52 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:59:08 PM PST 24
Peak memory 199532 kb
Host smart-6b5f4b3f-490a-43a4-8aeb-48ab2f578d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733485980 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.733485980
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4235483577
Short name T268
Test name
Test status
Simulation time 13250913 ps
CPU time 0.56 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:58:25 PM PST 24
Peak memory 193804 kb
Host smart-c76fb55b-0d9a-40e1-8098-3e63f59322e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235483577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4235483577
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.4231620350
Short name T445
Test name
Test status
Simulation time 389734825 ps
CPU time 7.71 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 12:58:49 PM PST 24
Peak memory 199428 kb
Host smart-6f0aa825-3671-43de-9d62-8b3c49057076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231620350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.4231620350
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.4045227689
Short name T318
Test name
Test status
Simulation time 897581057 ps
CPU time 12.09 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:46 PM PST 24
Peak memory 199424 kb
Host smart-1ad7f9b3-a893-40fa-972d-4f75359fc646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045227689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.4045227689
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3187306817
Short name T390
Test name
Test status
Simulation time 359794284 ps
CPU time 19.47 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:41 PM PST 24
Peak memory 199432 kb
Host smart-b8cd3727-20f2-4fd3-bfaf-611c13988490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187306817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3187306817
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.2425079642
Short name T6
Test name
Test status
Simulation time 41669467860 ps
CPU time 179.1 seconds
Started Feb 29 12:58:23 PM PST 24
Finished Feb 29 01:01:23 PM PST 24
Peak memory 199656 kb
Host smart-60139de2-c85c-4787-941b-8f60ae4b2173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425079642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.2425079642
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1825324116
Short name T192
Test name
Test status
Simulation time 991972912 ps
CPU time 11.02 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199452 kb
Host smart-1c970d02-b509-4329-9021-660ab352e006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825324116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1825324116
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.3837316983
Short name T440
Test name
Test status
Simulation time 147537442 ps
CPU time 1.73 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 199392 kb
Host smart-4b9706c1-a075-4304-ba6f-4ac37b1e153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837316983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.3837316983
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.2738985551
Short name T552
Test name
Test status
Simulation time 100492129505 ps
CPU time 306.14 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 01:03:31 PM PST 24
Peak memory 234728 kb
Host smart-7c9f19ab-ea61-4bae-9b04-933cf6b855e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738985551 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.2738985551
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.88719774
Short name T299
Test name
Test status
Simulation time 142814577 ps
CPU time 0.89 seconds
Started Feb 29 12:58:43 PM PST 24
Finished Feb 29 12:58:44 PM PST 24
Peak memory 196796 kb
Host smart-42edc5d2-a746-474f-b6fd-3b045c2c3df7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88719774 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_hmac_vectors.88719774
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.228016114
Short name T433
Test name
Test status
Simulation time 69895578167 ps
CPU time 419.57 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 01:05:25 PM PST 24
Peak memory 199420 kb
Host smart-1bcd6e2e-698c-420c-90ff-c9ff0e147856
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228016114 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.hmac_test_sha_vectors.228016114
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.715600584
Short name T448
Test name
Test status
Simulation time 5751848055 ps
CPU time 30.11 seconds
Started Feb 29 12:58:13 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 199492 kb
Host smart-3feb8803-c0c8-464c-a410-083d3828b65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715600584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.715600584
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2071573178
Short name T186
Test name
Test status
Simulation time 95335406 ps
CPU time 0.55 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 12:58:22 PM PST 24
Peak memory 193760 kb
Host smart-104460cc-15eb-4c13-aec5-5f7817e83813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071573178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2071573178
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4280043460
Short name T330
Test name
Test status
Simulation time 3478634533 ps
CPU time 27.23 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 12:58:46 PM PST 24
Peak memory 207628 kb
Host smart-749115b0-608a-4945-b545-a9b99fbd6db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4280043460 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4280043460
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.1191934736
Short name T216
Test name
Test status
Simulation time 318396146 ps
CPU time 6.96 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 199412 kb
Host smart-05766ae1-545c-48de-95ef-d7b6664d1f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191934736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.1191934736
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1088647521
Short name T333
Test name
Test status
Simulation time 1966326347 ps
CPU time 114.12 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 01:00:26 PM PST 24
Peak memory 199416 kb
Host smart-0d52f06a-c649-4a48-9b57-2e1c5b51508c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088647521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1088647521
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.971451535
Short name T352
Test name
Test status
Simulation time 8174109207 ps
CPU time 103.01 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 01:00:10 PM PST 24
Peak memory 199468 kb
Host smart-96bb8155-e9fc-4786-bb32-5f094db0c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971451535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.971451535
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1130499968
Short name T455
Test name
Test status
Simulation time 14855029566 ps
CPU time 54.24 seconds
Started Feb 29 12:59:50 PM PST 24
Finished Feb 29 01:00:47 PM PST 24
Peak memory 198008 kb
Host smart-4e2a3765-8250-4e57-93df-db32db205e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130499968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1130499968
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.842112975
Short name T492
Test name
Test status
Simulation time 625993952 ps
CPU time 1.89 seconds
Started Feb 29 12:58:31 PM PST 24
Finished Feb 29 12:58:33 PM PST 24
Peak memory 199424 kb
Host smart-70ff65e0-bb62-477a-bbe3-a52ad30fe860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842112975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.842112975
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3556575086
Short name T62
Test name
Test status
Simulation time 195109315971 ps
CPU time 1167.69 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 01:18:04 PM PST 24
Peak memory 229336 kb
Host smart-8e361d17-362e-4e72-a4a6-5682905b6d57
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556575086 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3556575086
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.3703327988
Short name T199
Test name
Test status
Simulation time 141324750 ps
CPU time 0.91 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:35 PM PST 24
Peak memory 197092 kb
Host smart-307a8901-7543-4982-a99d-a65699ba0d80
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703327988 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.3703327988
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2551217719
Short name T298
Test name
Test status
Simulation time 28163870030 ps
CPU time 368.26 seconds
Started Feb 29 12:58:20 PM PST 24
Finished Feb 29 01:04:29 PM PST 24
Peak memory 199400 kb
Host smart-e57d4543-84df-4e9b-a224-170c5bd96332
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551217719 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.hmac_test_sha_vectors.2551217719
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.1025603706
Short name T447
Test name
Test status
Simulation time 29006172750 ps
CPU time 72.33 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:59:45 PM PST 24
Peak memory 199424 kb
Host smart-bc6daf83-c5b1-415f-a95a-3adfc93aee76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025603706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.1025603706
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.3407239326
Short name T544
Test name
Test status
Simulation time 12862502 ps
CPU time 0.54 seconds
Started Feb 29 12:57:28 PM PST 24
Finished Feb 29 12:57:29 PM PST 24
Peak memory 193900 kb
Host smart-1ef9280f-56eb-4221-9654-56727e1eb96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407239326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.3407239326
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4178911275
Short name T207
Test name
Test status
Simulation time 1581344896 ps
CPU time 21.07 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:57:52 PM PST 24
Peak memory 199388 kb
Host smart-46f78e57-f0cc-479c-9a40-0eb8002544ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178911275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4178911275
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2578111597
Short name T378
Test name
Test status
Simulation time 877460814 ps
CPU time 48.34 seconds
Started Feb 29 12:57:26 PM PST 24
Finished Feb 29 12:58:15 PM PST 24
Peak memory 199448 kb
Host smart-8eb8eae9-401d-4188-8b86-f6278d2c218a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578111597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2578111597
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1799851321
Short name T244
Test name
Test status
Simulation time 1800503925 ps
CPU time 91.25 seconds
Started Feb 29 12:57:27 PM PST 24
Finished Feb 29 12:58:58 PM PST 24
Peak memory 199304 kb
Host smart-fcf549b9-3037-44ad-93d6-1cff1522deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799851321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1799851321
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.2638823854
Short name T296
Test name
Test status
Simulation time 23067730233 ps
CPU time 37.69 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:58:09 PM PST 24
Peak memory 199372 kb
Host smart-816037f4-15e2-4006-aedf-ab5f0a17a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638823854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.2638823854
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.147672687
Short name T22
Test name
Test status
Simulation time 163354105 ps
CPU time 0.81 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:57:37 PM PST 24
Peak memory 216580 kb
Host smart-05b5da16-2133-4e35-91d3-3444f9b541b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147672687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.147672687
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2839876861
Short name T579
Test name
Test status
Simulation time 686936906 ps
CPU time 4.06 seconds
Started Feb 29 12:57:34 PM PST 24
Finished Feb 29 12:57:39 PM PST 24
Peak memory 199332 kb
Host smart-63f3a0f1-da86-4ead-a7a6-0c5c6aa4e144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839876861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2839876861
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2836942694
Short name T86
Test name
Test status
Simulation time 119134058956 ps
CPU time 117.55 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:59:42 PM PST 24
Peak memory 233860 kb
Host smart-a9e1de5d-2953-4dfa-b942-ba8a7f4fb61f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836942694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2836942694
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.2870130276
Short name T29
Test name
Test status
Simulation time 104832869 ps
CPU time 0.89 seconds
Started Feb 29 12:57:28 PM PST 24
Finished Feb 29 12:57:29 PM PST 24
Peak memory 196792 kb
Host smart-d57629cc-a946-4eae-8e95-3de72972f7c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870130276 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.2870130276
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.4152897380
Short name T143
Test name
Test status
Simulation time 92059098101 ps
CPU time 525.74 seconds
Started Feb 29 12:57:17 PM PST 24
Finished Feb 29 01:06:03 PM PST 24
Peak memory 199460 kb
Host smart-fc8ffdee-daad-415c-a700-5f17df5b7bac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152897380 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_sha_vectors.4152897380
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1448053817
Short name T402
Test name
Test status
Simulation time 3811359065 ps
CPU time 67.09 seconds
Started Feb 29 12:57:28 PM PST 24
Finished Feb 29 12:58:36 PM PST 24
Peak memory 199372 kb
Host smart-9dd1063d-a08d-4ac9-93d7-e5d9f914cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448053817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1448053817
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.17285029
Short name T339
Test name
Test status
Simulation time 42016460 ps
CPU time 0.56 seconds
Started Feb 29 12:58:41 PM PST 24
Finished Feb 29 12:58:42 PM PST 24
Peak memory 193792 kb
Host smart-89abf8a9-f0fe-4b1a-a532-0eefc968901e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17285029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.17285029
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2720450115
Short name T520
Test name
Test status
Simulation time 1583520888 ps
CPU time 62.36 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:59:41 PM PST 24
Peak memory 231160 kb
Host smart-878d1efd-5dde-40e0-a21a-4543be8d0d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720450115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2720450115
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.728781397
Short name T262
Test name
Test status
Simulation time 2850147174 ps
CPU time 43.29 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:59:05 PM PST 24
Peak memory 199476 kb
Host smart-4c1f0a32-43cb-44e1-970a-33e7a0b0e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728781397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.728781397
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1342115525
Short name T392
Test name
Test status
Simulation time 6405725812 ps
CPU time 52.22 seconds
Started Feb 29 12:58:31 PM PST 24
Finished Feb 29 12:59:24 PM PST 24
Peak memory 199504 kb
Host smart-6e1615e2-4242-4948-8733-1e542411f854
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342115525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1342115525
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.3686849528
Short name T554
Test name
Test status
Simulation time 5088941967 ps
CPU time 82.57 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:59:45 PM PST 24
Peak memory 199464 kb
Host smart-8e3f2aa0-4cb9-4368-a4b1-3f3e913d2883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686849528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.3686849528
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2758872711
Short name T446
Test name
Test status
Simulation time 1825511231 ps
CPU time 24.14 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:59:00 PM PST 24
Peak memory 199484 kb
Host smart-a8cf547e-e27f-4c03-81d7-4633ea7815b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758872711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2758872711
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1977144108
Short name T309
Test name
Test status
Simulation time 249946765 ps
CPU time 2.61 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199192 kb
Host smart-63d6bbba-d749-440e-a5e1-aeeeec899ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977144108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1977144108
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3506480310
Short name T50
Test name
Test status
Simulation time 555754685512 ps
CPU time 1399.61 seconds
Started Feb 29 12:59:59 PM PST 24
Finished Feb 29 01:23:19 PM PST 24
Peak memory 224684 kb
Host smart-a4a345e1-0728-4a25-a954-0bdf4efff0ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506480310 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3506480310
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.111247756
Short name T495
Test name
Test status
Simulation time 60048185 ps
CPU time 1.21 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 12:58:34 PM PST 24
Peak memory 198704 kb
Host smart-a1c5f9f6-d546-4302-8c48-f9eb6c6dbe5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111247756 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.111247756
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.550997825
Short name T362
Test name
Test status
Simulation time 57284128201 ps
CPU time 436.66 seconds
Started Feb 29 12:58:21 PM PST 24
Finished Feb 29 01:05:38 PM PST 24
Peak memory 199616 kb
Host smart-00d5f36f-a875-4088-974d-43c9925ef481
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550997825 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.hmac_test_sha_vectors.550997825
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2701529943
Short name T256
Test name
Test status
Simulation time 1082388294 ps
CPU time 21.23 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:47 PM PST 24
Peak memory 199384 kb
Host smart-e81e5f86-9c23-4ef4-a872-e73adae1fa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701529943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2701529943
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2965449017
Short name T547
Test name
Test status
Simulation time 13573677 ps
CPU time 0.54 seconds
Started Feb 29 12:58:13 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 193616 kb
Host smart-ebcd9957-27ed-409f-a6a8-ac5144cc7c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965449017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2965449017
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2143066283
Short name T469
Test name
Test status
Simulation time 2110142400 ps
CPU time 14.27 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 12:58:47 PM PST 24
Peak memory 207516 kb
Host smart-4552ac26-2fe6-41bb-bf4c-146eb525ee4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2143066283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2143066283
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1212924794
Short name T31
Test name
Test status
Simulation time 3771188428 ps
CPU time 26.63 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:52 PM PST 24
Peak memory 199500 kb
Host smart-6a5322f4-a7f2-46a6-a3c7-9510621a16b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212924794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1212924794
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.3166196027
Short name T338
Test name
Test status
Simulation time 25382411 ps
CPU time 0.61 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:58:30 PM PST 24
Peak memory 194952 kb
Host smart-a7b92cf2-40e4-4267-a6e1-0c2573e0c7a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166196027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.3166196027
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.1463698870
Short name T225
Test name
Test status
Simulation time 10374190189 ps
CPU time 178.26 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 01:01:31 PM PST 24
Peak memory 199568 kb
Host smart-68f44eea-fafd-427a-ad47-231982e86754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463698870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.1463698870
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1982235394
Short name T516
Test name
Test status
Simulation time 6264925721 ps
CPU time 31.42 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:54 PM PST 24
Peak memory 199400 kb
Host smart-14f7b693-8f66-4754-b25b-0dab5c2d3b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982235394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1982235394
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.24302576
Short name T493
Test name
Test status
Simulation time 565609806 ps
CPU time 3.67 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 199268 kb
Host smart-3bb6fd9c-6857-401c-9994-06cb2124cab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24302576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.24302576
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.3679144983
Short name T503
Test name
Test status
Simulation time 65129293 ps
CPU time 1.2 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:29 PM PST 24
Peak memory 198372 kb
Host smart-c740f699-76cb-4bf1-b467-fb7185b7724b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679144983 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.3679144983
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.383211486
Short name T366
Test name
Test status
Simulation time 53007245458 ps
CPU time 423.58 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 01:05:44 PM PST 24
Peak memory 199288 kb
Host smart-7dcef383-21b5-48eb-b248-b2114e3642df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383211486 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.hmac_test_sha_vectors.383211486
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1158449498
Short name T254
Test name
Test status
Simulation time 5033786539 ps
CPU time 55.12 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:59:29 PM PST 24
Peak memory 199488 kb
Host smart-f5410d6a-10bd-4c74-828f-8ecf44aa68fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158449498 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1158449498
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2983694962
Short name T511
Test name
Test status
Simulation time 46408363 ps
CPU time 0.59 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:36 PM PST 24
Peak memory 193980 kb
Host smart-d76f0961-78a2-487e-af43-16d8b85e3a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983694962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2983694962
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2542705735
Short name T443
Test name
Test status
Simulation time 2616737572 ps
CPU time 21.2 seconds
Started Feb 29 12:59:59 PM PST 24
Finished Feb 29 01:00:21 PM PST 24
Peak memory 204236 kb
Host smart-d8eb6595-4cb7-4b29-9c16-fb9bc2ab06a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2542705735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2542705735
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2212121808
Short name T317
Test name
Test status
Simulation time 7218039085 ps
CPU time 29.63 seconds
Started Feb 29 12:58:27 PM PST 24
Finished Feb 29 12:58:57 PM PST 24
Peak memory 199316 kb
Host smart-f1364202-41f5-42c8-bff5-831ad412c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212121808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2212121808
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1375437705
Short name T375
Test name
Test status
Simulation time 5416123187 ps
CPU time 29.35 seconds
Started Feb 29 12:59:50 PM PST 24
Finished Feb 29 01:00:22 PM PST 24
Peak memory 197980 kb
Host smart-1e5e03a7-4f03-4775-ac27-6ae3809b92dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1375437705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1375437705
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.1462735523
Short name T30
Test name
Test status
Simulation time 8571264519 ps
CPU time 105.34 seconds
Started Feb 29 12:59:59 PM PST 24
Finished Feb 29 01:01:44 PM PST 24
Peak memory 199088 kb
Host smart-779c831d-fa3b-4d3b-b35f-eb8e22baf421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462735523 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.1462735523
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.4122859420
Short name T523
Test name
Test status
Simulation time 1267003471 ps
CPU time 17.18 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:58:57 PM PST 24
Peak memory 199392 kb
Host smart-54bef4f6-2cbd-4d32-8e29-ca788a323af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122859420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.4122859420
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.80486840
Short name T426
Test name
Test status
Simulation time 113655869 ps
CPU time 3.02 seconds
Started Feb 29 12:59:58 PM PST 24
Finished Feb 29 01:00:01 PM PST 24
Peak memory 199000 kb
Host smart-ad179a82-2e19-4ea6-a302-35423153140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80486840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.80486840
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.2973025400
Short name T575
Test name
Test status
Simulation time 49778659 ps
CPU time 0.99 seconds
Started Feb 29 12:58:18 PM PST 24
Finished Feb 29 12:58:20 PM PST 24
Peak memory 197408 kb
Host smart-1c7adfee-3243-4c4b-9abc-cf47452f77f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973025400 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.2973025400
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2489493053
Short name T452
Test name
Test status
Simulation time 134079596974 ps
CPU time 471.78 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 01:06:20 PM PST 24
Peak memory 199380 kb
Host smart-4b804799-a90c-478c-adb1-70d7d231b953
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489493053 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.hmac_test_sha_vectors.2489493053
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.389101917
Short name T146
Test name
Test status
Simulation time 695742351 ps
CPU time 8.07 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 199288 kb
Host smart-afd2c29f-07e5-48f7-a13c-cd871375f839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389101917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.389101917
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1584692593
Short name T250
Test name
Test status
Simulation time 15049743 ps
CPU time 0.56 seconds
Started Feb 29 12:58:16 PM PST 24
Finished Feb 29 12:58:17 PM PST 24
Peak memory 193988 kb
Host smart-7e0bc359-5c6c-4a14-8fcd-5b37663c7e33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584692593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1584692593
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3687426387
Short name T259
Test name
Test status
Simulation time 1267138585 ps
CPU time 11.53 seconds
Started Feb 29 12:58:22 PM PST 24
Finished Feb 29 12:58:35 PM PST 24
Peak memory 215160 kb
Host smart-68146cc3-da5f-4a08-b6b3-2675fef53844
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3687426387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3687426387
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3242166231
Short name T477
Test name
Test status
Simulation time 11327581656 ps
CPU time 20.18 seconds
Started Feb 29 12:58:25 PM PST 24
Finished Feb 29 12:58:46 PM PST 24
Peak memory 199372 kb
Host smart-1425ad5e-11e9-4259-a00f-f7c4cd508850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242166231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3242166231
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.1616302061
Short name T99
Test name
Test status
Simulation time 6768286999 ps
CPU time 82.3 seconds
Started Feb 29 01:00:00 PM PST 24
Finished Feb 29 01:01:22 PM PST 24
Peak memory 199104 kb
Host smart-33ce06aa-2b5b-4657-b409-bc1749b2f643
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1616302061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.1616302061
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.3811316835
Short name T27
Test name
Test status
Simulation time 7957723603 ps
CPU time 25.05 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:59 PM PST 24
Peak memory 199488 kb
Host smart-a0b99ac4-023b-462f-b479-3c597c77fa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811316835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.3811316835
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.2483409000
Short name T522
Test name
Test status
Simulation time 950576045 ps
CPU time 13.26 seconds
Started Feb 29 12:59:58 PM PST 24
Finished Feb 29 01:00:12 PM PST 24
Peak memory 199028 kb
Host smart-9581b36a-d515-404d-8fd7-e6481b60bb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483409000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.2483409000
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.4268329634
Short name T501
Test name
Test status
Simulation time 702883904 ps
CPU time 4.03 seconds
Started Feb 29 12:59:59 PM PST 24
Finished Feb 29 01:00:04 PM PST 24
Peak memory 199028 kb
Host smart-1a17f648-d174-4d4e-bd39-c3f39ffca5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268329634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.4268329634
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.953745141
Short name T528
Test name
Test status
Simulation time 223393515259 ps
CPU time 1416.93 seconds
Started Feb 29 12:59:58 PM PST 24
Finished Feb 29 01:23:35 PM PST 24
Peak memory 226764 kb
Host smart-1acdffb4-9f83-4159-8b3b-06395160e9f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953745141 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.953745141
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.4131276587
Short name T133
Test name
Test status
Simulation time 126222260 ps
CPU time 1.21 seconds
Started Feb 29 12:58:24 PM PST 24
Finished Feb 29 12:58:26 PM PST 24
Peak memory 197920 kb
Host smart-56a67465-383e-4cee-a90a-ad90d0f6d583
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131276587 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.4131276587
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.1475504455
Short name T558
Test name
Test status
Simulation time 56157396531 ps
CPU time 428.12 seconds
Started Feb 29 12:59:58 PM PST 24
Finished Feb 29 01:07:06 PM PST 24
Peak memory 199060 kb
Host smart-cfe733d2-e103-4ce1-81e9-a3e924877610
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475504455 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.hmac_test_sha_vectors.1475504455
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3880223066
Short name T548
Test name
Test status
Simulation time 3334978083 ps
CPU time 72.72 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:59:41 PM PST 24
Peak memory 199464 kb
Host smart-639a658e-7472-4bd6-89ca-c924b8194832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880223066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3880223066
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1217112869
Short name T169
Test name
Test status
Simulation time 22462271 ps
CPU time 0.57 seconds
Started Feb 29 12:58:39 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 193800 kb
Host smart-ec4898b9-0309-4eb5-91de-b8148fab380f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217112869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1217112869
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.3632076395
Short name T419
Test name
Test status
Simulation time 3562563481 ps
CPU time 26.89 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:58:56 PM PST 24
Peak memory 217120 kb
Host smart-d0cc46a0-e271-4611-b215-a524559eb175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632076395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.3632076395
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3348681034
Short name T582
Test name
Test status
Simulation time 6114443795 ps
CPU time 43.44 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:59:23 PM PST 24
Peak memory 199476 kb
Host smart-0df19307-609b-4921-bfb1-aa9354aa9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348681034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3348681034
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.987735018
Short name T258
Test name
Test status
Simulation time 1453198494 ps
CPU time 76.95 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:59:53 PM PST 24
Peak memory 199516 kb
Host smart-7a2116c4-53a8-4e87-9dbc-a67f74872adc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=987735018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.987735018
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1598965425
Short name T147
Test name
Test status
Simulation time 3715298208 ps
CPU time 16.25 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:58:49 PM PST 24
Peak memory 199428 kb
Host smart-e0844298-3113-48d5-b303-482a380425d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598965425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1598965425
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.783961663
Short name T3
Test name
Test status
Simulation time 1587928023 ps
CPU time 80.95 seconds
Started Feb 29 12:58:37 PM PST 24
Finished Feb 29 12:59:59 PM PST 24
Peak memory 199444 kb
Host smart-2249660b-5081-4e2e-9af8-2da527a41bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783961663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.783961663
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.2166613910
Short name T291
Test name
Test status
Simulation time 19316482 ps
CPU time 0.67 seconds
Started Feb 29 12:58:37 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 196020 kb
Host smart-5cf2fa12-5cec-498a-8f98-a3f7ffdcff5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166613910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.2166613910
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3669481699
Short name T56
Test name
Test status
Simulation time 453721475212 ps
CPU time 1503.21 seconds
Started Feb 29 12:58:45 PM PST 24
Finished Feb 29 01:23:49 PM PST 24
Peak memory 227752 kb
Host smart-c27f0356-cc91-47fb-a085-57b19177c380
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669481699 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3669481699
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.2658681787
Short name T300
Test name
Test status
Simulation time 211486908 ps
CPU time 1.14 seconds
Started Feb 29 12:58:28 PM PST 24
Finished Feb 29 12:58:29 PM PST 24
Peak memory 198332 kb
Host smart-df5afd4e-dcd5-4b87-928e-460b0356f3b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658681787 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.2658681787
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.96700708
Short name T150
Test name
Test status
Simulation time 45160349125 ps
CPU time 429.63 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 01:05:46 PM PST 24
Peak memory 199404 kb
Host smart-d614bb04-753a-43f2-bfd4-6dc846af3a26
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96700708 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 44.hmac_test_sha_vectors.96700708
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.4191415959
Short name T595
Test name
Test status
Simulation time 15549758992 ps
CPU time 60.81 seconds
Started Feb 29 12:58:47 PM PST 24
Finished Feb 29 12:59:48 PM PST 24
Peak memory 199460 kb
Host smart-afd63272-e1f7-4f57-98d2-4950c202bfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191415959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.4191415959
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2425986224
Short name T148
Test name
Test status
Simulation time 11926154 ps
CPU time 0.57 seconds
Started Feb 29 12:58:47 PM PST 24
Finished Feb 29 12:58:48 PM PST 24
Peak memory 193792 kb
Host smart-a2f28f16-af8f-4f02-bfb0-4ee15fb8a2c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425986224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2425986224
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.3235873802
Short name T313
Test name
Test status
Simulation time 669487842 ps
CPU time 25.33 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 12:59:02 PM PST 24
Peak memory 222252 kb
Host smart-42446c52-a83f-4203-b570-9e8afd0d577d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3235873802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.3235873802
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1752083580
Short name T555
Test name
Test status
Simulation time 514286860 ps
CPU time 12.65 seconds
Started Feb 29 12:58:43 PM PST 24
Finished Feb 29 12:58:56 PM PST 24
Peak memory 199408 kb
Host smart-f5535d3a-7f60-4ce7-991a-8afc54f45ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752083580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1752083580
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.1218235323
Short name T101
Test name
Test status
Simulation time 1297064262 ps
CPU time 8.7 seconds
Started Feb 29 12:58:43 PM PST 24
Finished Feb 29 12:58:52 PM PST 24
Peak memory 199456 kb
Host smart-47c9227c-7d16-42aa-8a00-ee51b676a5a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218235323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.1218235323
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.2895956499
Short name T278
Test name
Test status
Simulation time 36074533653 ps
CPU time 145.16 seconds
Started Feb 29 12:58:39 PM PST 24
Finished Feb 29 01:01:05 PM PST 24
Peak memory 199564 kb
Host smart-80b70829-ec6b-4eea-8ec9-e306a55a24fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895956499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.2895956499
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1132124845
Short name T44
Test name
Test status
Simulation time 14406989532 ps
CPU time 110.7 seconds
Started Feb 29 12:58:26 PM PST 24
Finished Feb 29 01:00:17 PM PST 24
Peak memory 199672 kb
Host smart-e80e22eb-728c-472f-8dd5-4b7924e868c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132124845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1132124845
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2441037779
Short name T165
Test name
Test status
Simulation time 144358502 ps
CPU time 1.38 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:58:35 PM PST 24
Peak memory 199408 kb
Host smart-6ab46abf-ff62-4bc3-8194-ca92141093e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441037779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2441037779
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2122334561
Short name T109
Test name
Test status
Simulation time 63158174012 ps
CPU time 817.84 seconds
Started Feb 29 12:58:37 PM PST 24
Finished Feb 29 01:12:16 PM PST 24
Peak memory 199544 kb
Host smart-f0e1c7d1-3ed6-41fb-b0c7-869c5504826c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122334561 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2122334561
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.217348050
Short name T288
Test name
Test status
Simulation time 203601816 ps
CPU time 1.15 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 198376 kb
Host smart-f9e0add7-1bac-4f16-8a3e-f9308679dcaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217348050 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.hmac_test_hmac_vectors.217348050
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.905715809
Short name T232
Test name
Test status
Simulation time 8192597573 ps
CPU time 386.69 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 01:05:00 PM PST 24
Peak memory 199440 kb
Host smart-42183a04-ff1b-4d28-a314-eecf15a37d88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905715809 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.hmac_test_sha_vectors.905715809
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2874801539
Short name T285
Test name
Test status
Simulation time 683342844 ps
CPU time 23.74 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:58:53 PM PST 24
Peak memory 199432 kb
Host smart-0dd95f5d-5616-4c4c-8695-c91e2da38407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874801539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2874801539
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2217738594
Short name T344
Test name
Test status
Simulation time 22214933 ps
CPU time 0.57 seconds
Started Feb 29 12:58:37 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 194836 kb
Host smart-8549ebcf-7ee4-4d5a-aed1-2aae415436f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217738594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2217738594
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1609833275
Short name T217
Test name
Test status
Simulation time 3893818122 ps
CPU time 46.58 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:59:20 PM PST 24
Peak memory 217744 kb
Host smart-20b37782-1c8d-48d6-ad79-a0fc78b39341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1609833275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1609833275
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.3453184143
Short name T423
Test name
Test status
Simulation time 1159132678 ps
CPU time 54.32 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 12:59:28 PM PST 24
Peak memory 199484 kb
Host smart-323cf0f7-78b2-4c19-a3a9-e695f9f4e959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453184143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.3453184143
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.4071432393
Short name T500
Test name
Test status
Simulation time 10898892333 ps
CPU time 112.37 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 01:00:27 PM PST 24
Peak memory 199480 kb
Host smart-5f359b32-7270-4c59-89ea-015d032385fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4071432393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.4071432393
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.1574332852
Short name T373
Test name
Test status
Simulation time 27996872480 ps
CPU time 105.75 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 01:00:21 PM PST 24
Peak memory 199464 kb
Host smart-0a768d11-6505-44de-81af-4bc6b14991b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574332852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.1574332852
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3005832972
Short name T441
Test name
Test status
Simulation time 166480006 ps
CPU time 8.66 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 199472 kb
Host smart-16f5a5a2-f957-4aca-ad53-c0704ed73d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005832972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3005832972
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3357444173
Short name T136
Test name
Test status
Simulation time 177765068 ps
CPU time 2.18 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 199388 kb
Host smart-c7cfb899-d189-4c39-ad44-235689a911f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357444173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3357444173
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.3243125346
Short name T60
Test name
Test status
Simulation time 77624806273 ps
CPU time 285.02 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 01:03:19 PM PST 24
Peak memory 232276 kb
Host smart-46b6e87b-49c9-45ae-a8a9-d96d02cfa66d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243125346 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.3243125346
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.152417829
Short name T130
Test name
Test status
Simulation time 72290084 ps
CPU time 0.92 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:58:35 PM PST 24
Peak memory 196720 kb
Host smart-21678eaf-4557-4ca5-a877-6563a3e53d13
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152417829 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_hmac_vectors.152417829
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2607904349
Short name T281
Test name
Test status
Simulation time 34869860013 ps
CPU time 391.72 seconds
Started Feb 29 12:58:33 PM PST 24
Finished Feb 29 01:05:05 PM PST 24
Peak memory 199480 kb
Host smart-ccae5fc1-9f9d-41ef-b4ad-dc496b83321a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607904349 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.hmac_test_sha_vectors.2607904349
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2173947694
Short name T365
Test name
Test status
Simulation time 7683959918 ps
CPU time 68.16 seconds
Started Feb 29 12:58:43 PM PST 24
Finished Feb 29 12:59:51 PM PST 24
Peak memory 199532 kb
Host smart-a0fefde4-b832-4e98-a990-427c154eea55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173947694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2173947694
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.665953189
Short name T463
Test name
Test status
Simulation time 40037382 ps
CPU time 0.59 seconds
Started Feb 29 12:58:45 PM PST 24
Finished Feb 29 12:58:46 PM PST 24
Peak memory 193768 kb
Host smart-c35ffb8a-8e90-43a4-8fa6-13b8a415c5c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665953189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.665953189
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.659884123
Short name T430
Test name
Test status
Simulation time 2342461243 ps
CPU time 47.41 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 12:59:28 PM PST 24
Peak memory 234304 kb
Host smart-4fd5a2de-e4b6-4fee-b0ba-3203905c5e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=659884123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.659884123
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1373587819
Short name T550
Test name
Test status
Simulation time 3809017515 ps
CPU time 48.11 seconds
Started Feb 29 12:58:49 PM PST 24
Finished Feb 29 12:59:37 PM PST 24
Peak memory 199472 kb
Host smart-a9ec0f3a-f33c-4775-a3d8-1c635e2befa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373587819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1373587819
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.4220245804
Short name T23
Test name
Test status
Simulation time 2200649085 ps
CPU time 84.12 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 01:00:01 PM PST 24
Peak memory 199500 kb
Host smart-7a2c49ef-f7c1-4d9b-9fcc-8367fa5a62f0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4220245804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.4220245804
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.429115594
Short name T512
Test name
Test status
Simulation time 7370011532 ps
CPU time 102.24 seconds
Started Feb 29 12:58:40 PM PST 24
Finished Feb 29 01:00:23 PM PST 24
Peak memory 199580 kb
Host smart-627b7c2f-d5ce-4a36-8c9c-1d4437227a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429115594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.429115594
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2021259046
Short name T387
Test name
Test status
Simulation time 9805727950 ps
CPU time 29.87 seconds
Started Feb 29 12:58:31 PM PST 24
Finished Feb 29 12:59:02 PM PST 24
Peak memory 199420 kb
Host smart-8f222e02-b080-44b3-86e5-d917ba7e76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021259046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2021259046
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2780682600
Short name T195
Test name
Test status
Simulation time 1037247708 ps
CPU time 3.57 seconds
Started Feb 29 12:58:29 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199476 kb
Host smart-064a2955-0930-4804-8661-13a7eb6ea76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780682600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2780682600
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2067741748
Short name T100
Test name
Test status
Simulation time 242466173535 ps
CPU time 1144.5 seconds
Started Feb 29 12:58:45 PM PST 24
Finished Feb 29 01:17:50 PM PST 24
Peak memory 199492 kb
Host smart-1186c3e1-91ff-46da-b2c4-56264d723895
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067741748 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2067741748
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2747127014
Short name T320
Test name
Test status
Simulation time 246251183 ps
CPU time 1.19 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 198092 kb
Host smart-abf530e3-abfb-4ac3-976a-793b6cd10f94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747127014 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2747127014
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.2982806869
Short name T246
Test name
Test status
Simulation time 5217595010 ps
CPU time 88.96 seconds
Started Feb 29 12:58:32 PM PST 24
Finished Feb 29 01:00:01 PM PST 24
Peak memory 199436 kb
Host smart-de87c8dd-2505-4c2c-acc6-ef0173367afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982806869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.2982806869
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.2619548102
Short name T471
Test name
Test status
Simulation time 19504048 ps
CPU time 0.56 seconds
Started Feb 29 12:58:42 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 194016 kb
Host smart-a657dc22-ea0f-4b33-b6c9-97b0748dfd7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619548102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.2619548102
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2175539405
Short name T322
Test name
Test status
Simulation time 22726191159 ps
CPU time 49.12 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:59:23 PM PST 24
Peak memory 224508 kb
Host smart-c07cdafc-0416-4a0f-8963-6521cade6be0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2175539405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2175539405
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1229048168
Short name T536
Test name
Test status
Simulation time 437565944 ps
CPU time 4.73 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:58:43 PM PST 24
Peak memory 199368 kb
Host smart-93906b8e-0b13-4d23-bd40-eaba2ef4ca6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229048168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1229048168
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.2621736001
Short name T414
Test name
Test status
Simulation time 3301279022 ps
CPU time 92.11 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 01:00:06 PM PST 24
Peak memory 199500 kb
Host smart-0e47e1e3-fd97-485b-a4de-dac4b06c8554
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2621736001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.2621736001
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.802880859
Short name T247
Test name
Test status
Simulation time 1488235371 ps
CPU time 20.31 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:56 PM PST 24
Peak memory 199240 kb
Host smart-ac649f4c-9957-48d9-b44f-1597dff1499c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802880859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.802880859
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3639373532
Short name T178
Test name
Test status
Simulation time 2737076330 ps
CPU time 60.64 seconds
Started Feb 29 12:58:34 PM PST 24
Finished Feb 29 12:59:35 PM PST 24
Peak memory 199492 kb
Host smart-af9be9a4-bb7d-48e6-a05e-8e5c3e3b180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639373532 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3639373532
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.1946590737
Short name T569
Test name
Test status
Simulation time 310734761 ps
CPU time 4.29 seconds
Started Feb 29 12:58:48 PM PST 24
Finished Feb 29 12:58:52 PM PST 24
Peak memory 199412 kb
Host smart-a4600379-eced-48a7-8f15-3a8859504fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946590737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.1946590737
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.1308420829
Short name T45
Test name
Test status
Simulation time 6865039816 ps
CPU time 315.15 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 01:03:51 PM PST 24
Peak memory 199480 kb
Host smart-6e44302d-88b2-4b65-a633-6b7aa064466d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308420829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.1308420829
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.333088926
Short name T131
Test name
Test status
Simulation time 26028004 ps
CPU time 0.89 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 12:58:38 PM PST 24
Peak memory 197152 kb
Host smart-7d1841ca-d00c-4d43-a7f2-5f40f45ac7cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333088926 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_hmac_vectors.333088926
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.4071961522
Short name T37
Test name
Test status
Simulation time 39387234381 ps
CPU time 408.06 seconds
Started Feb 29 12:58:30 PM PST 24
Finished Feb 29 01:05:18 PM PST 24
Peak memory 199520 kb
Host smart-46b48448-b776-44bc-975f-c21c4c74b8dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071961522 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.hmac_test_sha_vectors.4071961522
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3771944909
Short name T249
Test name
Test status
Simulation time 7736825903 ps
CPU time 71.81 seconds
Started Feb 29 12:58:42 PM PST 24
Finished Feb 29 12:59:54 PM PST 24
Peak memory 199516 kb
Host smart-69b54c6b-72f9-4304-84d4-888915f4cb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771944909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3771944909
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.11096324
Short name T518
Test name
Test status
Simulation time 29260196 ps
CPU time 0.56 seconds
Started Feb 29 12:58:39 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 193792 kb
Host smart-a369002b-c274-4e7e-b272-c58ebeedec5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11096324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.11096324
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.318274667
Short name T40
Test name
Test status
Simulation time 16327862671 ps
CPU time 47.52 seconds
Started Feb 29 12:58:41 PM PST 24
Finished Feb 29 12:59:29 PM PST 24
Peak memory 230272 kb
Host smart-8d6998d6-4a86-4ca6-922c-906f37dd4372
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=318274667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.318274667
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.4219894738
Short name T476
Test name
Test status
Simulation time 3986850086 ps
CPU time 15.08 seconds
Started Feb 29 12:58:48 PM PST 24
Finished Feb 29 12:59:03 PM PST 24
Peak memory 199332 kb
Host smart-1f75ed4d-698f-4846-94ed-8d1c51dd1856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219894738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.4219894738
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.4002816836
Short name T210
Test name
Test status
Simulation time 2350885600 ps
CPU time 130.75 seconds
Started Feb 29 12:58:39 PM PST 24
Finished Feb 29 01:00:50 PM PST 24
Peak memory 199480 kb
Host smart-e92679b5-ebd3-49cc-8bf4-4de97a2dd3c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4002816836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.4002816836
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.633179964
Short name T406
Test name
Test status
Simulation time 570060142 ps
CPU time 30.24 seconds
Started Feb 29 12:58:51 PM PST 24
Finished Feb 29 12:59:21 PM PST 24
Peak memory 199392 kb
Host smart-be77f1d6-2901-4315-b552-77aa0d57d679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633179964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.633179964
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1653610524
Short name T381
Test name
Test status
Simulation time 3692802207 ps
CPU time 33.26 seconds
Started Feb 29 12:58:38 PM PST 24
Finished Feb 29 12:59:12 PM PST 24
Peak memory 199496 kb
Host smart-6063f57a-2a9a-47aa-b95c-ad09e951b865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653610524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1653610524
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3923451923
Short name T237
Test name
Test status
Simulation time 295471529 ps
CPU time 3.49 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 199372 kb
Host smart-8051361c-2f1c-4b86-ab69-6e2be6473fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923451923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3923451923
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.3602566359
Short name T4
Test name
Test status
Simulation time 77029241290 ps
CPU time 855.03 seconds
Started Feb 29 12:58:44 PM PST 24
Finished Feb 29 01:12:59 PM PST 24
Peak memory 199460 kb
Host smart-9bea26a2-e533-496f-af95-206c22a13155
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602566359 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.3602566359
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1566735220
Short name T206
Test name
Test status
Simulation time 40399601 ps
CPU time 0.98 seconds
Started Feb 29 12:58:35 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 196708 kb
Host smart-18806799-61a3-44d1-b29d-6382c446af32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566735220 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1566735220
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1934990879
Short name T160
Test name
Test status
Simulation time 113635476653 ps
CPU time 484.43 seconds
Started Feb 29 12:58:36 PM PST 24
Finished Feb 29 01:06:41 PM PST 24
Peak memory 199332 kb
Host smart-3a53d307-c9a9-4ba0-b931-40cbe1fbcefb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934990879 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_sha_vectors.1934990879
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.270624725
Short name T394
Test name
Test status
Simulation time 8113929068 ps
CPU time 36.65 seconds
Started Feb 29 12:58:45 PM PST 24
Finished Feb 29 12:59:22 PM PST 24
Peak memory 199488 kb
Host smart-568be720-0f2e-4c9b-8350-514c63a724f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270624725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.270624725
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.2687679358
Short name T204
Test name
Test status
Simulation time 33746210 ps
CPU time 0.55 seconds
Started Feb 29 12:57:26 PM PST 24
Finished Feb 29 12:57:26 PM PST 24
Peak memory 193760 kb
Host smart-54b604cf-43bf-4849-b674-ed25653a2f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687679358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.2687679358
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.428419765
Short name T224
Test name
Test status
Simulation time 1127258848 ps
CPU time 39.8 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 12:58:17 PM PST 24
Peak memory 231984 kb
Host smart-27416199-a0ce-4cdd-bde5-df4ff52e581a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428419765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.428419765
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.227210741
Short name T209
Test name
Test status
Simulation time 3328446981 ps
CPU time 34.66 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:58:19 PM PST 24
Peak memory 199496 kb
Host smart-493bc071-40ba-445a-8689-f91683238a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227210741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.227210741
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1619255641
Short name T357
Test name
Test status
Simulation time 3041017523 ps
CPU time 39.73 seconds
Started Feb 29 12:57:33 PM PST 24
Finished Feb 29 12:58:13 PM PST 24
Peak memory 199544 kb
Host smart-91137ae2-7ad6-49c2-859c-2e7979844241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619255641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1619255641
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.337810092
Short name T110
Test name
Test status
Simulation time 4186664667 ps
CPU time 105.54 seconds
Started Feb 29 12:57:33 PM PST 24
Finished Feb 29 12:59:19 PM PST 24
Peak memory 199496 kb
Host smart-4c29396e-60fb-4762-8c1b-398176ea2cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337810092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.337810092
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.2093917197
Short name T332
Test name
Test status
Simulation time 352207624 ps
CPU time 19.01 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:57:50 PM PST 24
Peak memory 199312 kb
Host smart-13c19fc2-f026-4794-9e46-9d8a77c07a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093917197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.2093917197
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1450739493
Short name T220
Test name
Test status
Simulation time 624660040 ps
CPU time 2.05 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:57:41 PM PST 24
Peak memory 199276 kb
Host smart-79b1260c-9e51-4c6c-9f98-f2a5cb7f8f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450739493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1450739493
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.949612995
Short name T535
Test name
Test status
Simulation time 54890611 ps
CPU time 1.07 seconds
Started Feb 29 12:57:33 PM PST 24
Finished Feb 29 12:57:34 PM PST 24
Peak memory 198496 kb
Host smart-e15a71fd-ebd5-4fae-9028-5dffaec5e08c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949612995 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_hmac_vectors.949612995
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1402136209
Short name T234
Test name
Test status
Simulation time 35119805908 ps
CPU time 399.65 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 01:04:31 PM PST 24
Peak memory 199356 kb
Host smart-880c7318-bcc0-4a09-8182-b5c701ec3d95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402136209 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.hmac_test_sha_vectors.1402136209
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.4033062114
Short name T187
Test name
Test status
Simulation time 32540914378 ps
CPU time 103.89 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:59:27 PM PST 24
Peak memory 199516 kb
Host smart-1b48c2c3-a440-4ce4-863d-db8b0263474b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033062114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.4033062114
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.2762428232
Short name T231
Test name
Test status
Simulation time 13607037 ps
CPU time 0.54 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 193816 kb
Host smart-5230eed3-a512-49e5-a38a-88fb66848dd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762428232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.2762428232
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1867931410
Short name T434
Test name
Test status
Simulation time 3707104057 ps
CPU time 63.62 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:58:40 PM PST 24
Peak memory 219976 kb
Host smart-38e406dc-29ed-4fb5-9796-37a18eede70e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1867931410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1867931410
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.2440203506
Short name T532
Test name
Test status
Simulation time 1195568811 ps
CPU time 5.59 seconds
Started Feb 29 12:57:38 PM PST 24
Finished Feb 29 12:57:44 PM PST 24
Peak memory 199528 kb
Host smart-36d5e316-a008-4ee4-ad51-9e04f05f09ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440203506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.2440203506
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3768207893
Short name T382
Test name
Test status
Simulation time 1292276280 ps
CPU time 68.92 seconds
Started Feb 29 12:57:28 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 199424 kb
Host smart-4216341a-b6d3-4e72-8375-c1741c56eab0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768207893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3768207893
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.867607807
Short name T571
Test name
Test status
Simulation time 2337247203 ps
CPU time 13.4 seconds
Started Feb 29 12:57:42 PM PST 24
Finished Feb 29 12:57:55 PM PST 24
Peak memory 199580 kb
Host smart-62819856-0621-4f76-b08a-99f0cf347937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867607807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.867607807
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3708084636
Short name T261
Test name
Test status
Simulation time 37158512170 ps
CPU time 47.78 seconds
Started Feb 29 12:57:40 PM PST 24
Finished Feb 29 12:58:27 PM PST 24
Peak memory 199492 kb
Host smart-e0c6877a-914e-4554-9bda-7dafc7db977f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708084636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3708084636
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.3896338985
Short name T436
Test name
Test status
Simulation time 2138605653 ps
CPU time 4.64 seconds
Started Feb 29 12:58:05 PM PST 24
Finished Feb 29 12:58:10 PM PST 24
Peak memory 199604 kb
Host smart-af8a8ead-68d4-4315-863c-e912f7bc82d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896338985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.3896338985
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3694343575
Short name T542
Test name
Test status
Simulation time 11785859227 ps
CPU time 537.98 seconds
Started Feb 29 12:57:33 PM PST 24
Finished Feb 29 01:06:31 PM PST 24
Peak memory 239964 kb
Host smart-bb396436-f41e-4c41-b85f-cc72b243c929
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694343575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3694343575
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4210236033
Short name T424
Test name
Test status
Simulation time 58400006 ps
CPU time 1.07 seconds
Started Feb 29 12:57:49 PM PST 24
Finished Feb 29 12:57:51 PM PST 24
Peak memory 197780 kb
Host smart-8b8bd6d4-fb02-4ff6-949f-4f7e7f0fd7c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210236033 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4210236033
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.1577556885
Short name T466
Test name
Test status
Simulation time 12000877854 ps
CPU time 52.63 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 199484 kb
Host smart-bdcb0ef1-9bd3-4621-bb79-e0c37457e7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577556885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.1577556885
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.3648624014
Short name T275
Test name
Test status
Simulation time 96953242 ps
CPU time 0.55 seconds
Started Feb 29 12:57:54 PM PST 24
Finished Feb 29 12:57:54 PM PST 24
Peak memory 194032 kb
Host smart-82b3fcd2-44df-404a-abb4-ac4b3940a081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648624014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.3648624014
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1112594381
Short name T370
Test name
Test status
Simulation time 328840859 ps
CPU time 2.06 seconds
Started Feb 29 12:57:44 PM PST 24
Finished Feb 29 12:57:46 PM PST 24
Peak memory 199420 kb
Host smart-a3987339-288f-4321-a108-6653c85830cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1112594381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1112594381
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1020540679
Short name T591
Test name
Test status
Simulation time 4039789327 ps
CPU time 58.03 seconds
Started Feb 29 12:57:39 PM PST 24
Finished Feb 29 12:58:37 PM PST 24
Peak memory 199508 kb
Host smart-31343898-2695-499a-85ce-5eff50291dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020540679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1020540679
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.4245019798
Short name T590
Test name
Test status
Simulation time 8832308964 ps
CPU time 119.99 seconds
Started Feb 29 12:57:50 PM PST 24
Finished Feb 29 12:59:50 PM PST 24
Peak memory 199532 kb
Host smart-e61ce693-9e51-4237-ac72-2f2b649d8357
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4245019798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.4245019798
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2344459991
Short name T306
Test name
Test status
Simulation time 2093546250 ps
CPU time 105.28 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:59:32 PM PST 24
Peak memory 199400 kb
Host smart-d8702f50-4be4-4efa-8d24-357c6aa54820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344459991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2344459991
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3584123908
Short name T396
Test name
Test status
Simulation time 20944785346 ps
CPU time 49.69 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199484 kb
Host smart-ff052ec5-7565-4d73-afa6-c8faa1419d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584123908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3584123908
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2603509302
Short name T194
Test name
Test status
Simulation time 244424949 ps
CPU time 0.64 seconds
Started Feb 29 12:57:29 PM PST 24
Finished Feb 29 12:57:30 PM PST 24
Peak memory 194888 kb
Host smart-19ad8d8e-07de-4c26-903f-77f648ce78c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603509302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2603509302
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.555372741
Short name T289
Test name
Test status
Simulation time 61116800719 ps
CPU time 387.55 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 01:04:15 PM PST 24
Peak memory 247764 kb
Host smart-e40718f9-04f3-4bab-a193-31c4290c69eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555372741 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.555372741
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.1019587628
Short name T559
Test name
Test status
Simulation time 41678636 ps
CPU time 0.89 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:57:48 PM PST 24
Peak memory 197464 kb
Host smart-ac070529-ca25-4b44-9b03-122177fe5954
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019587628 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.1019587628
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.135263850
Short name T474
Test name
Test status
Simulation time 60390793449 ps
CPU time 397.3 seconds
Started Feb 29 12:57:37 PM PST 24
Finished Feb 29 01:04:14 PM PST 24
Peak memory 199348 kb
Host smart-35cb85b6-40f4-4dcb-965f-c2395cbeeca4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135263850 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 7.hmac_test_sha_vectors.135263850
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1225486314
Short name T304
Test name
Test status
Simulation time 560688920 ps
CPU time 17.99 seconds
Started Feb 29 12:57:55 PM PST 24
Finished Feb 29 12:58:14 PM PST 24
Peak memory 199344 kb
Host smart-c117c469-f378-4e98-a70f-5e6313aff2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225486314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1225486314
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2846692598
Short name T134
Test name
Test status
Simulation time 30751700 ps
CPU time 0.56 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 193972 kb
Host smart-c7e460e2-29e2-4d6e-a5bb-286f26ce7b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846692598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2846692598
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1910628627
Short name T238
Test name
Test status
Simulation time 1382120338 ps
CPU time 47.3 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 218868 kb
Host smart-660b91e1-53b9-4913-bd0b-96a0380e5077
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1910628627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1910628627
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2221781149
Short name T269
Test name
Test status
Simulation time 1501386893 ps
CPU time 51.66 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:58:32 PM PST 24
Peak memory 199428 kb
Host smart-0d5ce9a0-a410-4bd5-9321-3f9c7745ec28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221781149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2221781149
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2747373333
Short name T407
Test name
Test status
Simulation time 2146882847 ps
CPU time 111.37 seconds
Started Feb 29 12:57:40 PM PST 24
Finished Feb 29 12:59:32 PM PST 24
Peak memory 199440 kb
Host smart-06487afa-9564-4c48-b286-50581b580d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747373333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2747373333
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.597221164
Short name T537
Test name
Test status
Simulation time 6944815495 ps
CPU time 115.67 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:59:39 PM PST 24
Peak memory 199484 kb
Host smart-3529c092-015d-4dea-9217-8e8c5a184aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597221164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.597221164
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1310439312
Short name T383
Test name
Test status
Simulation time 1025989796 ps
CPU time 56.15 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:58:39 PM PST 24
Peak memory 199660 kb
Host smart-45198c2a-4924-4678-90b2-5e82fb4e5b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310439312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1310439312
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3336696430
Short name T334
Test name
Test status
Simulation time 129356473 ps
CPU time 2.09 seconds
Started Feb 29 12:57:36 PM PST 24
Finished Feb 29 12:57:38 PM PST 24
Peak memory 199388 kb
Host smart-2237e495-0e76-4fd7-815d-c3cc4f9bbe62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336696430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3336696430
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.3343579369
Short name T58
Test name
Test status
Simulation time 133772166172 ps
CPU time 358.29 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 01:03:46 PM PST 24
Peak memory 199536 kb
Host smart-8639a37f-220c-447a-9976-cbebe73aec7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343579369 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.3343579369
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.2257468287
Short name T556
Test name
Test status
Simulation time 88704648 ps
CPU time 1 seconds
Started Feb 29 12:57:47 PM PST 24
Finished Feb 29 12:57:48 PM PST 24
Peak memory 197944 kb
Host smart-5c28318a-0405-4e6b-8da7-7ab27f10cd0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257468287 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.2257468287
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.3753288835
Short name T158
Test name
Test status
Simulation time 34530943375 ps
CPU time 419.37 seconds
Started Feb 29 12:57:48 PM PST 24
Finished Feb 29 01:04:48 PM PST 24
Peak memory 199372 kb
Host smart-ac6078c8-842e-4d0b-977d-5946c311f10c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753288835 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.hmac_test_sha_vectors.3753288835
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.3518079239
Short name T459
Test name
Test status
Simulation time 1156940530 ps
CPU time 5.82 seconds
Started Feb 29 12:57:53 PM PST 24
Finished Feb 29 12:57:59 PM PST 24
Peak memory 199400 kb
Host smart-0ba725a9-4002-4499-b06e-f1189c57ff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518079239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.3518079239
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2443280149
Short name T478
Test name
Test status
Simulation time 23130378 ps
CPU time 0.56 seconds
Started Feb 29 12:57:41 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 194016 kb
Host smart-5858aaca-f987-42db-b0ea-163712e6244c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443280149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2443280149
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2530070995
Short name T260
Test name
Test status
Simulation time 1195414118 ps
CPU time 17.69 seconds
Started Feb 29 12:57:58 PM PST 24
Finished Feb 29 12:58:16 PM PST 24
Peak memory 215236 kb
Host smart-700d1266-08e1-4e7b-9445-fa96c9a9e329
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2530070995 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2530070995
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2687611614
Short name T597
Test name
Test status
Simulation time 393151777 ps
CPU time 2.38 seconds
Started Feb 29 12:57:31 PM PST 24
Finished Feb 29 12:57:34 PM PST 24
Peak memory 199412 kb
Host smart-2b8fc4d6-49b8-4133-ad10-458f456b4047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687611614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2687611614
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1818501499
Short name T141
Test name
Test status
Simulation time 688919352 ps
CPU time 36.48 seconds
Started Feb 29 12:57:35 PM PST 24
Finished Feb 29 12:58:12 PM PST 24
Peak memory 199348 kb
Host smart-daa73ac8-61d2-4d91-9b52-77ffb63aa4b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1818501499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1818501499
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1769153482
Short name T181
Test name
Test status
Simulation time 4355730986 ps
CPU time 110.49 seconds
Started Feb 29 12:57:43 PM PST 24
Finished Feb 29 12:59:34 PM PST 24
Peak memory 199464 kb
Host smart-f686e775-8165-45b5-ae61-3665a55d325e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769153482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1769153482
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3973061161
Short name T360
Test name
Test status
Simulation time 3470257010 ps
CPU time 23.29 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:58:08 PM PST 24
Peak memory 199524 kb
Host smart-03df5020-dc06-47d6-9d01-7b70cfaa76c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973061161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3973061161
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2593938509
Short name T228
Test name
Test status
Simulation time 120674411 ps
CPU time 1.54 seconds
Started Feb 29 12:57:40 PM PST 24
Finished Feb 29 12:57:42 PM PST 24
Peak memory 199244 kb
Host smart-02767f39-b60b-45d8-971e-e938ad3b2f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593938509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2593938509
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.2309038753
Short name T565
Test name
Test status
Simulation time 74735138384 ps
CPU time 1871.75 seconds
Started Feb 29 12:57:59 PM PST 24
Finished Feb 29 01:29:16 PM PST 24
Peak memory 234728 kb
Host smart-66732e26-7ec3-42da-ae2d-3308aed292c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309038753 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.2309038753
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2218012786
Short name T563
Test name
Test status
Simulation time 25859352 ps
CPU time 0.89 seconds
Started Feb 29 12:57:51 PM PST 24
Finished Feb 29 12:57:52 PM PST 24
Peak memory 197060 kb
Host smart-4ae5293f-0542-4630-8597-8751caea0003
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218012786 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2218012786
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.1176305146
Short name T126
Test name
Test status
Simulation time 8520619984 ps
CPU time 417.34 seconds
Started Feb 29 12:57:35 PM PST 24
Finished Feb 29 01:04:33 PM PST 24
Peak memory 199376 kb
Host smart-89630723-985f-4155-b4ea-4b4fa95df9cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176305146 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.hmac_test_sha_vectors.1176305146
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3217370260
Short name T573
Test name
Test status
Simulation time 11639528127 ps
CPU time 38.52 seconds
Started Feb 29 12:57:45 PM PST 24
Finished Feb 29 12:58:24 PM PST 24
Peak memory 199524 kb
Host smart-f54a1d7a-a7e1-4793-b166-148a76cc11fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217370260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3217370260
Directory /workspace/9.hmac_wipe_secret/latest
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