Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

38488461

1

T1

23609

T2

11743

T3

10112

full_word

36595541

1

T1

17763

T2

27260

T3

8252

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	75083662	1			T1	41372		T2	39003		T3	18364
auto[TlIntgErrCmd]	110	1			T49	2		T50	3		T51	6
auto[TlIntgErrData]	114	1			T49	4		T50	4		T51	7
auto[TlIntgErrBoth]	116	1			T49	4		T50	3		T51	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30171639

1

T1

25261

T2

15552

T3

7398

auto[1]

44912363

1

T1

16111

T2

23451

T3

10966

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16078239	1			T1	23325		T2	11411		T3	3765
auto[TlIntgErrNone]	partial	auto[1]	22409910	1			T1	284		T2	332		T3	6347
auto[TlIntgErrNone]	full_word	auto[0]	14093245	1			T1	1936		T2	4141		T3	3633
auto[TlIntgErrNone]	full_word	auto[1]	22502268	1			T1	15827		T2	23119		T3	4619
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T49	2		T51	1		T136	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T50	3		T51	4		T136	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T136	1		T137	1		T141	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T51	1		T142	1		T143	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T49	1		T51	3		T136	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T49	3		T50	4		T51	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T51	1		T140	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T136	1		T137	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	44	1			T49	2		T50	2		T51	1
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T49	2		T50	1		T51	6
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T136	1		T137	1		T139	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T56	2		-	-		-	-