Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.28	94.90	84.09	100.00	40.00	86.67	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	444972777	1330817	0	0
intr_enable_rd_A	444972777	2547	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444972777	1330817	0	0
T19	393113	177609	0	0
T20	0	27027	0	0
T21	0	55297	0	0
T39	0	86651	0	0
T40	0	156531	0	0
T41	0	191844	0	0
T57	0	7213	0	0
T58	0	112033	0	0
T59	0	24181	0	0
T60	0	496	0	0
T61	62633	0	0	0
T62	131117	0	0	0
T63	447715	0	0	0
T64	230594	0	0	0
T65	27944	0	0	0
T66	80310	0	0	0
T67	258979	0	0	0
T68	340915	0	0	0
T69	84654	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444972777	2547	0	0
T4	643224	28	0	0
T46	4370	0	0	0
T53	304662	0	0	0
T55	0	7	0	0
T70	0	18	0	0
T71	0	16	0	0
T72	0	40	0	0
T73	0	10	0	0
T74	0	20	0	0
T75	0	29	0	0
T76	0	38	0	0
T77	0	428	0	0
T78	21624	0	0	0
T79	25607	0	0	0
T80	13003	0	0	0
T81	31565	0	0	0
T82	800382	0	0	0
T83	4648	0	0	0
T84	38629	0	0	0