Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42875859

1

T1

49433

T2

57512

T3

78852

full_word

40420148

1

T1

46922

T2

55654

T3

77363

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	83295587	1			T1	96355		T2	113166		T3	156215
auto[TlIntgErrCmd]	132	1			T44	3		T45	7		T46	3
auto[TlIntgErrData]	149	1			T44	3		T45	13		T46	5
auto[TlIntgErrBoth]	139	1			T44	4		T45	10		T46	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33297729

1

T1

43446

T2

52238

T3

68602

auto[1]

49998278

1

T1

52909

T2

60928

T3

87613

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17748569	1			T1	21812		T2	26161		T3	34177
auto[TlIntgErrNone]	partial	auto[1]	25126912	1			T1	27621		T2	31351		T3	44675
auto[TlIntgErrNone]	full_word	auto[0]	15548967	1			T1	21634		T2	26077		T3	34425
auto[TlIntgErrNone]	full_word	auto[1]	24871139	1			T1	25288		T2	29577		T3	42938
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T44	2		T45	1		T46	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T44	1		T45	4		T46	2
auto[TlIntgErrCmd]	full_word	auto[0]	11	1			T45	1		T129	1		T135	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T45	1		T135	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	67	1			T44	2		T45	4		T46	3
auto[TlIntgErrData]	partial	auto[1]	68	1			T44	1		T45	9		T46	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T129	1		T137	1		T133	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T46	1		T129	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T44	2		T45	4		T129	2
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T44	1		T45	6		T46	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T133	1		T131	1		T138	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T44	1		T132	1		T137	1