Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37279444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40345141

1

T1

433968

T2

20889

T3

40082

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31006049	1			T1	358181		T2	18486		T3	35022
values[0x0]	21720482	1			T1	240133		T2	11854		T3	23113
values[0x1]	24898054	1			T1	272525		T2	14878		T3	28508

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27308249	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50316336

1

T1

549601

T2

27492

T3

52529

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	631319	1			T1	3252		T2	179		T3	355
valid_sources[0x01]	276880	1			T1	3497		T2	157		T3	314
valid_sources[0x02]	253553	1			T1	3430		T2	155		T3	312
valid_sources[0x03]	291865	1			T1	3526		T2	153		T3	360
valid_sources[0x04]	254458	1			T1	3444		T2	193		T3	369
valid_sources[0x05]	271722	1			T1	3277		T2	178		T3	349
valid_sources[0x06]	282773	1			T1	3472		T2	189		T3	319
valid_sources[0x07]	252873	1			T1	3413		T2	139		T3	330
valid_sources[0x08]	261799	1			T1	3270		T2	183		T3	341
valid_sources[0x09]	272431	1			T1	3277		T2	213		T3	332
valid_sources[0x0a]	336994	1			T1	3438		T2	153		T3	324
valid_sources[0x0b]	267921	1			T1	3384		T2	155		T3	349
valid_sources[0x0c]	256595	1			T1	3284		T2	155		T3	340
valid_sources[0x0d]	260879	1			T1	3386		T2	138		T3	335
valid_sources[0x0e]	266975	1			T1	3667		T2	152		T3	332
valid_sources[0x0f]	256999	1			T1	3475		T2	183		T3	379
valid_sources[0x10]	663849	1			T1	3402		T2	224		T3	360
valid_sources[0x11]	264073	1			T1	3190		T2	170		T3	342
valid_sources[0x12]	261889	1			T1	3456		T2	170		T3	364
valid_sources[0x13]	257141	1			T1	3427		T2	139		T3	333
valid_sources[0x14]	262864	1			T1	3467		T2	191		T3	360
valid_sources[0x15]	304492	1			T1	3386		T2	205		T3	347
valid_sources[0x16]	266298	1			T1	3392		T2	193		T3	344
valid_sources[0x17]	261962	1			T1	3491		T2	156		T3	291
valid_sources[0x18]	273197	1			T1	3460		T2	146		T3	309
valid_sources[0x19]	266024	1			T1	3607		T2	147		T3	354
valid_sources[0x1a]	257404	1			T1	3438		T2	238		T3	334
valid_sources[0x1b]	257206	1			T1	3419		T2	216		T3	332
valid_sources[0x1c]	270140	1			T1	3318		T2	207		T3	348
valid_sources[0x1d]	302325	1			T1	3235		T2	172		T3	349
valid_sources[0x1e]	258656	1			T1	3465		T2	142		T3	354
valid_sources[0x1f]	272125	1			T1	3181		T2	184		T3	277
valid_sources[0x20]	257421	1			T1	3426		T2	259		T3	319
valid_sources[0x21]	282284	1			T1	3213		T2	239		T3	311
valid_sources[0x22]	259844	1			T1	3567		T2	161		T3	358
valid_sources[0x23]	306818	1			T1	3406		T2	170		T3	341
valid_sources[0x24]	287628	1			T1	3559		T2	171		T3	306
valid_sources[0x25]	259107	1			T1	3314		T2	217		T3	343
valid_sources[0x26]	254029	1			T1	3416		T2	188		T3	353
valid_sources[0x27]	270289	1			T1	3396		T2	179		T3	368
valid_sources[0x28]	274150	1			T1	3453		T2	136		T3	370
valid_sources[0x29]	258038	1			T1	3322		T2	204		T3	371
valid_sources[0x2a]	268595	1			T1	3401		T2	160		T3	363
valid_sources[0x2b]	261509	1			T1	3452		T2	182		T3	318
valid_sources[0x2c]	252438	1			T1	3555		T2	120		T3	348
valid_sources[0x2d]	251340	1			T1	3267		T2	137		T3	332
valid_sources[0x2e]	270629	1			T1	3553		T2	217		T3	331
valid_sources[0x2f]	259083	1			T1	3466		T2	190		T3	319
valid_sources[0x30]	256224	1			T1	3375		T2	285		T3	334
valid_sources[0x31]	265024	1			T1	3525		T2	125		T3	333
valid_sources[0x32]	271607	1			T1	3360		T2	168		T3	391
valid_sources[0x33]	253533	1			T1	3357		T2	171		T3	359
valid_sources[0x34]	259869	1			T1	3351		T2	159		T3	353
valid_sources[0x35]	713673	1			T1	3441		T2	158		T3	339
valid_sources[0x36]	251151	1			T1	3316		T2	198		T3	338
valid_sources[0x37]	306354	1			T1	3320		T2	190		T3	370
valid_sources[0x38]	259545	1			T1	3255		T2	210		T3	322
valid_sources[0x39]	259415	1			T1	3375		T2	200		T3	347
valid_sources[0x3a]	315550	1			T1	3485		T2	209		T3	338
valid_sources[0x3b]	631898	1			T1	3406		T2	142		T3	287
valid_sources[0x3c]	275664	1			T1	3396		T2	165		T3	333
valid_sources[0x3d]	309604	1			T1	3460		T2	155		T3	343
valid_sources[0x3e]	296294	1			T1	3590		T2	252		T3	328
valid_sources[0x3f]	313636	1			T1	3504		T2	130		T3	344
valid_sources[0x40]	276211	1			T1	3311		T2	165		T3	329
valid_sources[0x41]	258300	1			T1	3281		T2	177		T3	315
valid_sources[0x42]	262340	1			T1	3405		T2	180		T3	359
valid_sources[0x43]	252974	1			T1	3259		T2	181		T3	361
valid_sources[0x44]	308743	1			T1	3396		T2	159		T3	352
valid_sources[0x45]	294567	1			T1	3415		T2	242		T3	366
valid_sources[0x46]	267922	1			T1	3366		T2	159		T3	299
valid_sources[0x47]	666703	1			T1	3401		T2	160		T3	348
valid_sources[0x48]	291381	1			T1	3400		T2	192		T3	339
valid_sources[0x49]	316063	1			T1	3665		T2	181		T3	344
valid_sources[0x4a]	255081	1			T1	3372		T2	202		T3	339
valid_sources[0x4b]	258916	1			T1	3436		T2	166		T3	338
valid_sources[0x4c]	624112	1			T1	3598		T2	186		T3	326
valid_sources[0x4d]	255111	1			T1	3140		T2	169		T3	326
valid_sources[0x4e]	258166	1			T1	3426		T2	175		T3	332
valid_sources[0x4f]	253379	1			T1	3353		T2	129		T3	382
valid_sources[0x50]	290767	1			T1	3433		T2	169		T3	330
valid_sources[0x51]	245271	1			T1	3395		T2	183		T3	333
valid_sources[0x52]	268386	1			T1	3486		T2	160		T3	320
valid_sources[0x53]	278444	1			T1	3536		T2	230		T3	318
valid_sources[0x54]	254884	1			T1	3457		T2	205		T3	351
valid_sources[0x55]	302993	1			T1	3534		T2	161		T3	348
valid_sources[0x56]	264175	1			T1	3284		T2	136		T3	326
valid_sources[0x57]	270336	1			T1	3589		T2	183		T3	342
valid_sources[0x58]	284060	1			T1	3530		T2	191		T3	317
valid_sources[0x59]	272794	1			T1	3283		T2	158		T3	333
valid_sources[0x5a]	263036	1			T1	3255		T2	215		T3	386
valid_sources[0x5b]	257931	1			T1	3235		T2	143		T3	333
valid_sources[0x5c]	265470	1			T1	3538		T2	211		T3	297
valid_sources[0x5d]	499919	1			T1	3327		T2	161		T3	363
valid_sources[0x5e]	281623	1			T1	3255		T2	208		T3	347
valid_sources[0x5f]	675795	1			T1	3336		T2	132		T3	346
valid_sources[0x60]	265131	1			T1	3492		T2	187		T3	337
valid_sources[0x61]	271130	1			T1	3556		T2	175		T3	365
valid_sources[0x62]	278917	1			T1	3376		T2	159		T3	326
valid_sources[0x63]	280699	1			T1	3472		T2	177		T3	353
valid_sources[0x64]	250620	1			T1	3438		T2	147		T3	316
valid_sources[0x65]	271978	1			T1	3263		T2	159		T3	335
valid_sources[0x66]	301811	1			T1	3356		T2	193		T3	337
valid_sources[0x67]	258360	1			T1	3518		T2	158		T3	366
valid_sources[0x68]	258376	1			T1	3485		T2	172		T3	315
valid_sources[0x69]	266076	1			T1	3412		T2	164		T3	319
valid_sources[0x6a]	295919	1			T1	3475		T2	112		T3	366
valid_sources[0x6b]	273939	1			T1	3408		T2	149		T3	321
valid_sources[0x6c]	250887	1			T1	3492		T2	162		T3	342
valid_sources[0x6d]	271326	1			T1	3571		T2	227		T3	310
valid_sources[0x6e]	291692	1			T1	3394		T2	156		T3	341
valid_sources[0x6f]	651059	1			T1	3487		T2	203		T3	329
valid_sources[0x70]	262255	1			T1	3476		T2	189		T3	335
valid_sources[0x71]	272982	1			T1	3288		T2	165		T3	357
valid_sources[0x72]	278290	1			T1	3516		T2	210		T3	352
valid_sources[0x73]	249604	1			T1	3389		T2	154		T3	357
valid_sources[0x74]	280681	1			T1	3421		T2	161		T3	322
valid_sources[0x75]	268761	1			T1	3309		T2	182		T3	346
valid_sources[0x76]	280055	1			T1	3463		T2	178		T3	332
valid_sources[0x77]	275532	1			T1	3568		T2	138		T3	308
valid_sources[0x78]	295514	1			T1	3501		T2	183		T3	333
valid_sources[0x79]	270436	1			T1	3326		T2	207		T3	357
valid_sources[0x7a]	256147	1			T1	3295		T2	217		T3	348
valid_sources[0x7b]	310128	1			T1	3454		T2	173		T3	303
valid_sources[0x7c]	318025	1			T1	3462		T2	187		T3	358
valid_sources[0x7d]	274813	1			T1	3404		T2	167		T3	338
valid_sources[0x7e]	267557	1			T1	3429		T2	224		T3	334
valid_sources[0x7f]	274184	1			T1	3322		T2	187		T3	375
valid_sources[0x80]	263159	1			T1	3365		T2	135		T3	341

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14846147

1

T1

168732

T2

9190

T3

17564

values[0x0]

all_enables

biggest_size

13394999

1

T1

140877

T2

6185

T3

12006

values[0x1]

all_enables

biggest_size

12103995

1

T1

124359

T2

5514

T3

10512