Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42935169

1

T1

436871

T2

24329

T3

46561

full_word

40713861

1

T1

433968

T2

20889

T3

40082

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	83648630	1			T1	870839		T2	45218		T3	86643
auto[TlIntgErrCmd]	137	1			T59	1		T60	6		T61	10
auto[TlIntgErrData]	137	1			T59	3		T60	1		T61	10
auto[TlIntgErrBoth]	126	1			T59	6		T60	3		T61	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32951464

1

T1

358181

T2

18486

T3

35022

auto[1]

50697566

1

T1

512658

T2

26732

T3

51621

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17957663	1			T1	189449		T2	9296		T3	17458
auto[TlIntgErrNone]	partial	auto[1]	24977142	1			T1	247422		T2	15033		T3	29103
auto[TlIntgErrNone]	full_word	auto[0]	14993630	1			T1	168732		T2	9190		T3	17564
auto[TlIntgErrNone]	full_word	auto[1]	25720195	1			T1	265236		T2	11699		T3	22518
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T60	1		T61	2		T122	1
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T60	4		T61	8		T122	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T60	1		T122	1		T125	1
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T59	1		T126	2		T127	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T59	2		T61	2		T122	3
auto[TlIntgErrData]	partial	auto[1]	75	1			T59	1		T61	7		T122	5
auto[TlIntgErrData]	full_word	auto[0]	3	1			T60	1		T123	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T61	1		T123	1		T125	1
auto[TlIntgErrBoth]	partial	auto[0]	57	1			T59	5		T60	2		T61	5
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T59	1		T61	2		T122	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T61	2		T128	1		T124	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T60	1		T61	1		T122	1