Unified Coverage Report :: Module :: hmac_reg_top

Module : hmac_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.27	100.00	97.09			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	99.27	100.00	97.09			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.27	100.00	97.09			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.20	94.80	97.48	100.00		98.72	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test	100.00	100.00
u_cfg_digest_size	100.00	100.00
u_cfg_digest_swap	100.00	100.00
u_cfg_endian_swap	100.00	100.00
u_cfg_hmac_en	100.00	100.00
u_cfg_key_length	100.00	100.00
u_cfg_sha_en	100.00	100.00
u_chk	100.00	100.00		100.00			100.00
u_cmd_hash_continue	100.00	100.00
u_cmd_hash_process	100.00	100.00
u_cmd_hash_start	100.00	100.00
u_cmd_hash_stop	100.00	100.00
u_digest_0	100.00	100.00
u_digest_1	100.00	100.00
u_digest_10	100.00	100.00
u_digest_11	100.00	100.00
u_digest_12	100.00	100.00
u_digest_13	100.00	100.00
u_digest_14	100.00	100.00
u_digest_15	100.00	100.00
u_digest_2	100.00	100.00
u_digest_3	100.00	100.00
u_digest_4	100.00	100.00
u_digest_5	100.00	100.00
u_digest_6	100.00	100.00
u_digest_7	100.00	100.00
u_digest_8	100.00	100.00
u_digest_9	100.00	100.00
u_err_code	100.00	100.00	100.00			100.00
u_intr_enable_fifo_empty	100.00	100.00	100.00			100.00
u_intr_enable_hmac_done	100.00	100.00	100.00			100.00
u_intr_enable_hmac_err	100.00	100.00	100.00			100.00
u_intr_state_fifo_empty	62.59	77.78	50.00			60.00
u_intr_state_hmac_done	100.00	100.00	100.00			100.00
u_intr_state_hmac_err	100.00	100.00	100.00			100.00
u_intr_test_fifo_empty	100.00	100.00
u_intr_test_hmac_done	100.00	100.00
u_intr_test_hmac_err	100.00	100.00
u_key_0	100.00	100.00
u_key_1	100.00	100.00
u_key_10	50.00	50.00
u_key_11	50.00	50.00
u_key_12	50.00	50.00
u_key_13	50.00	50.00
u_key_14	50.00	50.00
u_key_15	50.00	50.00
u_key_16	50.00	50.00
u_key_17	50.00	50.00
u_key_18	50.00	50.00
u_key_19	50.00	50.00
u_key_2	100.00	100.00
u_key_20	50.00	50.00
u_key_21	50.00	50.00
u_key_22	50.00	50.00
u_key_23	50.00	50.00
u_key_24	50.00	50.00
u_key_25	50.00	50.00
u_key_26	50.00	50.00
u_key_27	50.00	50.00
u_key_28	50.00	50.00
u_key_29	50.00	50.00
u_key_3	100.00	100.00
u_key_30	50.00	50.00
u_key_31	50.00	50.00
u_key_4	100.00	100.00
u_key_5	100.00	100.00
u_key_6	100.00	100.00
u_key_7	100.00	100.00
u_key_8	50.00	50.00
u_key_9	50.00	50.00
u_msg_length_lower	100.00	100.00
u_msg_length_upper	100.00	100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	99.69	100.00	98.75			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_socket	99.69	98.75	100.00			100.00	100.00
u_status_fifo_depth	100.00	100.00
u_status_fifo_empty	100.00	100.00
u_status_fifo_full	100.00	100.00
u_wipe_secret	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
TOTAL		482	482	100.00
ALWAYS	73	4	4	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	525	1	1	100.00
CONT_ASSIGN	540	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	572	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	645	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	677	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	730	1	1	100.00
CONT_ASSIGN	746	1	1	100.00
CONT_ASSIGN	762	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	864	1	1	100.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	885	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	927	1	1	100.00
CONT_ASSIGN	941	1	1	100.00
CONT_ASSIGN	948	1	1	100.00
CONT_ASSIGN	962	1	1	100.00
CONT_ASSIGN	969	1	1	100.00
CONT_ASSIGN	983	1	1	100.00
CONT_ASSIGN	990	1	1	100.00
CONT_ASSIGN	1004	1	1	100.00
CONT_ASSIGN	1011	1	1	100.00
CONT_ASSIGN	1025	1	1	100.00
CONT_ASSIGN	1032	1	1	100.00
CONT_ASSIGN	1046	1	1	100.00
CONT_ASSIGN	1053	1	1	100.00
CONT_ASSIGN	1067	1	1	100.00
CONT_ASSIGN	1074	1	1	100.00
CONT_ASSIGN	1088	1	1	100.00
CONT_ASSIGN	1095	1	1	100.00
CONT_ASSIGN	1109	1	1	100.00
CONT_ASSIGN	1116	1	1	100.00
CONT_ASSIGN	1130	1	1	100.00
CONT_ASSIGN	1137	1	1	100.00
CONT_ASSIGN	1151	1	1	100.00
CONT_ASSIGN	1158	1	1	100.00
CONT_ASSIGN	1172	1	1	100.00
CONT_ASSIGN	1179	1	1	100.00
CONT_ASSIGN	1193	1	1	100.00
CONT_ASSIGN	1200	1	1	100.00
CONT_ASSIGN	1214	1	1	100.00
CONT_ASSIGN	1221	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1256	1	1	100.00
CONT_ASSIGN	1263	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1347	1	1	100.00
CONT_ASSIGN	1361	1	1	100.00
CONT_ASSIGN	1368	1	1	100.00
CONT_ASSIGN	1382	1	1	100.00
CONT_ASSIGN	1389	1	1	100.00
CONT_ASSIGN	1403	1	1	100.00
CONT_ASSIGN	1410	1	1	100.00
CONT_ASSIGN	1424	1	1	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1445	1	1	100.00
CONT_ASSIGN	1452	1	1	100.00
CONT_ASSIGN	1466	1	1	100.00
CONT_ASSIGN	1473	1	1	100.00
CONT_ASSIGN	1487	1	1	100.00
CONT_ASSIGN	1494	1	1	100.00
CONT_ASSIGN	1508	1	1	100.00
CONT_ASSIGN	1515	1	1	100.00
CONT_ASSIGN	1529	1	1	100.00
CONT_ASSIGN	1536	1	1	100.00
CONT_ASSIGN	1550	1	1	100.00
CONT_ASSIGN	1557	1	1	100.00
CONT_ASSIGN	1571	1	1	100.00
CONT_ASSIGN	1578	1	1	100.00
CONT_ASSIGN	1592	1	1	100.00
CONT_ASSIGN	1599	1	1	100.00
CONT_ASSIGN	1613	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1634	1	1	100.00
CONT_ASSIGN	1641	1	1	100.00
CONT_ASSIGN	1655	1	1	100.00
CONT_ASSIGN	1662	1	1	100.00
CONT_ASSIGN	1676	1	1	100.00
CONT_ASSIGN	1683	1	1	100.00
CONT_ASSIGN	1697	1	1	100.00
CONT_ASSIGN	1704	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
CONT_ASSIGN	1725	1	1	100.00
CONT_ASSIGN	1739	1	1	100.00
CONT_ASSIGN	1746	1	1	100.00
CONT_ASSIGN	1760	1	1	100.00
CONT_ASSIGN	1767	1	1	100.00
CONT_ASSIGN	1781	1	1	100.00
CONT_ASSIGN	1788	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1809	1	1	100.00
CONT_ASSIGN	1823	1	1	100.00
CONT_ASSIGN	1830	1	1	100.00
CONT_ASSIGN	1844	1	1	100.00
CONT_ASSIGN	1851	1	1	100.00
CONT_ASSIGN	1865	1	1	100.00
CONT_ASSIGN	1871	1	1	100.00
CONT_ASSIGN	1885	1	1	100.00
CONT_ASSIGN	1891	1	1	100.00
CONT_ASSIGN	1905	1	1	100.00
ALWAYS	1911	60	60	100.00
CONT_ASSIGN	1973	1	1	100.00
ALWAYS	1977	1	1	100.00
CONT_ASSIGN	2040	1	1	100.00
CONT_ASSIGN	2042	1	1	100.00
CONT_ASSIGN	2044	1	1	100.00
CONT_ASSIGN	2045	1	1	100.00
CONT_ASSIGN	2047	1	1	100.00
CONT_ASSIGN	2049	1	1	100.00
CONT_ASSIGN	2051	1	1	100.00
CONT_ASSIGN	2052	1	1	100.00
CONT_ASSIGN	2054	1	1	100.00
CONT_ASSIGN	2056	1	1	100.00
CONT_ASSIGN	2058	1	1	100.00
CONT_ASSIGN	2059	1	1	100.00
CONT_ASSIGN	2061	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2063	1	1	100.00
CONT_ASSIGN	2065	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2069	1	1	100.00
CONT_ASSIGN	2071	1	1	100.00
CONT_ASSIGN	2073	1	1	100.00
CONT_ASSIGN	2075	1	1	100.00
CONT_ASSIGN	2076	1	1	100.00
CONT_ASSIGN	2078	1	1	100.00
CONT_ASSIGN	2080	1	1	100.00
CONT_ASSIGN	2082	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2085	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2089	1	1	100.00
CONT_ASSIGN	2091	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2094	1	1	100.00
CONT_ASSIGN	2095	1	1	100.00
CONT_ASSIGN	2097	1	1	100.00
CONT_ASSIGN	2098	1	1	100.00
CONT_ASSIGN	2100	1	1	100.00
CONT_ASSIGN	2101	1	1	100.00
CONT_ASSIGN	2103	1	1	100.00
CONT_ASSIGN	2104	1	1	100.00
CONT_ASSIGN	2106	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2110	1	1	100.00
CONT_ASSIGN	2112	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2115	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2119	1	1	100.00
CONT_ASSIGN	2121	1	1	100.00
CONT_ASSIGN	2122	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2128	1	1	100.00
CONT_ASSIGN	2130	1	1	100.00
CONT_ASSIGN	2131	1	1	100.00
CONT_ASSIGN	2133	1	1	100.00
CONT_ASSIGN	2134	1	1	100.00
CONT_ASSIGN	2136	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2140	1	1	100.00
CONT_ASSIGN	2142	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2145	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2167	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2170	1	1	100.00
CONT_ASSIGN	2172	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2175	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2182	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2185	1	1	100.00
CONT_ASSIGN	2186	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2189	1	1	100.00
CONT_ASSIGN	2190	1	1	100.00
CONT_ASSIGN	2192	1	1	100.00
CONT_ASSIGN	2193	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2196	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2198	1	1	100.00
CONT_ASSIGN	2200	1	1	100.00
CONT_ASSIGN	2201	1	1	100.00
CONT_ASSIGN	2202	1	1	100.00
CONT_ASSIGN	2204	1	1	100.00
CONT_ASSIGN	2205	1	1	100.00
CONT_ASSIGN	2206	1	1	100.00
CONT_ASSIGN	2208	1	1	100.00
CONT_ASSIGN	2209	1	1	100.00
CONT_ASSIGN	2210	1	1	100.00
CONT_ASSIGN	2212	1	1	100.00
CONT_ASSIGN	2213	1	1	100.00
CONT_ASSIGN	2214	1	1	100.00
CONT_ASSIGN	2216	1	1	100.00
CONT_ASSIGN	2217	1	1	100.00
CONT_ASSIGN	2218	1	1	100.00
CONT_ASSIGN	2220	1	1	100.00
CONT_ASSIGN	2221	1	1	100.00
CONT_ASSIGN	2222	1	1	100.00
CONT_ASSIGN	2224	1	1	100.00
CONT_ASSIGN	2225	1	1	100.00
CONT_ASSIGN	2226	1	1	100.00
CONT_ASSIGN	2228	1	1	100.00
CONT_ASSIGN	2229	1	1	100.00
CONT_ASSIGN	2230	1	1	100.00
CONT_ASSIGN	2232	1	1	100.00
CONT_ASSIGN	2233	1	1	100.00
CONT_ASSIGN	2234	1	1	100.00
CONT_ASSIGN	2236	1	1	100.00
CONT_ASSIGN	2237	1	1	100.00
CONT_ASSIGN	2238	1	1	100.00
CONT_ASSIGN	2240	1	1	100.00
CONT_ASSIGN	2241	1	1	100.00
CONT_ASSIGN	2242	1	1	100.00
CONT_ASSIGN	2244	1	1	100.00
CONT_ASSIGN	2245	1	1	100.00
CONT_ASSIGN	2246	1	1	100.00
CONT_ASSIGN	2248	1	1	100.00
CONT_ASSIGN	2249	1	1	100.00
CONT_ASSIGN	2250	1	1	100.00
CONT_ASSIGN	2252	1	1	100.00
CONT_ASSIGN	2253	1	1	100.00
CONT_ASSIGN	2254	1	1	100.00
CONT_ASSIGN	2256	1	1	100.00
ALWAYS	2260	60	60	100.00
ALWAYS	2324	77	77	100.00
CONT_ASSIGN	2589	0	0
CONT_ASSIGN	2597	1	1	100.00
CONT_ASSIGN	2598	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
82	1	1
100	1	1
101	1	1
103	1	1
104	1	1
130	1	1
136	1	1
137	1	1
			MISSING_ELSE
167	1	1
168	1	1
525	1	1
540	1	1
556	1	1
572	1	1
578	1	1
592	1	1
598	1	1
613	1	1
629	1	1
645	1	1
661	1	1
677	1	1
693	1	1
699	1	1
714	1	1
730	1	1
746	1	1
762	1	1
843	1	1
857	1	1
864	1	1
878	1	1
885	1	1
899	1	1
906	1	1
920	1	1
927	1	1
941	1	1
948	1	1
962	1	1
969	1	1
983	1	1
990	1	1
1004	1	1
1011	1	1
1025	1	1
1032	1	1
1046	1	1
1053	1	1
1067	1	1
1074	1	1
1088	1	1
1095	1	1
1109	1	1
1116	1	1
1130	1	1
1137	1	1
1151	1	1
1158	1	1
1172	1	1
1179	1	1
1193	1	1
1200	1	1
1214	1	1
1221	1	1
1235	1	1
1242	1	1
1256	1	1
1263	1	1
1277	1	1
1284	1	1
1298	1	1
1305	1	1
1319	1	1
1326	1	1
1340	1	1
1347	1	1
1361	1	1
1368	1	1
1382	1	1
1389	1	1
1403	1	1
1410	1	1
1424	1	1
1431	1	1
1445	1	1
1452	1	1
1466	1	1
1473	1	1
1487	1	1
1494	1	1
1508	1	1
1515	1	1
1529	1	1
1536	1	1
1550	1	1
1557	1	1
1571	1	1
1578	1	1
1592	1	1
1599	1	1
1613	1	1
1620	1	1
1634	1	1
1641	1	1
1655	1	1
1662	1	1
1676	1	1
1683	1	1
1697	1	1
1704	1	1
1718	1	1
1725	1	1
1739	1	1
1746	1	1
1760	1	1
1767	1	1
1781	1	1
1788	1	1
1802	1	1
1809	1	1
1823	1	1
1830	1	1
1844	1	1
1851	1	1
1865	1	1
1871	1	1
1885	1	1
1891	1	1
1905	1	1
1911	1	1
1912	1	1
1913	1	1
1914	1	1
1915	1	1
1916	1	1
1917	1	1
1918	1	1
1919	1	1
1920	1	1
1921	1	1
1922	1	1
1923	1	1
1924	1	1
1925	1	1
1926	1	1
1927	1	1
1928	1	1
1929	1	1
1930	1	1
1931	1	1
1932	1	1
1933	1	1
1934	1	1
1935	1	1
1936	1	1
1937	1	1
1938	1	1
1939	1	1
1940	1	1
1941	1	1
1942	1	1
1943	1	1
1944	1	1
1945	1	1
1946	1	1
1947	1	1
1948	1	1
1949	1	1
1950	1	1
1951	1	1
1952	1	1
1953	1	1
1954	1	1
1955	1	1
1956	1	1
1957	1	1
1958	1	1
1959	1	1
1960	1	1
1961	1	1
1962	1	1
1963	1	1
1964	1	1
1965	1	1
1966	1	1
1967	1	1
1968	1	1
1969	1	1
1970	1	1
1973	1	1
1977	1	1
2040	1	1
2042	1	1
2044	1	1
2045	1	1
2047	1	1
2049	1	1
2051	1	1
2052	1	1
2054	1	1
2056	1	1
2058	1	1
2059	1	1
2061	1	1
2062	1	1
2063	1	1
2065	1	1
2067	1	1
2069	1	1
2071	1	1
2073	1	1
2075	1	1
2076	1	1
2078	1	1
2080	1	1
2082	1	1
2084	1	1
2085	1	1
2086	1	1
2088	1	1
2089	1	1
2091	1	1
2092	1	1
2094	1	1
2095	1	1
2097	1	1
2098	1	1
2100	1	1
2101	1	1
2103	1	1
2104	1	1
2106	1	1
2107	1	1
2109	1	1
2110	1	1
2112	1	1
2113	1	1
2115	1	1
2116	1	1
2118	1	1
2119	1	1
2121	1	1
2122	1	1
2124	1	1
2125	1	1
2127	1	1
2128	1	1
2130	1	1
2131	1	1
2133	1	1
2134	1	1
2136	1	1
2137	1	1
2139	1	1
2140	1	1
2142	1	1
2143	1	1
2145	1	1
2146	1	1
2148	1	1
2149	1	1
2151	1	1
2152	1	1
2154	1	1
2155	1	1
2157	1	1
2158	1	1
2160	1	1
2161	1	1
2163	1	1
2164	1	1
2166	1	1
2167	1	1
2169	1	1
2170	1	1
2172	1	1
2173	1	1
2175	1	1
2176	1	1
2178	1	1
2179	1	1
2181	1	1
2182	1	1
2184	1	1
2185	1	1
2186	1	1
2188	1	1
2189	1	1
2190	1	1
2192	1	1
2193	1	1
2194	1	1
2196	1	1
2197	1	1
2198	1	1
2200	1	1
2201	1	1
2202	1	1
2204	1	1
2205	1	1
2206	1	1
2208	1	1
2209	1	1
2210	1	1
2212	1	1
2213	1	1
2214	1	1
2216	1	1
2217	1	1
2218	1	1
2220	1	1
2221	1	1
2222	1	1
2224	1	1
2225	1	1
2226	1	1
2228	1	1
2229	1	1
2230	1	1
2232	1	1
2233	1	1
2234	1	1
2236	1	1
2237	1	1
2238	1	1
2240	1	1
2241	1	1
2242	1	1
2244	1	1
2245	1	1
2246	1	1
2248	1	1
2249	1	1
2250	1	1
2252	1	1
2253	1	1
2254	1	1
2256	1	1
2260	1	1
2261	1	1
2262	1	1
2263	1	1
2264	1	1
2265	1	1
2266	1	1
2267	1	1
2268	1	1
2269	1	1
2270	1	1
2271	1	1
2272	1	1
2273	1	1
2274	1	1
2275	1	1
2276	1	1
2277	1	1
2278	1	1
2279	1	1
2280	1	1
2281	1	1
2282	1	1
2283	1	1
2284	1	1
2285	1	1
2286	1	1
2287	1	1
2288	1	1
2289	1	1
2290	1	1
2291	1	1
2292	1	1
2293	1	1
2294	1	1
2295	1	1
2296	1	1
2297	1	1
2298	1	1
2299	1	1
2300	1	1
2301	1	1
2302	1	1
2303	1	1
2304	1	1
2305	1	1
2306	1	1
2307	1	1
2308	1	1
2309	1	1
2310	1	1
2311	1	1
2312	1	1
2313	1	1
2314	1	1
2315	1	1
2316	1	1
2317	1	1
2318	1	1
2319	1	1
2324	1	1
2325	1	1
2327	1	1
2328	1	1
2329	1	1
2333	1	1
2334	1	1
2335	1	1
2339	1	1
2340	1	1
2341	1	1
2345	1	1
2349	1	1
2350	1	1
2351	1	1
2352	1	1
2353	1	1
2354	1	1
2358	1	1
2359	1	1
2360	1	1
2361	1	1
2365	1	1
2366	1	1
2367	1	1
2371	1	1
2375	1	1
2379	1	1
2383	1	1
2387	1	1
2391	1	1
2395	1	1
2399	1	1
2403	1	1
2407	1	1
2411	1	1
2415	1	1
2419	1	1
2423	1	1
2427	1	1
2431	1	1
2435	1	1
2439	1	1
2443	1	1
2447	1	1
2451	1	1
2455	1	1
2459	1	1
2463	1	1
2467	1	1
2471	1	1
2475	1	1
2479	1	1
2483	1	1
2487	1	1
2491	1	1
2495	1	1
2499	1	1
2503	1	1
2507	1	1
2511	1	1
2515	1	1
2519	1	1
2523	1	1
2527	1	1
2531	1	1
2535	1	1
2539	1	1
2543	1	1
2547	1	1
2551	1	1
2555	1	1
2559	1	1
2563	1	1
2567	1	1
2571	1	1
2575	1	1
2589		unreachable
2597	1	1
2598	1	1

---

Cond Coverage for Module : hmac_reg_top

	Total	Covered	Percent
Conditions	687	667	97.09
Logical	687	667	97.09
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
63-2095	99.53
2098-2254	93.08

---

Branch Coverage for Module : hmac_reg_top

	Line No.	Total	Covered	Percent
Branches		69	69	100.00
TERNARY	1973	2	2	100.00
IF	73	3	3	100.00
TERNARY	130	2	2	100.00
IF	136	2	2	100.00
CASE	2325	60	60	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1973	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	73	if ((!rst_ni))
-2-:	75	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T33,T34,T35
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	((tl_i.a_address[(AW - 1):0] inside {[4096:8191]})) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	136	if (intg_err)

Branches:

-1-	Status	Tests
1	Covered	T59,T60,T61
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	2325	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : hmac_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	437432115	54879929	0	0
reAfterRv	437432115	54879929	0	0
rePulse	437432115	30372983	0	0
wePulse	437432115	24506946	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	54879929	0	0
T1	183150	659942	0	0
T2	476697	28232	0	0
T3	610490	53364	0	0
T4	227150	7920	0	0
T17	487340	56584	0	0
T19	54535	15360	0	0
T22	1335	17	0	0
T23	924	8	0	0
T31	19257	3885	0	0
T32	35227	9225	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	54879929	0	0
T1	183150	659942	0	0
T2	476697	28232	0	0
T3	610490	53364	0	0
T4	227150	7920	0	0
T17	487340	56584	0	0
T19	54535	15360	0	0
T22	1335	17	0	0
T23	924	8	0	0
T31	19257	3885	0	0
T32	35227	9225	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	30372983	0	0
T1	183150	358181	0	0
T2	476697	18486	0	0
T3	610490	35022	0	0
T4	227150	4576	0	0
T17	487340	31018	0	0
T19	54535	14499	0	0
T22	1335	1	0	0
T23	924	1	0	0
T31	19257	2104	0	0
T32	35227	8504	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	24506946	0	0
T1	183150	301761	0	0
T2	476697	9746	0	0
T3	610490	18342	0	0
T4	227150	3344	0	0
T17	487340	25566	0	0
T19	54535	861	0	0
T22	1335	16	0	0
T23	924	7	0	0
T31	19257	1781	0	0
T32	35227	721	0	0