Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	437432115	3184610	0	0
intr_enable_rd_A	437432115	1870	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	3184610	0	0
T5	750904	32165	0	0
T6	190786	43391	0	0
T7	0	97699	0	0
T8	0	246738	0	0
T9	0	183739	0	0
T10	0	432623	0	0
T11	0	83963	0	0
T14	161167	0	0	0
T20	9552	0	0	0
T53	139045	0	0	0
T65	0	38276	0	0
T66	0	24185	0	0
T67	0	93418	0	0
T68	1761	0	0	0
T69	277370	0	0	0
T70	59529	0	0	0
T71	553107	0	0	0
T72	772331	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	437432115	1870	0	0
T30	166366	57	0	0
T55	181005	0	0	0
T73	0	27	0	0
T74	0	24	0	0
T75	0	31	0	0
T76	0	42	0	0
T77	0	23	0	0
T78	0	16	0	0
T79	0	34	0	0
T80	0	42	0	0
T81	0	9	0	0
T82	435797	0	0	0
T83	30209	0	0	0
T84	129815	0	0	0
T85	1330	0	0	0
T86	245121	0	0	0
T87	86103	0	0	0
T88	832	0	0	0
T89	9765	0	0	0