Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14678135	1			T1	14		T2	94		T3	17086
all_values[1]	14678135	1			T1	14		T2	94		T3	17086
all_values[2]	14678135	1			T1	14		T2	94		T3	17086

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

120446

1

T3

399

T6

585

T4

15

auto[1]

43913959

1

T1

42

T2

282

T3

50859

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

41429949

1

T1

41

T2

256

T3

42951

auto[1]

2604456

1

T1

1

T2

26

T3

8307

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	38076	1			T3	397		T9	8		T13	9
all_values[0]	auto[0]	auto[1]	471	1			T3	2		T9	2		T13	8
all_values[0]	auto[1]	auto[0]	14590145	1			T1	13		T2	90		T3	16678
all_values[0]	auto[1]	auto[1]	49443	1			T1	1		T2	4		T3	9
all_values[1]	auto[0]	auto[0]	40803	1			T4	15		T5	265		T13	1834
all_values[1]	auto[0]	auto[1]	269	1			T13	10		T16	5		T17	2
all_values[1]	auto[1]	auto[0]	14636465	1			T1	14		T2	94		T3	17086
all_values[1]	auto[1]	auto[1]	598	1			T13	23		T16	5		T103	3
all_values[2]	auto[0]	auto[0]	29081	1			T6	585		T5	265		T8	653
all_values[2]	auto[0]	auto[1]	11746	1			T13	10		T44	273		T16	5
all_values[2]	auto[1]	auto[0]	12095379	1			T1	14		T2	72		T3	8790
all_values[2]	auto[1]	auto[1]	2541929	1			T2	22		T3	8296		T13	35177