Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	27	0	27	100.00
Crosses	168	0	168	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	17	0	17	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	136	0	136	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6931420

1

T1

12

T2

32

T3

3132

auto[1]

2900936

1

T3

2756

T6

2800

T7

4530

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2918202

1

T3

2242

T6

2878

T7

4335

auto[1]

6914154

1

T1

12

T2

32

T3

3646

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6155277

1

T3

2086

T6

1749

T7

4975

auto[1]

3677079

1

T1

12

T2

32

T3

3802

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	17	0	17	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6169801	1			T1	11		T2	23		T3	5653
fifo_depth[1]	472419	1			T1	1		T2	3		T3	147
fifo_depth[2]	397454	1			T2	2		T3	57		T6	105
fifo_depth[3]	333068	1			T2	3		T3	20		T6	30
fifo_depth[4]	294234	1			T3	9		T6	5		T7	11
fifo_depth[5]	266146	1			T2	1		T3	2		T6	4
fifo_depth[6]	253457	1			T4	308		T5	396		T8	388
fifo_depth[7]	223014	1			T4	293		T5	358		T8	357
fifo_depth[8]	203116	1			T4	274		T5	309		T8	283
fifo_depth[9]	139978	1			T4	214		T5	199		T8	225
fifo_depth[10]	107822	1			T4	143		T5	142		T8	169
fifo_depth[11]	67352	1			T4	74		T5	85		T8	106
fifo_depth[12]	68686	1			T4	38		T5	47		T8	53
fifo_depth[13]	34688	1			T4	16		T5	25		T8	22
fifo_depth[14]	44963	1			T4	10		T5	8		T8	6
fifo_depth[15]	28466	1			T4	8		T5	8		T8	6
fifo_depth[16]	97684	1			T4	1		T5	3		T13	1139

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3789082

1

T1

1

T2

9

T3

235

auto[1]

6043274

1

T1

11

T2

23

T3

5653

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9705829

1

T1

12

T2

32

T3

5888

auto[1]

126527

1

T20

3

T13

575

T21

1

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

248068

1

T3

39

T6

15

T7

60

auto[0]

auto[0]

auto[0]

auto[1]

267439

1

T3

7

T7

137

T5

919

auto[0]

auto[0]

auto[1]

auto[0]

1013650

1

T6

51

T7

104

T4

347

auto[0]

auto[0]

auto[1]

auto[1]

270358

1

T3

25

T6

63

T7

48

auto[0]

auto[1]

auto[0]

auto[0]

485745

1

T3

52

T6

109

T7

122

auto[0]

auto[1]

auto[0]

auto[1]

510458

1

T6

108

T7

2

T5

436

auto[0]

auto[1]

auto[1]

auto[0]

522043

1

T1

1

T2

9

T7

129

auto[0]

auto[1]

auto[1]

auto[1]

471321

1

T3

112

T6

64

T7

138

auto[1]

auto[0]

auto[0]

auto[0]

266531

1

T3

491

T6

285

T7

761

auto[1]

auto[0]

auto[0]

auto[1]

283694

1

T3

274

T7

1953

T5

531

auto[1]

auto[0]

auto[1]

auto[0]

3529443

1

T6

603

T7

1264

T4

182

auto[1]

auto[0]

auto[1]

auto[1]

276094

1

T3

1250

T6

732

T7

648

auto[1]

auto[1]

auto[0]

auto[0]

437333

1

T3

978

T6

1189

T7

1293

auto[1]

auto[1]

auto[0]

auto[1]

418934

1

T3

401

T6

1172

T7

7

auto[1]

auto[1]

auto[1]

auto[0]

428607

1

T1

11

T2

23

T3

1572

auto[1]

auto[1]

auto[1]

auto[1]

402638

1

T3

687

T6

661

T7

1597

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

501965

1

T3

530

T6

300

T7

821

auto[0]

auto[0]

auto[0]

auto[1]

539051

1

T3

281

T7

2090

T5

1450

auto[0]

auto[0]

auto[1]

auto[0]

4526684

1

T6

654

T7

1368

T4

529

auto[0]

auto[0]

auto[1]

auto[1]

527075

1

T3

1275

T6

795

T7

696

auto[0]

auto[1]

auto[0]

auto[0]

904506

1

T3

1030

T6

1298

T7

1415

auto[0]

auto[1]

auto[0]

auto[1]

911602

1

T3

401

T6

1280

T7

9

auto[0]

auto[1]

auto[1]

auto[0]

935903

1

T1

12

T2

32

T3

1572

auto[0]

auto[1]

auto[1]

auto[1]

859043

1

T3

799

T6

725

T7

1735

auto[1]

auto[0]

auto[0]

auto[0]

12634

1

T13

1

T26

73

T16

162

auto[1]

auto[0]

auto[0]

auto[1]

12082

1

T20

2

T13

2

T26

646

auto[1]

auto[0]

auto[1]

auto[0]

16409

1

T13

46

T21

1

T26

244

auto[1]

auto[0]

auto[1]

auto[1]

19377

1

T13

7

T26

155

T16

394

auto[1]

auto[1]

auto[0]

auto[0]

18572

1

T20

1

T13

14

T26

614

auto[1]

auto[1]

auto[0]

auto[1]

17790

1

T13

505

T26

1899

T16

570

auto[1]

auto[1]

auto[1]

auto[0]

14747

1

T26

314

T16

333

T29

58

auto[1]

auto[1]

auto[1]

auto[1]

14916

1

T26

262

T16

627

T103

347

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	136	0	136	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	279165	1			T3	491		T6	285		T7	761
fifo_depth[0]	auto[0]	auto[0]	auto[1]	295776	1			T3	274		T7	1953		T5	531
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3545852	1			T6	603		T7	1264		T4	182
fifo_depth[0]	auto[0]	auto[1]	auto[1]	295471	1			T3	1250		T6	732		T7	648
fifo_depth[0]	auto[1]	auto[0]	auto[0]	455905	1			T3	978		T6	1189		T7	1293
fifo_depth[0]	auto[1]	auto[0]	auto[1]	436724	1			T3	401		T6	1172		T7	7
fifo_depth[0]	auto[1]	auto[1]	auto[0]	443354	1			T1	11		T2	23		T3	1572
fifo_depth[0]	auto[1]	auto[1]	auto[1]	417554	1			T3	687		T6	661		T7	1597
fifo_depth[1]	auto[0]	auto[0]	auto[0]	20825	1			T3	22		T6	12		T7	44
fifo_depth[1]	auto[0]	auto[0]	auto[1]	23454	1			T3	7		T7	93		T5	101
fifo_depth[1]	auto[0]	auto[1]	auto[0]	211175	1			T6	31		T7	63		T4	36
fifo_depth[1]	auto[0]	auto[1]	auto[1]	22864	1			T3	25		T6	47		T7	33
fifo_depth[1]	auto[1]	auto[0]	auto[0]	47941	1			T3	38		T6	73		T7	73
fifo_depth[1]	auto[1]	auto[0]	auto[1]	49739	1			T6	61		T7	1		T5	37
fifo_depth[1]	auto[1]	auto[1]	auto[0]	50570	1			T1	1		T2	3		T7	81
fifo_depth[1]	auto[1]	auto[1]	auto[1]	45851	1			T3	55		T6	42		T7	80
fifo_depth[2]	auto[0]	auto[0]	auto[0]	17942	1			T3	14		T6	2		T7	11
fifo_depth[2]	auto[0]	auto[0]	auto[1]	20348	1			T7	34		T5	109		T35	120
fifo_depth[2]	auto[0]	auto[1]	auto[0]	161224	1			T6	13		T7	28		T4	44
fifo_depth[2]	auto[0]	auto[1]	auto[1]	20142	1			T6	13		T7	12		T4	41
fifo_depth[2]	auto[1]	auto[0]	auto[0]	43789	1			T3	11		T6	29		T7	31
fifo_depth[2]	auto[1]	auto[0]	auto[1]	45522	1			T6	29		T7	1		T5	52
fifo_depth[2]	auto[1]	auto[1]	auto[0]	46482	1			T2	2		T7	36		T5	69
fifo_depth[2]	auto[1]	auto[1]	auto[1]	42005	1			T3	32		T6	19		T7	51
fifo_depth[3]	auto[0]	auto[0]	auto[0]	14433	1			T3	3		T6	1		T7	4
fifo_depth[3]	auto[0]	auto[0]	auto[1]	17006	1			T7	8		T5	101		T35	128
fifo_depth[3]	auto[0]	auto[1]	auto[0]	123273	1			T6	5		T7	9		T4	36
fifo_depth[3]	auto[0]	auto[1]	auto[1]	16542	1			T6	3		T7	3		T4	34
fifo_depth[3]	auto[1]	auto[0]	auto[0]	39449	1			T3	2		T6	5		T7	15
fifo_depth[3]	auto[1]	auto[0]	auto[1]	41775	1			T6	13		T5	53		T8	93
fifo_depth[3]	auto[1]	auto[1]	auto[0]	42645	1			T2	3		T7	8		T5	72
fifo_depth[3]	auto[1]	auto[1]	auto[1]	37945	1			T3	15		T6	3		T7	7
fifo_depth[4]	auto[0]	auto[0]	auto[0]	14150	1			T7	1		T4	130		T35	2
fifo_depth[4]	auto[0]	auto[0]	auto[1]	16654	1			T7	1		T5	103		T35	122
fifo_depth[4]	auto[0]	auto[1]	auto[0]	91496	1			T6	2		T7	3		T4	35
fifo_depth[4]	auto[0]	auto[1]	auto[1]	16091	1			T4	47		T5	63		T9	5
fifo_depth[4]	auto[1]	auto[0]	auto[0]	37494	1			T3	1		T7	3		T4	61
fifo_depth[4]	auto[1]	auto[0]	auto[1]	40529	1			T6	3		T5	39		T8	100
fifo_depth[4]	auto[1]	auto[1]	auto[0]	40768	1			T7	3		T5	70		T8	186
fifo_depth[4]	auto[1]	auto[1]	auto[1]	37052	1			T3	8		T4	85		T5	53
fifo_depth[5]	auto[0]	auto[0]	auto[0]	12399	1			T4	106		T35	1		T13	143
fifo_depth[5]	auto[0]	auto[0]	auto[1]	14841	1			T7	1		T5	114		T35	147
fifo_depth[5]	auto[0]	auto[1]	auto[0]	76016	1			T7	1		T4	31		T5	32
fifo_depth[5]	auto[0]	auto[1]	auto[1]	14466	1			T4	30		T5	71		T9	1
fifo_depth[5]	auto[1]	auto[0]	auto[0]	35732	1			T6	2		T4	65		T5	20
fifo_depth[5]	auto[1]	auto[0]	auto[1]	38397	1			T6	2		T5	46		T8	101
fifo_depth[5]	auto[1]	auto[1]	auto[0]	39912	1			T2	1		T7	1		T5	66
fifo_depth[5]	auto[1]	auto[1]	auto[1]	34383	1			T3	2		T4	83		T5	52
fifo_depth[6]	auto[0]	auto[0]	auto[0]	12659	1			T4	114		T35	1		T13	129
fifo_depth[6]	auto[0]	auto[0]	auto[1]	14937	1			T5	102		T35	136		T13	137
fifo_depth[6]	auto[0]	auto[1]	auto[0]	65752	1			T4	42		T5	33		T35	60
fifo_depth[6]	auto[0]	auto[1]	auto[1]	14333	1			T4	24		T5	74		T9	3
fifo_depth[6]	auto[1]	auto[0]	auto[0]	34740	1			T4	47		T5	27		T8	61
fifo_depth[6]	auto[1]	auto[0]	auto[1]	37969	1			T5	36		T8	112		T35	28
fifo_depth[6]	auto[1]	auto[1]	auto[0]	38582	1			T5	64		T8	215		T9	1
fifo_depth[6]	auto[1]	auto[1]	auto[1]	34485	1			T4	81		T5	60		T35	181
fifo_depth[7]	auto[0]	auto[0]	auto[0]	11227	1			T4	95		T35	1		T13	142
fifo_depth[7]	auto[0]	auto[0]	auto[1]	13505	1			T5	84		T35	114		T13	127
fifo_depth[7]	auto[0]	auto[1]	auto[0]	52398	1			T4	31		T5	30		T35	52
fifo_depth[7]	auto[0]	auto[1]	auto[1]	12781	1			T4	27		T5	60		T35	25
fifo_depth[7]	auto[1]	auto[0]	auto[0]	31839	1			T4	51		T5	16		T8	56
fifo_depth[7]	auto[1]	auto[0]	auto[1]	34806	1			T5	49		T8	114		T35	25
fifo_depth[7]	auto[1]	auto[1]	auto[0]	35494	1			T5	55		T8	187		T35	53
fifo_depth[7]	auto[1]	auto[1]	auto[1]	30964	1			T4	89		T5	64		T35	154
fifo_depth[8]	auto[0]	auto[0]	auto[0]	12029	1			T4	78		T13	124		T53	27
fifo_depth[8]	auto[0]	auto[0]	auto[1]	13233	1			T5	81		T35	88		T13	114
fifo_depth[8]	auto[0]	auto[1]	auto[0]	41882	1			T4	36		T5	21		T35	52
fifo_depth[8]	auto[0]	auto[1]	auto[1]	12578	1			T4	29		T5	55		T35	36
fifo_depth[8]	auto[1]	auto[0]	auto[0]	30041	1			T4	51		T5	11		T8	48
fifo_depth[8]	auto[1]	auto[0]	auto[1]	31386	1			T5	33		T8	77		T35	21
fifo_depth[8]	auto[1]	auto[1]	auto[0]	32616	1			T5	53		T8	158		T35	44
fifo_depth[8]	auto[1]	auto[1]	auto[1]	29351	1			T4	80		T5	55		T35	136
fifo_depth[9]	auto[0]	auto[0]	auto[0]	7925	1			T4	73		T13	84		T53	28
fifo_depth[9]	auto[0]	auto[0]	auto[1]	9297	1			T5	48		T35	79		T13	92
fifo_depth[9]	auto[0]	auto[1]	auto[0]	27244	1			T4	29		T5	9		T35	31
fifo_depth[9]	auto[0]	auto[1]	auto[1]	8500	1			T4	24		T5	38		T35	22
fifo_depth[9]	auto[1]	auto[0]	auto[0]	21062	1			T4	29		T5	18		T8	30
fifo_depth[9]	auto[1]	auto[0]	auto[1]	22503	1			T5	26		T8	66		T35	12
fifo_depth[9]	auto[1]	auto[1]	auto[0]	23118	1			T5	30		T8	129		T35	35
fifo_depth[9]	auto[1]	auto[1]	auto[1]	20329	1			T4	59		T5	30		T35	106
fifo_depth[10]	auto[0]	auto[0]	auto[0]	7051	1			T4	47		T13	67		T53	19
fifo_depth[10]	auto[0]	auto[0]	auto[1]	7641	1			T5	47		T35	44		T13	52
fifo_depth[10]	auto[0]	auto[1]	auto[0]	18523	1			T4	12		T5	6		T35	29
fifo_depth[10]	auto[0]	auto[1]	auto[1]	7335	1			T4	16		T5	26		T35	13
fifo_depth[10]	auto[1]	auto[0]	auto[0]	15094	1			T4	28		T5	6		T8	33
fifo_depth[10]	auto[1]	auto[0]	auto[1]	17080	1			T5	21		T8	44		T35	16
fifo_depth[10]	auto[1]	auto[1]	auto[0]	18264	1			T5	18		T8	92		T35	26
fifo_depth[10]	auto[1]	auto[1]	auto[1]	16834	1			T4	40		T5	18		T35	61
fifo_depth[11]	auto[0]	auto[0]	auto[0]	4734	1			T4	25		T13	27		T53	12
fifo_depth[11]	auto[0]	auto[0]	auto[1]	5049	1			T5	15		T35	21		T13	35
fifo_depth[11]	auto[0]	auto[1]	auto[0]	11164	1			T4	8		T5	2		T35	10
fifo_depth[11]	auto[0]	auto[1]	auto[1]	4800	1			T4	5		T5	15		T35	9
fifo_depth[11]	auto[1]	auto[0]	auto[0]	9660	1			T4	17		T5	3		T8	19
fifo_depth[11]	auto[1]	auto[0]	auto[1]	10813	1			T5	19		T8	36		T35	7
fifo_depth[11]	auto[1]	auto[1]	auto[0]	11423	1			T5	15		T8	51		T35	14
fifo_depth[11]	auto[1]	auto[1]	auto[1]	9709	1			T4	19		T5	16		T35	51
fifo_depth[12]	auto[0]	auto[0]	auto[0]	6670	1			T4	9		T13	20		T53	5
fifo_depth[12]	auto[0]	auto[0]	auto[1]	5742	1			T5	11		T35	12		T13	18
fifo_depth[12]	auto[0]	auto[1]	auto[0]	10124	1			T4	5		T5	3		T35	5
fifo_depth[12]	auto[0]	auto[1]	auto[1]	5952	1			T4	4		T5	4		T35	7
fifo_depth[12]	auto[1]	auto[0]	auto[0]	9923	1			T4	10		T8	13		T35	5
fifo_depth[12]	auto[1]	auto[0]	auto[1]	9331	1			T5	12		T8	11		T35	2
fifo_depth[12]	auto[1]	auto[1]	auto[0]	11196	1			T5	10		T8	29		T35	7
fifo_depth[12]	auto[1]	auto[1]	auto[1]	9748	1			T4	10		T5	7		T35	25
fifo_depth[13]	auto[0]	auto[0]	auto[0]	3571	1			T4	2		T13	9		T18	5
fifo_depth[13]	auto[0]	auto[0]	auto[1]	3430	1			T5	2		T35	11		T13	7
fifo_depth[13]	auto[0]	auto[1]	auto[0]	4388	1			T4	2		T5	4		T35	3
fifo_depth[13]	auto[0]	auto[1]	auto[1]	3241	1			T4	1		T5	4		T35	2
fifo_depth[13]	auto[1]	auto[0]	auto[0]	4237	1			T4	3		T5	1		T8	1
fifo_depth[13]	auto[1]	auto[0]	auto[1]	5007	1			T5	8		T8	10		T35	1
fifo_depth[13]	auto[1]	auto[1]	auto[0]	5757	1			T5	3		T8	11		T35	1
fifo_depth[13]	auto[1]	auto[1]	auto[1]	5057	1			T4	8		T5	3		T35	10
fifo_depth[14]	auto[0]	auto[0]	auto[0]	5358	1			T4	1		T13	3		T26	49
fifo_depth[14]	auto[0]	auto[0]	auto[1]	4867	1			T5	1		T35	3		T13	5
fifo_depth[14]	auto[0]	auto[1]	auto[0]	4793	1			T5	1		T13	123		T26	114
fifo_depth[14]	auto[0]	auto[1]	auto[1]	4764	1			T4	2		T5	1		T13	88
fifo_depth[14]	auto[1]	auto[0]	auto[0]	5087	1			T4	3		T5	1		T8	1
fifo_depth[14]	auto[1]	auto[0]	auto[1]	5678	1			T5	2		T8	2		T13	29
fifo_depth[14]	auto[1]	auto[1]	auto[0]	7127	1			T8	3		T13	33		T67	1
fifo_depth[14]	auto[1]	auto[1]	auto[1]	7289	1			T4	4		T5	2		T35	5
fifo_depth[15]	auto[0]	auto[0]	auto[0]	3385	1			T4	2		T53	1		T26	81
fifo_depth[15]	auto[0]	auto[0]	auto[1]	3517	1			T13	2		T26	257		T16	58
fifo_depth[15]	auto[0]	auto[1]	auto[0]	3158	1			T13	25		T53	1		T26	101
fifo_depth[15]	auto[0]	auto[1]	auto[1]	2987	1			T5	1		T13	81		T26	211
fifo_depth[15]	auto[1]	auto[0]	auto[0]	3278	1			T4	4		T8	1		T13	20
fifo_depth[15]	auto[1]	auto[0]	auto[1]	3774	1			T5	1		T8	2		T13	6
fifo_depth[15]	auto[1]	auto[1]	auto[0]	4333	1			T5	4		T8	3		T13	13
fifo_depth[15]	auto[1]	auto[1]	auto[1]	4034	1			T4	2		T5	2		T35	2
fifo_depth[16]	auto[0]	auto[0]	auto[0]	10382	1			T26	326		T16	76		T103	300
fifo_depth[16]	auto[0]	auto[0]	auto[1]	11182	1			T26	623		T16	227		T103	160
fifo_depth[16]	auto[0]	auto[1]	auto[0]	15820	1			T13	722		T26	1202		T111	2
fifo_depth[16]	auto[0]	auto[1]	auto[1]	9685	1			T5	1		T13	326		T26	228
fifo_depth[16]	auto[1]	auto[0]	auto[0]	14486	1			T13	46		T26	60		T16	53
fifo_depth[16]	auto[1]	auto[0]	auto[1]	12562	1			T5	2		T13	38		T26	112
fifo_depth[16]	auto[1]	auto[1]	auto[0]	10017	1			T13	3		T26	947		T112	2
fifo_depth[16]	auto[1]	auto[1]	auto[1]	13550	1			T4	1		T13	4		T18	1