Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	14678135	1			T1	14		T2	94		T3	17086
all_pins[1]	14678135	1			T1	14		T2	94		T3	17086
all_pins[2]	14678135	1			T1	14		T2	94		T3	17086

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	41441035	1			T1	41		T2	256		T3	42953
values[0x1]	2593370	1			T1	1		T2	26		T3	8305
transitions[0x0=>0x1]	2593165	1			T1	1		T2	26		T3	8305
transitions[0x1=>0x0]	2593191	1			T1	1		T2	26		T3	8305

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	14627323	1			T1	13		T2	90		T3	17077
all_pins[0]	values[0x1]	50812	1			T1	1		T2	4		T3	9
all_pins[0]	transitions[0x0=>0x1]	50727	1			T1	1		T2	4		T3	9
all_pins[0]	transitions[0x1=>0x0]	2541870	1			T2	22		T3	8296		T13	35177
all_pins[1]	values[0x0]	14677506	1			T1	14		T2	94		T3	17086
all_pins[1]	values[0x1]	629	1			T13	23		T26	2		T16	6
all_pins[1]	transitions[0x0=>0x1]	565	1			T13	21		T26	2		T16	6
all_pins[1]	transitions[0x1=>0x0]	50748	1			T1	1		T2	4		T3	9
all_pins[2]	values[0x0]	12136206	1			T1	14		T2	72		T3	8790
all_pins[2]	values[0x1]	2541929	1			T2	22		T3	8296		T13	35177
all_pins[2]	transitions[0x0=>0x1]	2541873	1			T2	22		T3	8296		T13	35176
all_pins[2]	transitions[0x1=>0x0]	573	1			T13	22		T26	2		T16	5