Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1098 1 T13 28 T16 24 T17 20
all_values[1] 1098 1 T13 28 T16 24 T17 20
all_values[2] 1098 1 T13 28 T16 24 T17 20


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1703 1 T13 47 T16 35 T17 31
auto[1] 1591 1 T13 37 T16 37 T17 29


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1173 1 T13 26 T16 29 T17 23
auto[1] 2121 1 T13 58 T16 43 T17 37


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1866 1 T13 45 T16 41 T17 37
auto[1] 1428 1 T13 39 T16 31 T17 23


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 219 1 T13 6 T16 2 T17 3
all_values[0] auto[0] auto[0] auto[1] 109 1 T13 3 T16 2 T17 4
all_values[0] auto[0] auto[1] auto[0] 207 1 T13 6 T16 7 T17 4
all_values[0] auto[0] auto[1] auto[1] 110 1 T13 2 T16 2 T17 3
all_values[0] auto[1] auto[0] auto[1] 225 1 T13 5 T16 8 T17 5
all_values[0] auto[1] auto[1] auto[1] 228 1 T13 6 T16 3 T17 1
all_values[1] auto[0] auto[0] auto[0] 167 1 T13 3 T16 6 T17 4
all_values[1] auto[0] auto[0] auto[1] 134 1 T13 5 T16 2 T17 1
all_values[1] auto[0] auto[1] auto[0] 146 1 T13 2 T16 6 T17 2
all_values[1] auto[0] auto[1] auto[1] 143 1 T13 3 T16 2 T17 6
all_values[1] auto[1] auto[0] auto[1] 273 1 T13 10 T16 4 T17 5
all_values[1] auto[1] auto[1] auto[1] 235 1 T13 5 T16 4 T17 2
all_values[2] auto[0] auto[0] auto[0] 229 1 T13 3 T16 4 T17 3
all_values[2] auto[0] auto[0] auto[1] 93 1 T13 3 T16 2 T38 1
all_values[2] auto[0] auto[1] auto[0] 205 1 T13 6 T16 4 T17 7
all_values[2] auto[0] auto[1] auto[1] 104 1 T13 3 T16 2 T11 7
all_values[2] auto[1] auto[0] auto[1] 254 1 T13 9 T16 5 T17 6
all_values[2] auto[1] auto[1] auto[1] 213 1 T13 4 T16 7 T17 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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