Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.04 92.80 86.09 100.00 73.68 88.15 99.49 69.08


Total test records in report: 735
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T529 /workspace/coverage/default/17.hmac_wipe_secret.759150971 Mar 10 01:39:53 PM PDT 24 Mar 10 01:40:16 PM PDT 24 352537221 ps
T530 /workspace/coverage/default/46.hmac_test_hmac_vectors.4152962901 Mar 10 01:42:23 PM PDT 24 Mar 10 01:42:24 PM PDT 24 33528348 ps
T531 /workspace/coverage/default/45.hmac_long_msg.1453772782 Mar 10 01:42:17 PM PDT 24 Mar 10 01:44:07 PM PDT 24 3493816181 ps
T532 /workspace/coverage/default/24.hmac_long_msg.1922703127 Mar 10 01:40:24 PM PDT 24 Mar 10 01:41:17 PM PDT 24 8075859055 ps
T533 /workspace/coverage/default/25.hmac_test_sha_vectors.1889881635 Mar 10 01:40:29 PM PDT 24 Mar 10 01:47:35 PM PDT 24 14325303712 ps
T534 /workspace/coverage/default/24.hmac_stress_all.2358760610 Mar 10 01:40:23 PM PDT 24 Mar 10 01:43:10 PM PDT 24 26642162099 ps
T535 /workspace/coverage/default/48.hmac_burst_wr.469497182 Mar 10 01:42:31 PM PDT 24 Mar 10 01:42:56 PM PDT 24 5982534438 ps
T536 /workspace/coverage/default/3.hmac_error.3384993337 Mar 10 01:39:19 PM PDT 24 Mar 10 01:39:31 PM PDT 24 3785746322 ps
T537 /workspace/coverage/default/42.hmac_long_msg.533455381 Mar 10 01:41:53 PM PDT 24 Mar 10 01:42:40 PM PDT 24 6364731683 ps
T538 /workspace/coverage/default/8.hmac_datapath_stress.1012119110 Mar 10 01:39:30 PM PDT 24 Mar 10 01:41:12 PM PDT 24 6881310279 ps
T539 /workspace/coverage/default/48.hmac_alert_test.390944153 Mar 10 01:42:37 PM PDT 24 Mar 10 01:42:37 PM PDT 24 15596152 ps
T540 /workspace/coverage/default/30.hmac_stress_all.1400859145 Mar 10 01:40:54 PM PDT 24 Mar 10 01:59:20 PM PDT 24 60245302864 ps
T541 /workspace/coverage/default/44.hmac_test_hmac_vectors.874136055 Mar 10 01:42:11 PM PDT 24 Mar 10 01:42:13 PM PDT 24 28239577 ps
T542 /workspace/coverage/default/39.hmac_smoke.588920666 Mar 10 01:41:39 PM PDT 24 Mar 10 01:41:41 PM PDT 24 346999191 ps
T543 /workspace/coverage/default/21.hmac_stress_all.3446235182 Mar 10 01:40:13 PM PDT 24 Mar 10 01:43:27 PM PDT 24 8075090349 ps
T544 /workspace/coverage/default/30.hmac_error.1381173333 Mar 10 01:40:53 PM PDT 24 Mar 10 01:43:19 PM PDT 24 9849978620 ps
T545 /workspace/coverage/default/1.hmac_alert_test.4019519942 Mar 10 01:39:15 PM PDT 24 Mar 10 01:39:15 PM PDT 24 12606021 ps
T546 /workspace/coverage/default/31.hmac_back_pressure.3302064132 Mar 10 01:40:59 PM PDT 24 Mar 10 01:41:49 PM PDT 24 1258338582 ps
T547 /workspace/coverage/default/15.hmac_test_hmac_vectors.1285016906 Mar 10 01:39:52 PM PDT 24 Mar 10 01:39:53 PM PDT 24 42879280 ps
T548 /workspace/coverage/default/48.hmac_back_pressure.2755741238 Mar 10 01:42:31 PM PDT 24 Mar 10 01:42:34 PM PDT 24 180974439 ps
T549 /workspace/coverage/default/29.hmac_burst_wr.2362479085 Mar 10 01:40:48 PM PDT 24 Mar 10 01:41:44 PM PDT 24 16576854082 ps
T550 /workspace/coverage/default/7.hmac_test_hmac_vectors.2010736944 Mar 10 01:39:29 PM PDT 24 Mar 10 01:39:31 PM PDT 24 55752866 ps
T551 /workspace/coverage/default/45.hmac_error.3266311718 Mar 10 01:42:18 PM PDT 24 Mar 10 01:44:42 PM PDT 24 2547050588 ps
T552 /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2233843643 Mar 10 01:41:05 PM PDT 24 Mar 10 02:13:32 PM PDT 24 70835540810 ps
T553 /workspace/coverage/default/45.hmac_datapath_stress.3636621598 Mar 10 01:42:17 PM PDT 24 Mar 10 01:44:16 PM PDT 24 8210810798 ps
T554 /workspace/coverage/default/38.hmac_burst_wr.2846270070 Mar 10 01:41:34 PM PDT 24 Mar 10 01:41:57 PM PDT 24 3388533214 ps
T555 /workspace/coverage/default/2.hmac_test_sha_vectors.2346294647 Mar 10 01:39:18 PM PDT 24 Mar 10 01:47:14 PM PDT 24 162970150247 ps
T556 /workspace/coverage/default/33.hmac_long_msg.3636743115 Mar 10 01:41:07 PM PDT 24 Mar 10 01:41:20 PM PDT 24 3762321923 ps
T557 /workspace/coverage/default/46.hmac_long_msg.1266943027 Mar 10 01:42:23 PM PDT 24 Mar 10 01:43:22 PM PDT 24 11129567509 ps
T558 /workspace/coverage/default/18.hmac_test_hmac_vectors.3165419602 Mar 10 01:39:57 PM PDT 24 Mar 10 01:39:58 PM PDT 24 51918810 ps
T559 /workspace/coverage/default/49.hmac_stress_all.338853345 Mar 10 01:42:40 PM PDT 24 Mar 10 01:43:00 PM PDT 24 8368897181 ps
T560 /workspace/coverage/default/2.hmac_smoke.2514741081 Mar 10 01:39:13 PM PDT 24 Mar 10 01:39:14 PM PDT 24 48236188 ps
T561 /workspace/coverage/default/32.hmac_stress_all.3525616167 Mar 10 01:41:04 PM PDT 24 Mar 10 01:43:17 PM PDT 24 11925796680 ps
T562 /workspace/coverage/default/14.hmac_error.4227391689 Mar 10 01:39:52 PM PDT 24 Mar 10 01:42:12 PM PDT 24 40150597588 ps
T563 /workspace/coverage/default/32.hmac_datapath_stress.3487199597 Mar 10 01:41:03 PM PDT 24 Mar 10 01:42:59 PM PDT 24 3447434009 ps
T564 /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3869114956 Mar 10 01:44:03 PM PDT 24 Mar 10 02:11:58 PM PDT 24 200426249059 ps
T565 /workspace/coverage/default/34.hmac_long_msg.3428614851 Mar 10 01:41:13 PM PDT 24 Mar 10 01:41:21 PM PDT 24 474349908 ps
T566 /workspace/coverage/default/0.hmac_wipe_secret.3168051887 Mar 10 01:39:13 PM PDT 24 Mar 10 01:39:47 PM PDT 24 32806116255 ps
T567 /workspace/coverage/default/10.hmac_test_sha_vectors.548257589 Mar 10 01:39:35 PM PDT 24 Mar 10 01:45:43 PM PDT 24 14105347764 ps
T568 /workspace/coverage/default/28.hmac_long_msg.1104941641 Mar 10 01:40:44 PM PDT 24 Mar 10 01:40:50 PM PDT 24 1192906275 ps
T78 /workspace/coverage/default/19.hmac_stress_all.1737184137 Mar 10 01:40:00 PM PDT 24 Mar 10 02:09:53 PM PDT 24 119822441874 ps
T569 /workspace/coverage/default/5.hmac_stress_all.1338288847 Mar 10 01:39:20 PM PDT 24 Mar 10 01:53:05 PM PDT 24 15453318084 ps
T570 /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.4107819906 Mar 10 01:43:09 PM PDT 24 Mar 10 01:56:43 PM PDT 24 30222212897 ps
T571 /workspace/coverage/default/39.hmac_test_hmac_vectors.1154980148 Mar 10 01:41:42 PM PDT 24 Mar 10 01:41:44 PM PDT 24 89912935 ps
T572 /workspace/coverage/default/42.hmac_back_pressure.2568307264 Mar 10 01:41:53 PM PDT 24 Mar 10 01:42:29 PM PDT 24 1828120620 ps
T573 /workspace/coverage/default/38.hmac_stress_all.216710099 Mar 10 01:41:39 PM PDT 24 Mar 10 02:05:51 PM PDT 24 213704449245 ps
T574 /workspace/coverage/default/13.hmac_smoke.1161046869 Mar 10 01:39:40 PM PDT 24 Mar 10 01:39:42 PM PDT 24 56028899 ps
T575 /workspace/coverage/default/41.hmac_wipe_secret.4033071416 Mar 10 01:41:52 PM PDT 24 Mar 10 01:41:58 PM PDT 24 1373046697 ps
T576 /workspace/coverage/default/6.hmac_error.31502908 Mar 10 01:39:27 PM PDT 24 Mar 10 01:41:07 PM PDT 24 4295221152 ps
T577 /workspace/coverage/default/6.hmac_alert_test.6253592 Mar 10 01:39:27 PM PDT 24 Mar 10 01:39:28 PM PDT 24 40924458 ps
T578 /workspace/coverage/default/38.hmac_test_hmac_vectors.3295910475 Mar 10 01:41:43 PM PDT 24 Mar 10 01:41:44 PM PDT 24 169712424 ps
T579 /workspace/coverage/default/42.hmac_test_sha_vectors.1444976943 Mar 10 01:41:59 PM PDT 24 Mar 10 01:48:46 PM PDT 24 12839828936 ps
T580 /workspace/coverage/default/41.hmac_datapath_stress.772019751 Mar 10 01:41:48 PM PDT 24 Mar 10 01:42:36 PM PDT 24 2833201493 ps
T581 /workspace/coverage/default/2.hmac_alert_test.267771440 Mar 10 01:39:15 PM PDT 24 Mar 10 01:39:15 PM PDT 24 14024968 ps
T582 /workspace/coverage/default/34.hmac_smoke.965456215 Mar 10 01:41:19 PM PDT 24 Mar 10 01:41:24 PM PDT 24 270442128 ps
T583 /workspace/coverage/default/2.hmac_burst_wr.580979531 Mar 10 01:39:17 PM PDT 24 Mar 10 01:39:58 PM PDT 24 881376677 ps
T584 /workspace/coverage/default/30.hmac_long_msg.2775908258 Mar 10 01:40:54 PM PDT 24 Mar 10 01:42:13 PM PDT 24 18711895185 ps
T585 /workspace/coverage/default/13.hmac_burst_wr.1296322457 Mar 10 01:39:44 PM PDT 24 Mar 10 01:40:47 PM PDT 24 1109158318 ps
T586 /workspace/coverage/default/19.hmac_alert_test.1610106067 Mar 10 01:40:03 PM PDT 24 Mar 10 01:40:04 PM PDT 24 13755513 ps
T587 /workspace/coverage/default/37.hmac_error.2691961210 Mar 10 01:41:27 PM PDT 24 Mar 10 01:44:14 PM PDT 24 47505633151 ps
T588 /workspace/coverage/default/30.hmac_test_sha_vectors.2393146894 Mar 10 01:40:52 PM PDT 24 Mar 10 01:48:04 PM PDT 24 7588638127 ps
T589 /workspace/coverage/default/28.hmac_smoke.1180182939 Mar 10 01:40:41 PM PDT 24 Mar 10 01:40:45 PM PDT 24 589763315 ps
T590 /workspace/coverage/default/8.hmac_alert_test.2499436068 Mar 10 01:39:29 PM PDT 24 Mar 10 01:39:30 PM PDT 24 21631262 ps
T591 /workspace/coverage/default/39.hmac_burst_wr.615480585 Mar 10 01:41:38 PM PDT 24 Mar 10 01:42:01 PM PDT 24 1645432002 ps
T592 /workspace/coverage/default/20.hmac_smoke.1740772272 Mar 10 01:40:07 PM PDT 24 Mar 10 01:40:13 PM PDT 24 8127055311 ps
T593 /workspace/coverage/default/8.hmac_error.1201751781 Mar 10 01:39:30 PM PDT 24 Mar 10 01:40:32 PM PDT 24 2413818424 ps
T594 /workspace/coverage/default/44.hmac_datapath_stress.354841167 Mar 10 01:42:06 PM PDT 24 Mar 10 01:42:36 PM PDT 24 467624191 ps
T595 /workspace/coverage/default/44.hmac_stress_all.2331827869 Mar 10 01:42:13 PM PDT 24 Mar 10 01:47:43 PM PDT 24 6723084717 ps
T596 /workspace/coverage/default/20.hmac_wipe_secret.425061895 Mar 10 01:40:05 PM PDT 24 Mar 10 01:41:00 PM PDT 24 3816404498 ps
T597 /workspace/coverage/default/38.hmac_datapath_stress.2824456196 Mar 10 01:41:34 PM PDT 24 Mar 10 01:42:06 PM PDT 24 1064201206 ps
T57 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2661275989 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:58 PM PDT 24 213787122 ps
T598 /workspace/coverage/cover_reg_top/1.hmac_intr_test.1588909240 Mar 10 12:25:02 PM PDT 24 Mar 10 12:25:03 PM PDT 24 20655851 ps
T58 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1419229912 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:07 PM PDT 24 545013632 ps
T59 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2541539540 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:58 PM PDT 24 130387545 ps
T599 /workspace/coverage/cover_reg_top/43.hmac_intr_test.2774188020 Mar 10 12:25:33 PM PDT 24 Mar 10 12:25:33 PM PDT 24 119562899 ps
T54 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2443923633 Mar 10 12:24:56 PM PDT 24 Mar 10 12:25:01 PM PDT 24 880668535 ps
T55 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1820769157 Mar 10 12:24:56 PM PDT 24 Mar 10 12:25:01 PM PDT 24 133054385 ps
T600 /workspace/coverage/cover_reg_top/22.hmac_intr_test.2455322981 Mar 10 12:25:11 PM PDT 24 Mar 10 12:25:12 PM PDT 24 31835990 ps
T92 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1194950550 Mar 10 12:25:27 PM PDT 24 Mar 10 12:25:28 PM PDT 24 12233592 ps
T601 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1329719175 Mar 10 12:25:10 PM PDT 24 Mar 10 12:25:10 PM PDT 24 27720735 ps
T602 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.749891343 Mar 10 12:24:50 PM PDT 24 Mar 10 12:24:51 PM PDT 24 48081326 ps
T56 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.250676524 Mar 10 12:25:41 PM PDT 24 Mar 10 12:25:43 PM PDT 24 146626105 ps
T603 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3300306812 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:13 PM PDT 24 79831747 ps
T604 /workspace/coverage/cover_reg_top/9.hmac_intr_test.177610303 Mar 10 12:24:50 PM PDT 24 Mar 10 12:24:51 PM PDT 24 16946869 ps
T605 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2897142389 Mar 10 12:25:24 PM PDT 24 Mar 10 12:25:24 PM PDT 24 18519991 ps
T106 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3733055371 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:11 PM PDT 24 864543932 ps
T606 /workspace/coverage/cover_reg_top/27.hmac_intr_test.850469225 Mar 10 12:25:45 PM PDT 24 Mar 10 12:25:46 PM PDT 24 181394593 ps
T607 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4133989215 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:54 PM PDT 24 12354080 ps
T608 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2485462733 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:08 PM PDT 24 61047943 ps
T609 /workspace/coverage/cover_reg_top/29.hmac_intr_test.67447970 Mar 10 12:25:25 PM PDT 24 Mar 10 12:25:25 PM PDT 24 10789930 ps
T610 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3354284289 Mar 10 12:25:10 PM PDT 24 Mar 10 12:25:10 PM PDT 24 51854028 ps
T611 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3219256998 Mar 10 12:25:00 PM PDT 24 Mar 10 12:25:03 PM PDT 24 135267823 ps
T612 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4132164495 Mar 10 12:25:11 PM PDT 24 Mar 10 12:25:13 PM PDT 24 424130111 ps
T613 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3064234566 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:08 PM PDT 24 179284831 ps
T104 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1284418302 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:10 PM PDT 24 276750867 ps
T614 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1016721982 Mar 10 12:24:56 PM PDT 24 Mar 10 12:24:59 PM PDT 24 110954094 ps
T615 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2360822689 Mar 10 12:24:51 PM PDT 24 Mar 10 12:24:51 PM PDT 24 34869166 ps
T110 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.824336807 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:59 PM PDT 24 534524343 ps
T616 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2449928839 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:07 PM PDT 24 30729538 ps
T617 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2252697324 Mar 10 12:25:07 PM PDT 24 Mar 10 12:25:08 PM PDT 24 53757452 ps
T105 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1652813983 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:14 PM PDT 24 1005108290 ps
T618 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3299300667 Mar 10 12:24:56 PM PDT 24 Mar 10 12:24:57 PM PDT 24 12944449 ps
T619 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.294988479 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:12 PM PDT 24 186100336 ps
T620 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3909299839 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:11 PM PDT 24 299322470 ps
T107 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1375362946 Mar 10 12:25:21 PM PDT 24 Mar 10 12:25:25 PM PDT 24 903104156 ps
T621 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3742080871 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:02 PM PDT 24 33090942 ps
T93 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2726974745 Mar 10 12:24:52 PM PDT 24 Mar 10 12:24:58 PM PDT 24 112457286 ps
T94 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4101077051 Mar 10 12:25:03 PM PDT 24 Mar 10 12:25:12 PM PDT 24 2300396291 ps
T95 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1364807425 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:02 PM PDT 24 59817774 ps
T622 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3786294998 Mar 10 12:25:07 PM PDT 24 Mar 10 12:25:08 PM PDT 24 14312154 ps
T623 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.338590141 Mar 10 12:25:00 PM PDT 24 Mar 10 12:25:02 PM PDT 24 152264674 ps
T624 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2319848726 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:06 PM PDT 24 358174043 ps
T625 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3045364241 Mar 10 12:24:50 PM PDT 24 Mar 10 12:24:51 PM PDT 24 91669277 ps
T108 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.65708106 Mar 10 12:24:59 PM PDT 24 Mar 10 12:25:03 PM PDT 24 529710976 ps
T626 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.300467734 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:07 PM PDT 24 120065604 ps
T627 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1231789236 Mar 10 12:25:00 PM PDT 24 Mar 10 12:25:03 PM PDT 24 230366472 ps
T628 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.958609312 Mar 10 12:25:10 PM PDT 24 Mar 10 12:25:12 PM PDT 24 375462146 ps
T109 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3203047292 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:03 PM PDT 24 105054224 ps
T629 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.199463531 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:59 PM PDT 24 614671601 ps
T630 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.630088855 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:10 PM PDT 24 257574343 ps
T631 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3072182442 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:05 PM PDT 24 91240215 ps
T632 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.109341945 Mar 10 12:24:57 PM PDT 24 Mar 10 12:25:00 PM PDT 24 160943080 ps
T633 /workspace/coverage/cover_reg_top/24.hmac_intr_test.1522863011 Mar 10 12:25:47 PM PDT 24 Mar 10 12:25:47 PM PDT 24 27606358 ps
T96 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4206816341 Mar 10 12:24:54 PM PDT 24 Mar 10 12:25:09 PM PDT 24 1275654657 ps
T97 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2113965818 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:10 PM PDT 24 34941482 ps
T634 /workspace/coverage/cover_reg_top/4.hmac_intr_test.3722229584 Mar 10 12:25:21 PM PDT 24 Mar 10 12:25:22 PM PDT 24 12841158 ps
T635 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1753560453 Mar 10 12:25:44 PM PDT 24 Mar 10 12:25:46 PM PDT 24 38818994 ps
T636 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.141836506 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:57 PM PDT 24 124655352 ps
T637 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.644849679 Mar 10 12:24:54 PM PDT 24 Mar 10 12:25:00 PM PDT 24 4450493184 ps
T638 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3404821299 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:56 PM PDT 24 117824239 ps
T639 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2178414243 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:56 PM PDT 24 46284035 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1708926992 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:56 PM PDT 24 96534787 ps
T641 /workspace/coverage/cover_reg_top/35.hmac_intr_test.2644946206 Mar 10 12:25:29 PM PDT 24 Mar 10 12:25:30 PM PDT 24 26606517 ps
T642 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.220639121 Mar 10 12:25:43 PM PDT 24 Mar 10 12:25:45 PM PDT 24 113529110 ps
T643 /workspace/coverage/cover_reg_top/7.hmac_intr_test.4128535195 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:10 PM PDT 24 11255990 ps
T644 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2989426231 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:57 PM PDT 24 265639358 ps
T645 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1897979211 Mar 10 12:24:52 PM PDT 24 Mar 10 12:24:58 PM PDT 24 539123238 ps
T98 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1668740731 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:11 PM PDT 24 62837550 ps
T646 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2072256312 Mar 10 12:25:00 PM PDT 24 Mar 10 12:25:03 PM PDT 24 34068707 ps
T647 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.86470044 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:58 PM PDT 24 19694155 ps
T648 /workspace/coverage/cover_reg_top/13.hmac_intr_test.4028680176 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:05 PM PDT 24 55899567 ps
T649 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3990799923 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:07 PM PDT 24 62431951 ps
T650 /workspace/coverage/cover_reg_top/48.hmac_intr_test.4232736264 Mar 10 12:25:22 PM PDT 24 Mar 10 12:25:23 PM PDT 24 12526062 ps
T651 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.174082993 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:57 PM PDT 24 39027292 ps
T652 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1652264251 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:53 PM PDT 24 27676107 ps
T653 /workspace/coverage/cover_reg_top/0.hmac_intr_test.3764273442 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:56 PM PDT 24 38436185 ps
T654 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1353933011 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:04 PM PDT 24 686161914 ps
T655 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3220751130 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:09 PM PDT 24 352207697 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4289397757 Mar 10 12:25:27 PM PDT 24 Mar 10 12:25:28 PM PDT 24 17498570 ps
T99 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.593333727 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:05 PM PDT 24 82837257 ps
T657 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1153437521 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:57 PM PDT 24 46985992 ps
T658 /workspace/coverage/cover_reg_top/45.hmac_intr_test.1373850472 Mar 10 12:25:10 PM PDT 24 Mar 10 12:25:11 PM PDT 24 13272506 ps
T659 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3649280616 Mar 10 12:25:47 PM PDT 24 Mar 10 12:25:47 PM PDT 24 30595691 ps
T660 /workspace/coverage/cover_reg_top/19.hmac_intr_test.314804254 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:02 PM PDT 24 14449351 ps
T661 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3070422612 Mar 10 12:25:25 PM PDT 24 Mar 10 12:25:26 PM PDT 24 36581442 ps
T662 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2012158322 Mar 10 12:24:59 PM PDT 24 Mar 10 12:25:00 PM PDT 24 82868602 ps
T663 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1412857081 Mar 10 12:24:56 PM PDT 24 Mar 10 12:25:00 PM PDT 24 332572042 ps
T100 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2742100768 Mar 10 12:25:03 PM PDT 24 Mar 10 12:25:04 PM PDT 24 18121088 ps
T664 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2366257635 Mar 10 12:25:56 PM PDT 24 Mar 10 12:25:58 PM PDT 24 20944712 ps
T665 /workspace/coverage/cover_reg_top/44.hmac_intr_test.1875849521 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:10 PM PDT 24 12935874 ps
T666 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3996273756 Mar 10 12:24:58 PM PDT 24 Mar 10 12:25:03 PM PDT 24 654659564 ps
T667 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.844407122 Mar 10 12:25:01 PM PDT 24 Mar 10 12:38:30 PM PDT 24 75681349229 ps
T668 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.734691360 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:59 PM PDT 24 345920202 ps
T669 /workspace/coverage/cover_reg_top/49.hmac_intr_test.463471140 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:09 PM PDT 24 69866023 ps
T670 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4249550723 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:08 PM PDT 24 30311469 ps
T671 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2058749537 Mar 10 12:25:53 PM PDT 24 Mar 10 12:25:58 PM PDT 24 51484597 ps
T672 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.45541492 Mar 10 12:24:50 PM PDT 24 Mar 10 12:24:51 PM PDT 24 62021858 ps
T101 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.303264278 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:02 PM PDT 24 51814620 ps
T102 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2315587333 Mar 10 12:25:43 PM PDT 24 Mar 10 12:25:50 PM PDT 24 348974178 ps
T673 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2681289029 Mar 10 12:25:08 PM PDT 24 Mar 10 12:25:10 PM PDT 24 24952970 ps
T674 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1489194286 Mar 10 12:25:11 PM PDT 24 Mar 10 12:25:11 PM PDT 24 24787556 ps
T675 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1189922838 Mar 10 12:25:12 PM PDT 24 Mar 10 12:25:14 PM PDT 24 241287872 ps
T676 /workspace/coverage/cover_reg_top/34.hmac_intr_test.691907137 Mar 10 12:25:22 PM PDT 24 Mar 10 12:25:23 PM PDT 24 47395327 ps
T677 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2766781852 Mar 10 12:24:52 PM PDT 24 Mar 10 12:25:08 PM PDT 24 4388082776 ps
T678 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2682950651 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:58 PM PDT 24 598008156 ps
T62 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.856049624 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:14 PM PDT 24 155067506 ps
T679 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2726822837 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:03 PM PDT 24 33681859 ps
T680 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1017903350 Mar 10 12:24:54 PM PDT 24 Mar 10 12:35:03 PM PDT 24 66469753320 ps
T681 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3629149309 Mar 10 12:25:48 PM PDT 24 Mar 10 12:25:50 PM PDT 24 264080068 ps
T682 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4210950525 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:07 PM PDT 24 48993323 ps
T683 /workspace/coverage/cover_reg_top/10.hmac_intr_test.776549798 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:05 PM PDT 24 12901449 ps
T684 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2500360815 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:08 PM PDT 24 204943030 ps
T685 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3971003882 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:54 PM PDT 24 25677563 ps
T686 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2628248253 Mar 10 12:24:59 PM PDT 24 Mar 10 12:25:00 PM PDT 24 15762140 ps
T687 /workspace/coverage/cover_reg_top/32.hmac_intr_test.522676040 Mar 10 12:25:08 PM PDT 24 Mar 10 12:25:09 PM PDT 24 14867571 ps
T688 /workspace/coverage/cover_reg_top/2.hmac_intr_test.3426121195 Mar 10 12:24:56 PM PDT 24 Mar 10 12:24:57 PM PDT 24 45407642 ps
T689 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3889970511 Mar 10 12:25:12 PM PDT 24 Mar 10 12:25:13 PM PDT 24 12256098 ps
T690 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2750187669 Mar 10 12:24:59 PM PDT 24 Mar 10 12:25:01 PM PDT 24 83726838 ps
T691 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3334351452 Mar 10 12:25:07 PM PDT 24 Mar 10 12:25:10 PM PDT 24 613154865 ps
T692 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.975641436 Mar 10 12:25:00 PM PDT 24 Mar 10 12:25:03 PM PDT 24 331743789 ps
T693 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2303365119 Mar 10 12:24:54 PM PDT 24 Mar 10 12:24:56 PM PDT 24 95188594 ps
T694 /workspace/coverage/cover_reg_top/36.hmac_intr_test.893494302 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:08 PM PDT 24 42619911 ps
T695 /workspace/coverage/cover_reg_top/16.hmac_intr_test.2098220465 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:02 PM PDT 24 14843150 ps
T61 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2638825672 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:09 PM PDT 24 804567412 ps
T696 /workspace/coverage/cover_reg_top/37.hmac_intr_test.1056340372 Mar 10 12:25:10 PM PDT 24 Mar 10 12:25:11 PM PDT 24 46640451 ps
T697 /workspace/coverage/cover_reg_top/23.hmac_intr_test.919809247 Mar 10 12:25:51 PM PDT 24 Mar 10 12:25:52 PM PDT 24 119161163 ps
T698 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3669715258 Mar 10 12:24:52 PM PDT 24 Mar 10 12:24:53 PM PDT 24 32527080 ps
T699 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3999590871 Mar 10 12:25:11 PM PDT 24 Mar 10 12:25:15 PM PDT 24 268300349 ps
T700 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2476218045 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:09 PM PDT 24 69389879 ps
T701 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3940336341 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:10 PM PDT 24 185005611 ps
T702 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2715603147 Mar 10 12:24:48 PM PDT 24 Mar 10 12:38:13 PM PDT 24 517014376021 ps
T703 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1326000342 Mar 10 12:25:08 PM PDT 24 Mar 10 12:25:09 PM PDT 24 26485979 ps
T704 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.139305580 Mar 10 12:24:57 PM PDT 24 Mar 10 12:25:04 PM PDT 24 1578362432 ps
T705 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.800797078 Mar 10 12:25:34 PM PDT 24 Mar 10 12:25:36 PM PDT 24 92431813 ps
T706 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2492418834 Mar 10 12:25:20 PM PDT 24 Mar 10 12:25:21 PM PDT 24 13953554 ps
T707 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4234559349 Mar 10 12:24:57 PM PDT 24 Mar 10 12:24:59 PM PDT 24 56696528 ps
T708 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3014741157 Mar 10 12:24:50 PM PDT 24 Mar 10 12:24:50 PM PDT 24 46624091 ps
T709 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2271412043 Mar 10 12:25:44 PM PDT 24 Mar 10 12:25:45 PM PDT 24 70429583 ps
T710 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2279582629 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:57 PM PDT 24 373493494 ps
T711 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.602602368 Mar 10 12:24:55 PM PDT 24 Mar 10 12:24:58 PM PDT 24 610519945 ps
T712 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3890065257 Mar 10 12:25:03 PM PDT 24 Mar 10 12:25:08 PM PDT 24 784106375 ps
T713 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4078198493 Mar 10 12:25:12 PM PDT 24 Mar 10 12:25:12 PM PDT 24 29415532 ps
T714 /workspace/coverage/cover_reg_top/15.hmac_intr_test.2196887466 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:07 PM PDT 24 29171772 ps
T715 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2621332957 Mar 10 12:25:13 PM PDT 24 Mar 10 12:25:14 PM PDT 24 23563730 ps
T716 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3782651711 Mar 10 12:24:53 PM PDT 24 Mar 10 12:24:57 PM PDT 24 737718758 ps
T717 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2038640142 Mar 10 12:25:05 PM PDT 24 Mar 10 12:25:08 PM PDT 24 169001973 ps
T718 /workspace/coverage/cover_reg_top/40.hmac_intr_test.431702752 Mar 10 12:25:09 PM PDT 24 Mar 10 12:25:10 PM PDT 24 14560519 ps
T719 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1652975771 Mar 10 12:25:13 PM PDT 24 Mar 10 12:25:15 PM PDT 24 132395951 ps
T720 /workspace/coverage/cover_reg_top/28.hmac_intr_test.648354736 Mar 10 12:25:41 PM PDT 24 Mar 10 12:25:42 PM PDT 24 15086514 ps
T721 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.560260402 Mar 10 12:25:03 PM PDT 24 Mar 10 12:25:04 PM PDT 24 246400808 ps
T722 /workspace/coverage/cover_reg_top/47.hmac_intr_test.2349364618 Mar 10 12:25:22 PM PDT 24 Mar 10 12:25:22 PM PDT 24 50678064 ps
T723 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.664729322 Mar 10 12:24:43 PM PDT 24 Mar 10 12:24:45 PM PDT 24 128408546 ps
T724 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3214699059 Mar 10 12:25:15 PM PDT 24 Mar 10 12:25:17 PM PDT 24 82490459 ps
T725 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1399433351 Mar 10 12:25:04 PM PDT 24 Mar 10 12:25:06 PM PDT 24 62784099 ps
T726 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1640638035 Mar 10 12:25:03 PM PDT 24 Mar 10 12:25:07 PM PDT 24 2313356308 ps
T727 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1777402908 Mar 10 12:24:59 PM PDT 24 Mar 10 12:25:01 PM PDT 24 81671009 ps
T60 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1876563215 Mar 10 12:25:32 PM PDT 24 Mar 10 12:25:33 PM PDT 24 83402592 ps
T728 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1089707478 Mar 10 12:24:53 PM PDT 24 Mar 10 12:25:09 PM PDT 24 1127024484 ps
T729 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.888606704 Mar 10 12:24:58 PM PDT 24 Mar 10 12:25:00 PM PDT 24 84336373 ps
T730 /workspace/coverage/cover_reg_top/25.hmac_intr_test.2004714346 Mar 10 12:25:12 PM PDT 24 Mar 10 12:25:13 PM PDT 24 51326103 ps
T731 /workspace/coverage/cover_reg_top/46.hmac_intr_test.2164626487 Mar 10 12:25:24 PM PDT 24 Mar 10 12:25:25 PM PDT 24 58710802 ps
T732 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2606937799 Mar 10 12:24:56 PM PDT 24 Mar 10 12:24:57 PM PDT 24 21762543 ps
T733 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1716550412 Mar 10 12:25:01 PM PDT 24 Mar 10 12:25:05 PM PDT 24 159785735 ps
T734 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3341972079 Mar 10 12:25:27 PM PDT 24 Mar 10 12:25:28 PM PDT 24 119854534 ps
T735 /workspace/coverage/cover_reg_top/33.hmac_intr_test.2329534355 Mar 10 12:25:06 PM PDT 24 Mar 10 12:25:07 PM PDT 24 15682932 ps

Test location /workspace/coverage/default/7.hmac_long_msg.3542018551
Short name T5
Test name
Test status
Simulation time 4285475741 ps
CPU time 41.57 seconds
Started Mar 10 01:39:26 PM PDT 24
Finished Mar 10 01:40:08 PM PDT 24
Peak memory 199988 kb
Host smart-3219b042-99c9-4b9b-88c3-4c65cd98a630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542018551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3542018551
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/101.hmac_stress_all_with_rand_reset.182141436
Short name T13
Test name
Test status
Simulation time 274116017913 ps
CPU time 2524.39 seconds
Started Mar 10 01:43:03 PM PDT 24
Finished Mar 10 02:25:08 PM PDT 24
Peak memory 241768 kb
Host smart-2e9e427b-761d-4b04-a0b2-1c0f1706d361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182141436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.hmac_stress_all_with_rand_reset.182141436
Directory /workspace/101.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.167442747
Short name T30
Test name
Test status
Simulation time 281654681 ps
CPU time 1.3 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 219388 kb
Host smart-2f24cd04-1d22-49fe-b601-6fbcd6fb54be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167442747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.167442747
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/170.hmac_stress_all_with_rand_reset.893826201
Short name T11
Test name
Test status
Simulation time 185376946835 ps
CPU time 2167.11 seconds
Started Mar 10 01:43:46 PM PDT 24
Finished Mar 10 02:19:54 PM PDT 24
Peak memory 254392 kb
Host smart-d833a8ca-4dd6-4ddb-b5f2-ceae72c7b3df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=893826201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.hmac_stress_all_with_rand_reset.893826201
Directory /workspace/170.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3733055371
Short name T106
Test name
Test status
Simulation time 864543932 ps
CPU time 4.25 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 198944 kb
Host smart-ccdc9595-1ee2-4a48-8f9f-f9bb8e9bf913
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733055371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3733055371
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/51.hmac_stress_all_with_rand_reset.2191160311
Short name T10
Test name
Test status
Simulation time 71488471172 ps
CPU time 1185.67 seconds
Started Mar 10 01:42:40 PM PDT 24
Finished Mar 10 02:02:26 PM PDT 24
Peak memory 232872 kb
Host smart-f65970bf-5673-4558-8007-10337506a6c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191160311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.hmac_stress_all_with_rand_reset.2191160311
Directory /workspace/51.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.hmac_stress_all.217024460
Short name T38
Test name
Test status
Simulation time 82522966474 ps
CPU time 1292.34 seconds
Started Mar 10 01:42:21 PM PDT 24
Finished Mar 10 02:03:54 PM PDT 24
Peak memory 226628 kb
Host smart-5263416a-0e11-4cca-bad6-e1bc7377ef6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217024460 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.217024460
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.2726974745
Short name T93
Test name
Test status
Simulation time 112457286 ps
CPU time 5.57 seconds
Started Mar 10 12:24:52 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 198084 kb
Host smart-385a679a-f4b2-4394-88f2-fd18c50944a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726974745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.2726974745
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.3203047292
Short name T109
Test name
Test status
Simulation time 105054224 ps
CPU time 1.84 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 198948 kb
Host smart-668e6a2b-1853-499d-8de4-0e739a2ea926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203047292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.3203047292
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/47.hmac_alert_test.4249889836
Short name T23
Test name
Test status
Simulation time 24387884 ps
CPU time 0.63 seconds
Started Mar 10 01:42:33 PM PDT 24
Finished Mar 10 01:42:33 PM PDT 24
Peak memory 195336 kb
Host smart-1be768cc-d310-4623-ae39-3265cf837bb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249889836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.4249889836
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1787639497
Short name T202
Test name
Test status
Simulation time 24941072487 ps
CPU time 1304.84 seconds
Started Mar 10 01:42:19 PM PDT 24
Finished Mar 10 02:04:05 PM PDT 24
Peak memory 199984 kb
Host smart-29914c51-66c9-4a0f-9e67-6b50e7122734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787639497 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1787639497
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.2638825672
Short name T61
Test name
Test status
Simulation time 804567412 ps
CPU time 3.05 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 198992 kb
Host smart-ef42f4b1-93d3-4ab8-a929-7af24bd7c46c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638825672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.2638825672
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/14.hmac_stress_all.2080150376
Short name T41
Test name
Test status
Simulation time 629627984048 ps
CPU time 1720.92 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 02:08:23 PM PDT 24
Peak memory 229200 kb
Host smart-7125c5cb-acae-407b-b7f3-a39963a77483
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080150376 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.2080150376
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1876563215
Short name T60
Test name
Test status
Simulation time 83402592 ps
CPU time 1.85 seconds
Started Mar 10 12:25:32 PM PDT 24
Finished Mar 10 12:25:33 PM PDT 24
Peak memory 198912 kb
Host smart-64de241b-cf3c-4101-a8aa-2112a77edeca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876563215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1876563215
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.856049624
Short name T62
Test name
Test status
Simulation time 155067506 ps
CPU time 3.09 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:14 PM PDT 24
Peak memory 198916 kb
Host smart-4684c46e-1655-4b28-8673-37caf19c5664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856049624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.856049624
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/12.hmac_stress_all.3145333641
Short name T46
Test name
Test status
Simulation time 118959487148 ps
CPU time 1083.3 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:57:49 PM PDT 24
Peak memory 240692 kb
Host smart-32203811-8b7b-4d90-9b9e-2c80fcb75f7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145333641 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.3145333641
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.1897979211
Short name T645
Test name
Test status
Simulation time 539123238 ps
CPU time 5.95 seconds
Started Mar 10 12:24:52 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 197556 kb
Host smart-ed749696-ab2f-4534-8c24-9bfc18501d25
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897979211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.1897979211
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.664729322
Short name T723
Test name
Test status
Simulation time 128408546 ps
CPU time 0.83 seconds
Started Mar 10 12:24:43 PM PDT 24
Finished Mar 10 12:24:45 PM PDT 24
Peak memory 197276 kb
Host smart-84907ec6-3c85-48c0-9aa5-277b61071236
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664729322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.664729322
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.2271412043
Short name T709
Test name
Test status
Simulation time 70429583 ps
CPU time 1.07 seconds
Started Mar 10 12:25:44 PM PDT 24
Finished Mar 10 12:25:45 PM PDT 24
Peak memory 198940 kb
Host smart-167b1b64-a4d0-45a8-a380-8aa00fb4b557
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271412043 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.2271412043
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2012158322
Short name T662
Test name
Test status
Simulation time 82868602 ps
CPU time 0.83 seconds
Started Mar 10 12:24:59 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 197776 kb
Host smart-02038f90-82f5-4dd6-b0f2-54c0b32e3cad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012158322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2012158322
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.3764273442
Short name T653
Test name
Test status
Simulation time 38436185 ps
CPU time 0.55 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:56 PM PDT 24
Peak memory 193488 kb
Host smart-6c0fa049-c3c7-492d-bda2-cca9381721d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764273442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.3764273442
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2178414243
Short name T639
Test name
Test status
Simulation time 46284035 ps
CPU time 1.17 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:56 PM PDT 24
Peak memory 196876 kb
Host smart-be93084a-217d-4474-a6bc-bee5ea592c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178414243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2178414243
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1708926992
Short name T640
Test name
Test status
Simulation time 96534787 ps
CPU time 2.09 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:56 PM PDT 24
Peak memory 199012 kb
Host smart-e5ce3dca-9119-425e-a499-1406bbd8f66a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708926992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1708926992
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.824336807
Short name T110
Test name
Test status
Simulation time 534524343 ps
CPU time 4.38 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 198924 kb
Host smart-20874e50-6364-4d08-a7d5-6250727593e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824336807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.824336807
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.294988479
Short name T619
Test name
Test status
Simulation time 186100336 ps
CPU time 3.08 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 197156 kb
Host smart-a3df9c2a-724c-4ed9-ae14-7f53e3c39376
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294988479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.294988479
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.644849679
Short name T637
Test name
Test status
Simulation time 4450493184 ps
CPU time 5.87 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 198004 kb
Host smart-b095efa6-4745-43e4-a784-3fc8aceed2a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644849679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.644849679
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.888606704
Short name T729
Test name
Test status
Simulation time 84336373 ps
CPU time 1.15 seconds
Started Mar 10 12:24:58 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 197780 kb
Host smart-eff77a94-126f-4ac4-b924-507bec78158d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888606704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.888606704
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2303365119
Short name T693
Test name
Test status
Simulation time 95188594 ps
CPU time 1.72 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:56 PM PDT 24
Peak memory 199012 kb
Host smart-21b497b3-a0a8-4cb5-bac1-181642072244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303365119 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2303365119
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.2661275989
Short name T57
Test name
Test status
Simulation time 213787122 ps
CPU time 0.98 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 198860 kb
Host smart-40247262-eb3e-4c35-9f45-71616ae779ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661275989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.2661275989
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1588909240
Short name T598
Test name
Test status
Simulation time 20655851 ps
CPU time 0.6 seconds
Started Mar 10 12:25:02 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 193492 kb
Host smart-13d0e8cb-aa67-4e99-8869-2638673ff811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588909240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1588909240
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3341972079
Short name T734
Test name
Test status
Simulation time 119854534 ps
CPU time 1.18 seconds
Started Mar 10 12:25:27 PM PDT 24
Finished Mar 10 12:25:28 PM PDT 24
Peak memory 197476 kb
Host smart-ceec828c-c325-40c2-b7f4-59356bd5557c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341972079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3341972079
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.141836506
Short name T636
Test name
Test status
Simulation time 124655352 ps
CPU time 2.99 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 199060 kb
Host smart-7fe52153-0a31-49c4-ac84-9d02f57db78b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141836506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.141836506
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2038640142
Short name T717
Test name
Test status
Simulation time 169001973 ps
CPU time 2.82 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 198852 kb
Host smart-a3dd9479-d73b-4bd5-83e3-c4d55bf94088
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038640142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2038640142
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.734691360
Short name T668
Test name
Test status
Simulation time 345920202 ps
CPU time 1.89 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 199140 kb
Host smart-c85d71eb-d491-44f4-86bd-c2d930e0ffdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734691360 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.734691360
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2500360815
Short name T684
Test name
Test status
Simulation time 204943030 ps
CPU time 0.7 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 196352 kb
Host smart-631e5083-8960-4fea-902a-8026f84d9873
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500360815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2500360815
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.776549798
Short name T683
Test name
Test status
Simulation time 12901449 ps
CPU time 0.56 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:05 PM PDT 24
Peak memory 193524 kb
Host smart-aff6109b-4d67-4247-ba18-ad9c84a01bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776549798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.776549798
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.2252697324
Short name T617
Test name
Test status
Simulation time 53757452 ps
CPU time 1.11 seconds
Started Mar 10 12:25:07 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 197880 kb
Host smart-080cb69a-b7b0-4cfc-931d-fb0ffe2480ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252697324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.2252697324
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2476218045
Short name T700
Test name
Test status
Simulation time 69389879 ps
CPU time 3.8 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 199056 kb
Host smart-b6eaffe2-58cb-4717-8c79-95e88a2a4f01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476218045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2476218045
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3940336341
Short name T701
Test name
Test status
Simulation time 185005611 ps
CPU time 2.51 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198804 kb
Host smart-6d07079c-b40f-4743-8e5c-383ca9d52eea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940336341 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3940336341
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.2449928839
Short name T616
Test name
Test status
Simulation time 30729538 ps
CPU time 0.95 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 198004 kb
Host smart-c299ec53-c4b8-4479-ac72-e8d8145366ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449928839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.2449928839
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3742080871
Short name T621
Test name
Test status
Simulation time 33090942 ps
CPU time 0.6 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 193384 kb
Host smart-1cc7f85f-1147-418c-91c1-058ac2d97366
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742080871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3742080871
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3990799923
Short name T649
Test name
Test status
Simulation time 62431951 ps
CPU time 1.24 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 197916 kb
Host smart-5c45ed77-451e-497e-b40d-c13ff5bb5b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990799923 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3990799923
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.3220751130
Short name T655
Test name
Test status
Simulation time 352207697 ps
CPU time 2.19 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 198976 kb
Host smart-6de0ce27-0511-4884-b1e6-dc96902131a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220751130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.3220751130
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1189922838
Short name T675
Test name
Test status
Simulation time 241287872 ps
CPU time 1.58 seconds
Started Mar 10 12:25:12 PM PDT 24
Finished Mar 10 12:25:14 PM PDT 24
Peak memory 199080 kb
Host smart-11a3b0c5-a012-4add-8709-5051f14fd40a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189922838 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1189922838
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.593333727
Short name T99
Test name
Test status
Simulation time 82837257 ps
CPU time 0.78 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:05 PM PDT 24
Peak memory 197904 kb
Host smart-4fd6a92e-18a5-464b-a32f-1839747cd88d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593333727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.593333727
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2621332957
Short name T715
Test name
Test status
Simulation time 23563730 ps
CPU time 0.59 seconds
Started Mar 10 12:25:13 PM PDT 24
Finished Mar 10 12:25:14 PM PDT 24
Peak memory 193552 kb
Host smart-db072736-79f2-43ff-9a03-4d884a970262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621332957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2621332957
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.2319848726
Short name T624
Test name
Test status
Simulation time 358174043 ps
CPU time 1.6 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:06 PM PDT 24
Peak memory 198784 kb
Host smart-e768e447-a771-475c-b307-64018dd983b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319848726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.2319848726
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3890065257
Short name T712
Test name
Test status
Simulation time 784106375 ps
CPU time 4.18 seconds
Started Mar 10 12:25:03 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 198936 kb
Host smart-84483717-51a8-4b4d-9aa5-2cdeffc9922f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890065257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3890065257
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.630088855
Short name T630
Test name
Test status
Simulation time 257574343 ps
CPU time 3.79 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198912 kb
Host smart-d05c07b5-e9fd-4743-8436-58d1e2025f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630088855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.630088855
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.2072256312
Short name T646
Test name
Test status
Simulation time 34068707 ps
CPU time 1.82 seconds
Started Mar 10 12:25:00 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 199060 kb
Host smart-463a6e73-7ca1-4fdc-988e-a88b3e4b27c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072256312 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.2072256312
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.86470044
Short name T647
Test name
Test status
Simulation time 19694155 ps
CPU time 0.71 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 196252 kb
Host smart-f96c9ab3-43ad-42fe-a240-f741db4d5e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86470044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.86470044
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.4028680176
Short name T648
Test name
Test status
Simulation time 55899567 ps
CPU time 0.59 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:05 PM PDT 24
Peak memory 193440 kb
Host smart-3f76d796-15ed-43ac-9f86-6cded468f54c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028680176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.4028680176
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.1153437521
Short name T657
Test name
Test status
Simulation time 46985992 ps
CPU time 1.1 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 197496 kb
Host smart-9be6c2a5-e3a4-4826-9e52-b09861d4c1fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153437521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.1153437521
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3064234566
Short name T613
Test name
Test status
Simulation time 179284831 ps
CPU time 2.45 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 199072 kb
Host smart-08c16cca-33b4-4697-bc1a-438d24cd649a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064234566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3064234566
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.65708106
Short name T108
Test name
Test status
Simulation time 529710976 ps
CPU time 3.97 seconds
Started Mar 10 12:24:59 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 199056 kb
Host smart-7b1cff93-3e25-4eaf-a91c-6f720072569a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65708106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.65708106
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.844407122
Short name T667
Test name
Test status
Simulation time 75681349229 ps
CPU time 808.44 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:38:30 PM PDT 24
Peak memory 216736 kb
Host smart-4b4135d3-2392-4d81-8515-87aa136b8163
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844407122 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.844407122
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.1364807425
Short name T95
Test name
Test status
Simulation time 59817774 ps
CPU time 0.67 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 196500 kb
Host smart-bcf07fea-ea27-452e-8036-db9ebd5d82fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364807425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.1364807425
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1652264251
Short name T652
Test name
Test status
Simulation time 27676107 ps
CPU time 0.56 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:53 PM PDT 24
Peak memory 193544 kb
Host smart-38328bf2-9658-4d0a-9966-b2fdd62bedf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652264251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1652264251
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1231789236
Short name T627
Test name
Test status
Simulation time 230366472 ps
CPU time 2.37 seconds
Started Mar 10 12:25:00 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 198736 kb
Host smart-e317c88a-d116-4123-99ec-3f41db061233
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231789236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1231789236
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1777402908
Short name T727
Test name
Test status
Simulation time 81671009 ps
CPU time 1.31 seconds
Started Mar 10 12:24:59 PM PDT 24
Finished Mar 10 12:25:01 PM PDT 24
Peak memory 199036 kb
Host smart-86aa0b01-8f43-4008-a8fd-ec63008b3b39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777402908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1777402908
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3999590871
Short name T699
Test name
Test status
Simulation time 268300349 ps
CPU time 4.46 seconds
Started Mar 10 12:25:11 PM PDT 24
Finished Mar 10 12:25:15 PM PDT 24
Peak memory 198976 kb
Host smart-feb9304c-9215-47d1-81de-bf12b96a340e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999590871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3999590871
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2541539540
Short name T59
Test name
Test status
Simulation time 130387545 ps
CPU time 2.32 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 199000 kb
Host smart-369861ba-d16d-4f88-bc2b-71002687e3d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541539540 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2541539540
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.2113965818
Short name T97
Test name
Test status
Simulation time 34941482 ps
CPU time 0.93 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198048 kb
Host smart-67086dac-2109-453b-a2ec-98964294bf46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113965818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.2113965818
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.2196887466
Short name T714
Test name
Test status
Simulation time 29171772 ps
CPU time 0.6 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 193548 kb
Host smart-b8b06351-56f6-4f79-b6b2-6dd660a87ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196887466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.2196887466
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3214699059
Short name T724
Test name
Test status
Simulation time 82490459 ps
CPU time 1.05 seconds
Started Mar 10 12:25:15 PM PDT 24
Finished Mar 10 12:25:17 PM PDT 24
Peak memory 198124 kb
Host smart-ff52050d-7f33-476f-b680-2eb2d206ece7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214699059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3214699059
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1412857081
Short name T663
Test name
Test status
Simulation time 332572042 ps
CPU time 3.67 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 198944 kb
Host smart-207a56cb-da4a-419c-9262-b529bf06ee39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412857081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1412857081
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.958609312
Short name T628
Test name
Test status
Simulation time 375462146 ps
CPU time 2.13 seconds
Started Mar 10 12:25:10 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 199060 kb
Host smart-f70eabe3-cf55-486b-90d0-71a77a03d7be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958609312 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.958609312
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.1326000342
Short name T703
Test name
Test status
Simulation time 26485979 ps
CPU time 0.77 seconds
Started Mar 10 12:25:08 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 197744 kb
Host smart-a1a372b0-6848-4f18-9c7e-d3d417d62c38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326000342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.1326000342
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.2098220465
Short name T695
Test name
Test status
Simulation time 14843150 ps
CPU time 0.55 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 193484 kb
Host smart-29add68f-97c3-4823-b59d-beabd5b6d39e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098220465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.2098220465
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.220639121
Short name T642
Test name
Test status
Simulation time 113529110 ps
CPU time 1.63 seconds
Started Mar 10 12:25:43 PM PDT 24
Finished Mar 10 12:25:45 PM PDT 24
Peak memory 198932 kb
Host smart-f0a61755-3405-44a2-a028-b0d1c0aade02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220639121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.220639121
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3996273756
Short name T666
Test name
Test status
Simulation time 654659564 ps
CPU time 3.49 seconds
Started Mar 10 12:24:58 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 199008 kb
Host smart-cedd10fe-7cc2-4ced-8049-5be751780abd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996273756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3996273756
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.2726822837
Short name T679
Test name
Test status
Simulation time 33681859 ps
CPU time 1.92 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 199136 kb
Host smart-b3aa80e0-412b-412d-98e8-c5b3dc42431d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726822837 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.2726822837
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3072182442
Short name T631
Test name
Test status
Simulation time 91240215 ps
CPU time 0.81 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:05 PM PDT 24
Peak memory 197388 kb
Host smart-b583dc8d-975f-481c-becb-cc4d6b2bad6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072182442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3072182442
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2628248253
Short name T686
Test name
Test status
Simulation time 15762140 ps
CPU time 0.57 seconds
Started Mar 10 12:24:59 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 193408 kb
Host smart-67f52e94-9907-4e71-8ab5-58c741db3f6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628248253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2628248253
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3909299839
Short name T620
Test name
Test status
Simulation time 299322470 ps
CPU time 2.03 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 198924 kb
Host smart-b8ba3eda-6360-4ccc-bbbc-d22246e11149
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909299839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3909299839
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1652975771
Short name T719
Test name
Test status
Simulation time 132395951 ps
CPU time 1.99 seconds
Started Mar 10 12:25:13 PM PDT 24
Finished Mar 10 12:25:15 PM PDT 24
Peak memory 198972 kb
Host smart-b23aed2a-a5d0-4638-bbb9-0b32db06deb0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652975771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1652975771
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1652813983
Short name T105
Test name
Test status
Simulation time 1005108290 ps
CPU time 4.32 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:14 PM PDT 24
Peak memory 199024 kb
Host smart-6ad60f0f-dbe6-4900-b037-806a8e79fcb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652813983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1652813983
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2058749537
Short name T671
Test name
Test status
Simulation time 51484597 ps
CPU time 3.13 seconds
Started Mar 10 12:25:53 PM PDT 24
Finished Mar 10 12:25:58 PM PDT 24
Peak memory 199088 kb
Host smart-9e876e19-ec29-43c9-9cb9-db0fbe3e47b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058749537 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2058749537
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1668740731
Short name T98
Test name
Test status
Simulation time 62837550 ps
CPU time 0.95 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 198112 kb
Host smart-0478cc57-b009-44b3-932b-15e0b4ee148a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668740731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1668740731
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2492418834
Short name T706
Test name
Test status
Simulation time 13953554 ps
CPU time 0.58 seconds
Started Mar 10 12:25:20 PM PDT 24
Finished Mar 10 12:25:21 PM PDT 24
Peak memory 193484 kb
Host smart-2264bd95-c768-4c16-ae78-5f5bef48404d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492418834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2492418834
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.975641436
Short name T692
Test name
Test status
Simulation time 331743789 ps
CPU time 1.75 seconds
Started Mar 10 12:25:00 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 198688 kb
Host smart-2a6eb19a-f591-489e-a92e-9381980a09e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975641436 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.975641436
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2366257635
Short name T664
Test name
Test status
Simulation time 20944712 ps
CPU time 1.22 seconds
Started Mar 10 12:25:56 PM PDT 24
Finished Mar 10 12:25:58 PM PDT 24
Peak memory 198876 kb
Host smart-29f1ccdc-a2bb-4f49-8335-7a4a9e12f51d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366257635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2366257635
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1284418302
Short name T104
Test name
Test status
Simulation time 276750867 ps
CPU time 2.94 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198964 kb
Host smart-6e3680ed-a52d-4945-9bce-69fdec4448db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284418302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1284418302
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.300467734
Short name T626
Test name
Test status
Simulation time 120065604 ps
CPU time 2.13 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 199040 kb
Host smart-898a5730-7fab-4d4d-9620-2ddd9680e7bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300467734 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.300467734
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.1194950550
Short name T92
Test name
Test status
Simulation time 12233592 ps
CPU time 0.65 seconds
Started Mar 10 12:25:27 PM PDT 24
Finished Mar 10 12:25:28 PM PDT 24
Peak memory 196100 kb
Host smart-c265d961-1b97-4890-a80a-72f8d8bce0c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194950550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.1194950550
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.314804254
Short name T660
Test name
Test status
Simulation time 14449351 ps
CPU time 0.59 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 193508 kb
Host smart-4920db55-1ed0-4c86-8f1d-83b22ab6ea0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314804254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.314804254
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4132164495
Short name T612
Test name
Test status
Simulation time 424130111 ps
CPU time 2.27 seconds
Started Mar 10 12:25:11 PM PDT 24
Finished Mar 10 12:25:13 PM PDT 24
Peak memory 198836 kb
Host smart-e073dfde-8378-42ba-b96b-78d72ffc78b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132164495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4132164495
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3219256998
Short name T611
Test name
Test status
Simulation time 135267823 ps
CPU time 1.78 seconds
Started Mar 10 12:25:00 PM PDT 24
Finished Mar 10 12:25:03 PM PDT 24
Peak memory 198936 kb
Host smart-9ed41d04-8c1c-4416-92e9-615c4c2dbda7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219256998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3219256998
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1640638035
Short name T726
Test name
Test status
Simulation time 2313356308 ps
CPU time 3.25 seconds
Started Mar 10 12:25:03 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 199084 kb
Host smart-e8b001fd-7b65-4d00-9c3c-76a5557bd491
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640638035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1640638035
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4101077051
Short name T94
Test name
Test status
Simulation time 2300396291 ps
CPU time 8.91 seconds
Started Mar 10 12:25:03 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 198268 kb
Host smart-e57e5525-88f5-4e2a-9f29-70525d24d627
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101077051 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4101077051
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.4206816341
Short name T96
Test name
Test status
Simulation time 1275654657 ps
CPU time 14.27 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 197392 kb
Host smart-dc04c3d2-6c05-4414-af9f-fd26299e0cd3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206816341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.4206816341
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.303264278
Short name T101
Test name
Test status
Simulation time 51814620 ps
CPU time 0.81 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 197368 kb
Host smart-30708690-5d79-42d5-806a-6bf47a626159
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303264278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.303264278
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.2715603147
Short name T702
Test name
Test status
Simulation time 517014376021 ps
CPU time 804.81 seconds
Started Mar 10 12:24:48 PM PDT 24
Finished Mar 10 12:38:13 PM PDT 24
Peak memory 215600 kb
Host smart-68436ae7-1710-4a79-a4e6-d60ee1c0bf06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715603147 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.2715603147
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.4249550723
Short name T670
Test name
Test status
Simulation time 30311469 ps
CPU time 0.93 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 198032 kb
Host smart-3164aa96-bc78-40e3-bf59-308a4a8c2a81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249550723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.4249550723
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.3426121195
Short name T688
Test name
Test status
Simulation time 45407642 ps
CPU time 0.61 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 193532 kb
Host smart-063d36e5-7e5d-414b-8749-559d2d45de78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426121195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.3426121195
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3334351452
Short name T691
Test name
Test status
Simulation time 613154865 ps
CPU time 2.43 seconds
Started Mar 10 12:25:07 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198652 kb
Host smart-1cd45d94-e479-417f-aa3c-55be55dae8e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334351452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3334351452
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.3782651711
Short name T716
Test name
Test status
Simulation time 737718758 ps
CPU time 3.64 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 199128 kb
Host smart-18b5bc65-9bb4-4c87-b5a9-8acbb1a9994e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782651711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.3782651711
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.602602368
Short name T711
Test name
Test status
Simulation time 610519945 ps
CPU time 3.23 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 198944 kb
Host smart-481bfdb9-66ad-40cc-b023-6bf85c9d459b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602602368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.602602368
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1329719175
Short name T601
Test name
Test status
Simulation time 27720735 ps
CPU time 0.59 seconds
Started Mar 10 12:25:10 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 193512 kb
Host smart-808e74de-11fe-43a1-8005-c779e733cb57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329719175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1329719175
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3889970511
Short name T689
Test name
Test status
Simulation time 12256098 ps
CPU time 0.56 seconds
Started Mar 10 12:25:12 PM PDT 24
Finished Mar 10 12:25:13 PM PDT 24
Peak memory 192928 kb
Host smart-f4b6c840-1d48-4e15-9e50-a7fe86118406
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889970511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3889970511
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2455322981
Short name T600
Test name
Test status
Simulation time 31835990 ps
CPU time 0.62 seconds
Started Mar 10 12:25:11 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 193520 kb
Host smart-723f1303-90da-4652-9cc9-3969ffe342e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455322981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2455322981
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.919809247
Short name T697
Test name
Test status
Simulation time 119161163 ps
CPU time 0.57 seconds
Started Mar 10 12:25:51 PM PDT 24
Finished Mar 10 12:25:52 PM PDT 24
Peak memory 193596 kb
Host smart-db69064b-c598-4419-8eff-1e8846eca8b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919809247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.919809247
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.1522863011
Short name T633
Test name
Test status
Simulation time 27606358 ps
CPU time 0.61 seconds
Started Mar 10 12:25:47 PM PDT 24
Finished Mar 10 12:25:47 PM PDT 24
Peak memory 193588 kb
Host smart-dc8e7ec8-7078-424f-81fa-b45491a29135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522863011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.1522863011
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.2004714346
Short name T730
Test name
Test status
Simulation time 51326103 ps
CPU time 0.56 seconds
Started Mar 10 12:25:12 PM PDT 24
Finished Mar 10 12:25:13 PM PDT 24
Peak memory 192872 kb
Host smart-9e2e8123-2b58-4bf2-884b-0438ab530b0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004714346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.2004714346
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3649280616
Short name T659
Test name
Test status
Simulation time 30595691 ps
CPU time 0.66 seconds
Started Mar 10 12:25:47 PM PDT 24
Finished Mar 10 12:25:47 PM PDT 24
Peak memory 193488 kb
Host smart-c6bb80aa-e3e6-4d7e-acb8-6a4e9a2ab6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649280616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3649280616
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.850469225
Short name T606
Test name
Test status
Simulation time 181394593 ps
CPU time 0.61 seconds
Started Mar 10 12:25:45 PM PDT 24
Finished Mar 10 12:25:46 PM PDT 24
Peak memory 193496 kb
Host smart-eeaa7b64-71b7-43a3-acca-7dfab64b0586
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850469225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.850469225
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.648354736
Short name T720
Test name
Test status
Simulation time 15086514 ps
CPU time 0.64 seconds
Started Mar 10 12:25:41 PM PDT 24
Finished Mar 10 12:25:42 PM PDT 24
Peak memory 193496 kb
Host smart-91567841-a263-4c38-97e2-d49d196fd905
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648354736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.648354736
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.67447970
Short name T609
Test name
Test status
Simulation time 10789930 ps
CPU time 0.57 seconds
Started Mar 10 12:25:25 PM PDT 24
Finished Mar 10 12:25:25 PM PDT 24
Peak memory 193468 kb
Host smart-d9963815-624f-466d-b8dc-9cd77a24293c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67447970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.67447970
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.139305580
Short name T704
Test name
Test status
Simulation time 1578362432 ps
CPU time 6.41 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:25:04 PM PDT 24
Peak memory 198584 kb
Host smart-b4962e0f-6a7e-40fb-bfa2-9aeeb549e70e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139305580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.139305580
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1089707478
Short name T728
Test name
Test status
Simulation time 1127024484 ps
CPU time 15.47 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 197408 kb
Host smart-437b8285-3029-4281-a2f5-4de3f30b3af9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089707478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1089707478
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3669715258
Short name T698
Test name
Test status
Simulation time 32527080 ps
CPU time 0.7 seconds
Started Mar 10 12:24:52 PM PDT 24
Finished Mar 10 12:24:53 PM PDT 24
Peak memory 196224 kb
Host smart-8ecf8d04-f1f0-4028-9e9d-b64b342637f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669715258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3669715258
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.174082993
Short name T651
Test name
Test status
Simulation time 39027292 ps
CPU time 2.3 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 198964 kb
Host smart-ffc302a8-40e7-4740-8909-3bfab060275a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174082993 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.174082993
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3971003882
Short name T685
Test name
Test status
Simulation time 25677563 ps
CPU time 0.8 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:54 PM PDT 24
Peak memory 197468 kb
Host smart-2391ce8b-d0ac-4037-985e-287bf70f4aa4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971003882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3971003882
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4133989215
Short name T607
Test name
Test status
Simulation time 12354080 ps
CPU time 0.62 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:54 PM PDT 24
Peak memory 193392 kb
Host smart-1e34acfc-2cea-479d-9928-610bbd04b49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133989215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4133989215
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.109341945
Short name T632
Test name
Test status
Simulation time 160943080 ps
CPU time 2.54 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:25:00 PM PDT 24
Peak memory 198840 kb
Host smart-d90e640d-468e-4f19-97e0-dd0860fda172
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109341945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.109341945
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.199463531
Short name T629
Test name
Test status
Simulation time 614671601 ps
CPU time 3.29 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 198932 kb
Host smart-a28601f7-cff3-4b2b-91fd-2bc19ad5181f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199463531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.199463531
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2443923633
Short name T54
Test name
Test status
Simulation time 880668535 ps
CPU time 4.48 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:25:01 PM PDT 24
Peak memory 198892 kb
Host smart-ea6f9bba-f605-4b89-9c00-b0453bb9273a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443923633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2443923633
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2897142389
Short name T605
Test name
Test status
Simulation time 18519991 ps
CPU time 0.58 seconds
Started Mar 10 12:25:24 PM PDT 24
Finished Mar 10 12:25:24 PM PDT 24
Peak memory 193552 kb
Host smart-340119ac-2261-4471-a682-baaeb3bb53ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897142389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2897142389
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3786294998
Short name T622
Test name
Test status
Simulation time 14312154 ps
CPU time 0.56 seconds
Started Mar 10 12:25:07 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 193548 kb
Host smart-a8c204ff-f9b3-4ae8-b5d7-def82003e63f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786294998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3786294998
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.522676040
Short name T687
Test name
Test status
Simulation time 14867571 ps
CPU time 0.55 seconds
Started Mar 10 12:25:08 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 193512 kb
Host smart-a334a516-e9f8-477e-a58f-c5da0456a650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522676040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.522676040
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.2329534355
Short name T735
Test name
Test status
Simulation time 15682932 ps
CPU time 0.61 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 193484 kb
Host smart-6c52938e-5233-49f5-a71a-8f2397f28740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329534355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.2329534355
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.691907137
Short name T676
Test name
Test status
Simulation time 47395327 ps
CPU time 0.54 seconds
Started Mar 10 12:25:22 PM PDT 24
Finished Mar 10 12:25:23 PM PDT 24
Peak memory 193488 kb
Host smart-22bd3a66-9dec-49e7-9648-af8a95ac77cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691907137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.691907137
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.2644946206
Short name T641
Test name
Test status
Simulation time 26606517 ps
CPU time 0.57 seconds
Started Mar 10 12:25:29 PM PDT 24
Finished Mar 10 12:25:30 PM PDT 24
Peak memory 193528 kb
Host smart-bb586e2d-f4fc-4121-993b-28fe99d038b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644946206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.2644946206
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.893494302
Short name T694
Test name
Test status
Simulation time 42619911 ps
CPU time 0.56 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 193480 kb
Host smart-a69c4514-d296-4b21-9b15-ba956c4be27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893494302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.893494302
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.1056340372
Short name T696
Test name
Test status
Simulation time 46640451 ps
CPU time 0.54 seconds
Started Mar 10 12:25:10 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 193480 kb
Host smart-4ae30ba3-5a20-4d00-832e-7b611417fdf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056340372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.1056340372
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3070422612
Short name T661
Test name
Test status
Simulation time 36581442 ps
CPU time 0.56 seconds
Started Mar 10 12:25:25 PM PDT 24
Finished Mar 10 12:25:26 PM PDT 24
Peak memory 193536 kb
Host smart-6b24611c-58e9-4921-9c19-5c4624f9ed91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070422612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3070422612
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4078198493
Short name T713
Test name
Test status
Simulation time 29415532 ps
CPU time 0.57 seconds
Started Mar 10 12:25:12 PM PDT 24
Finished Mar 10 12:25:12 PM PDT 24
Peak memory 193596 kb
Host smart-61928a06-d482-4009-b894-e44abad1b105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078198493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4078198493
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2315587333
Short name T102
Test name
Test status
Simulation time 348974178 ps
CPU time 6.05 seconds
Started Mar 10 12:25:43 PM PDT 24
Finished Mar 10 12:25:50 PM PDT 24
Peak memory 198564 kb
Host smart-0578b3c2-948d-4d28-a4d2-845e0226e113
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315587333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2315587333
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.2766781852
Short name T677
Test name
Test status
Simulation time 4388082776 ps
CPU time 15.27 seconds
Started Mar 10 12:24:52 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 197816 kb
Host smart-b1420516-3554-493a-acc7-a0c5dbc061ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766781852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.2766781852
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2742100768
Short name T100
Test name
Test status
Simulation time 18121088 ps
CPU time 0.85 seconds
Started Mar 10 12:25:03 PM PDT 24
Finished Mar 10 12:25:04 PM PDT 24
Peak memory 197348 kb
Host smart-7a96021c-be02-48ba-9fc7-b9c3928eff6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742100768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2742100768
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3300306812
Short name T603
Test name
Test status
Simulation time 79831747 ps
CPU time 1.89 seconds
Started Mar 10 12:25:06 PM PDT 24
Finished Mar 10 12:25:13 PM PDT 24
Peak memory 199108 kb
Host smart-379393e7-b700-4604-90e3-e87ffadb924b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300306812 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3300306812
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2360822689
Short name T615
Test name
Test status
Simulation time 34869166 ps
CPU time 0.69 seconds
Started Mar 10 12:24:51 PM PDT 24
Finished Mar 10 12:24:51 PM PDT 24
Peak memory 195788 kb
Host smart-1ee0286a-4fae-4adb-a3de-92cb4f0c34cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360822689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2360822689
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.3722229584
Short name T634
Test name
Test status
Simulation time 12841158 ps
CPU time 0.57 seconds
Started Mar 10 12:25:21 PM PDT 24
Finished Mar 10 12:25:22 PM PDT 24
Peak memory 193476 kb
Host smart-cd3353bb-9b27-4db9-b5dc-450619ba98ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722229584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.3722229584
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2989426231
Short name T644
Test name
Test status
Simulation time 265639358 ps
CPU time 2.33 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 197884 kb
Host smart-1cae8ba8-0cee-4d49-80d9-b90c596ad038
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989426231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2989426231
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2682950651
Short name T678
Test name
Test status
Simulation time 598008156 ps
CPU time 2.81 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:24:58 PM PDT 24
Peak memory 199384 kb
Host smart-869a6ddc-77eb-48ca-a49e-3fee72e3e90e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682950651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2682950651
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1820769157
Short name T55
Test name
Test status
Simulation time 133054385 ps
CPU time 3.84 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:25:01 PM PDT 24
Peak memory 199036 kb
Host smart-a4f057a2-4b63-4683-ab6d-8af05903ad2a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820769157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1820769157
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.431702752
Short name T718
Test name
Test status
Simulation time 14560519 ps
CPU time 0.6 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 193476 kb
Host smart-e7f36f66-5fae-4209-9841-f77c1aa6caa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431702752 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.431702752
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3354284289
Short name T610
Test name
Test status
Simulation time 51854028 ps
CPU time 0.61 seconds
Started Mar 10 12:25:10 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 193552 kb
Host smart-0151d09b-9cf8-429a-a8f1-b56c08474af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354284289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3354284289
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1489194286
Short name T674
Test name
Test status
Simulation time 24787556 ps
CPU time 0.62 seconds
Started Mar 10 12:25:11 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 193472 kb
Host smart-dbc3c08b-ea1a-4a88-a102-8ea5767800f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489194286 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1489194286
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.2774188020
Short name T599
Test name
Test status
Simulation time 119562899 ps
CPU time 0.6 seconds
Started Mar 10 12:25:33 PM PDT 24
Finished Mar 10 12:25:33 PM PDT 24
Peak memory 193512 kb
Host smart-6da23cb4-6517-4280-ac8b-0c08dbb17e79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774188020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.2774188020
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.1875849521
Short name T665
Test name
Test status
Simulation time 12935874 ps
CPU time 0.54 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 193388 kb
Host smart-df1649cc-855c-4a92-8ee4-d50d92d1b3ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875849521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.1875849521
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1373850472
Short name T658
Test name
Test status
Simulation time 13272506 ps
CPU time 0.57 seconds
Started Mar 10 12:25:10 PM PDT 24
Finished Mar 10 12:25:11 PM PDT 24
Peak memory 193580 kb
Host smart-0af315c0-f76c-4047-bcae-d9944d4e5c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373850472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1373850472
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2164626487
Short name T731
Test name
Test status
Simulation time 58710802 ps
CPU time 0.6 seconds
Started Mar 10 12:25:24 PM PDT 24
Finished Mar 10 12:25:25 PM PDT 24
Peak memory 193440 kb
Host smart-f71b19d4-3b11-4882-884f-451ae45632e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164626487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2164626487
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.2349364618
Short name T722
Test name
Test status
Simulation time 50678064 ps
CPU time 0.58 seconds
Started Mar 10 12:25:22 PM PDT 24
Finished Mar 10 12:25:22 PM PDT 24
Peak memory 193536 kb
Host smart-9299eb24-63e7-4995-b7e8-a7f4265a039c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349364618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.2349364618
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.4232736264
Short name T650
Test name
Test status
Simulation time 12526062 ps
CPU time 0.56 seconds
Started Mar 10 12:25:22 PM PDT 24
Finished Mar 10 12:25:23 PM PDT 24
Peak memory 193464 kb
Host smart-e56710f2-4985-4bf3-a42e-5e670da4c21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232736264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.4232736264
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.463471140
Short name T669
Test name
Test status
Simulation time 69866023 ps
CPU time 0.56 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:09 PM PDT 24
Peak memory 193432 kb
Host smart-601d6791-9805-4ec5-9816-8cb711aeb9bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463471140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.463471140
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.800797078
Short name T705
Test name
Test status
Simulation time 92431813 ps
CPU time 2.23 seconds
Started Mar 10 12:25:34 PM PDT 24
Finished Mar 10 12:25:36 PM PDT 24
Peak memory 199144 kb
Host smart-36ac690d-129d-4f75-914a-31a8134fea5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800797078 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.800797078
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.45541492
Short name T672
Test name
Test status
Simulation time 62021858 ps
CPU time 0.81 seconds
Started Mar 10 12:24:50 PM PDT 24
Finished Mar 10 12:24:51 PM PDT 24
Peak memory 197344 kb
Host smart-ef02442c-cd4b-4c20-9bc6-ee0e51683f33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45541492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.45541492
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2606937799
Short name T732
Test name
Test status
Simulation time 21762543 ps
CPU time 0.59 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 193532 kb
Host smart-25772927-db23-4153-99f9-73fefb0c0f98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606937799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2606937799
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1419229912
Short name T58
Test name
Test status
Simulation time 545013632 ps
CPU time 2.4 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 198872 kb
Host smart-8a619746-704e-4792-bd5c-942c2d1dbd8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419229912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1419229912
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1016721982
Short name T614
Test name
Test status
Simulation time 110954094 ps
CPU time 2.55 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 199076 kb
Host smart-e419afbb-a9b1-4945-9744-02219167ac3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016721982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1016721982
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1375362946
Short name T107
Test name
Test status
Simulation time 903104156 ps
CPU time 4.31 seconds
Started Mar 10 12:25:21 PM PDT 24
Finished Mar 10 12:25:25 PM PDT 24
Peak memory 198956 kb
Host smart-ef624206-3439-4c7a-ad2e-eb6a0b184266
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375362946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1375362946
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.3629149309
Short name T681
Test name
Test status
Simulation time 264080068 ps
CPU time 1.76 seconds
Started Mar 10 12:25:48 PM PDT 24
Finished Mar 10 12:25:50 PM PDT 24
Peak memory 199056 kb
Host smart-f6b89599-1657-45ad-b63f-b766b1e93dec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629149309 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.3629149309
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.4289397757
Short name T656
Test name
Test status
Simulation time 17498570 ps
CPU time 0.66 seconds
Started Mar 10 12:25:27 PM PDT 24
Finished Mar 10 12:25:28 PM PDT 24
Peak memory 196052 kb
Host smart-0090ebf7-96e8-4e6b-9b14-679746077f71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289397757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.4289397757
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3299300667
Short name T618
Test name
Test status
Simulation time 12944449 ps
CPU time 0.61 seconds
Started Mar 10 12:24:56 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 193508 kb
Host smart-7bdfff55-086f-4231-bc88-accbce11a7c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299300667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3299300667
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.1753560453
Short name T635
Test name
Test status
Simulation time 38818994 ps
CPU time 1.68 seconds
Started Mar 10 12:25:44 PM PDT 24
Finished Mar 10 12:25:46 PM PDT 24
Peak memory 198716 kb
Host smart-06f1d45b-d07c-4a9b-adf5-78aff8b2dafa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753560453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.1753560453
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2485462733
Short name T608
Test name
Test status
Simulation time 61047943 ps
CPU time 3.41 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:08 PM PDT 24
Peak memory 199072 kb
Host smart-3879ea5a-af13-443e-8e35-2b6e230f744c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485462733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2485462733
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.250676524
Short name T56
Test name
Test status
Simulation time 146626105 ps
CPU time 1.74 seconds
Started Mar 10 12:25:41 PM PDT 24
Finished Mar 10 12:25:43 PM PDT 24
Peak memory 198988 kb
Host smart-de50e6df-7261-49b6-aa6b-699b5c9ab603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250676524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.250676524
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2681289029
Short name T673
Test name
Test status
Simulation time 24952970 ps
CPU time 1.45 seconds
Started Mar 10 12:25:08 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 198952 kb
Host smart-740f4710-f0ff-4eef-8110-3e3d5634988f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681289029 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2681289029
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.749891343
Short name T602
Test name
Test status
Simulation time 48081326 ps
CPU time 0.67 seconds
Started Mar 10 12:24:50 PM PDT 24
Finished Mar 10 12:24:51 PM PDT 24
Peak memory 196260 kb
Host smart-9b77a0c4-8e8d-4023-a415-f829f6de34a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749891343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.749891343
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.4128535195
Short name T643
Test name
Test status
Simulation time 11255990 ps
CPU time 0.59 seconds
Started Mar 10 12:25:09 PM PDT 24
Finished Mar 10 12:25:10 PM PDT 24
Peak memory 193448 kb
Host smart-63285854-0045-4068-83b4-94f37730165c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128535195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.4128535195
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.3404821299
Short name T638
Test name
Test status
Simulation time 117824239 ps
CPU time 2.41 seconds
Started Mar 10 12:24:53 PM PDT 24
Finished Mar 10 12:24:56 PM PDT 24
Peak memory 198840 kb
Host smart-07709652-0774-4224-8c33-014bc893e5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404821299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.3404821299
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.1353933011
Short name T654
Test name
Test status
Simulation time 686161914 ps
CPU time 2.84 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:04 PM PDT 24
Peak memory 198952 kb
Host smart-bd46b969-fb3d-4b99-9105-0bbb3f373b32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353933011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.1353933011
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.338590141
Short name T623
Test name
Test status
Simulation time 152264674 ps
CPU time 1.51 seconds
Started Mar 10 12:25:00 PM PDT 24
Finished Mar 10 12:25:02 PM PDT 24
Peak memory 198944 kb
Host smart-50b15a95-5e1c-4229-b60f-dce89cc3c0e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338590141 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.338590141
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.560260402
Short name T721
Test name
Test status
Simulation time 246400808 ps
CPU time 0.81 seconds
Started Mar 10 12:25:03 PM PDT 24
Finished Mar 10 12:25:04 PM PDT 24
Peak memory 197848 kb
Host smart-6d917ef2-1465-4f5c-ae75-a125426bb37a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560260402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.560260402
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3014741157
Short name T708
Test name
Test status
Simulation time 46624091 ps
CPU time 0.55 seconds
Started Mar 10 12:24:50 PM PDT 24
Finished Mar 10 12:24:50 PM PDT 24
Peak memory 193472 kb
Host smart-5b484ff7-7f94-4693-b3aa-9c905f6c88a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014741157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3014741157
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1399433351
Short name T725
Test name
Test status
Simulation time 62784099 ps
CPU time 1.27 seconds
Started Mar 10 12:25:04 PM PDT 24
Finished Mar 10 12:25:06 PM PDT 24
Peak memory 197052 kb
Host smart-f004e2cc-72e3-4234-a4d1-c036725ea515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399433351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1399433351
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.4210950525
Short name T682
Test name
Test status
Simulation time 48993323 ps
CPU time 1.67 seconds
Started Mar 10 12:25:05 PM PDT 24
Finished Mar 10 12:25:07 PM PDT 24
Peak memory 199088 kb
Host smart-d730018e-dd18-4565-b4ca-f64266640b41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210950525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.4210950525
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.2750187669
Short name T690
Test name
Test status
Simulation time 83726838 ps
CPU time 1.87 seconds
Started Mar 10 12:24:59 PM PDT 24
Finished Mar 10 12:25:01 PM PDT 24
Peak memory 198912 kb
Host smart-511e11c3-b86c-45e8-80cd-2b737959d14f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750187669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.2750187669
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1017903350
Short name T680
Test name
Test status
Simulation time 66469753320 ps
CPU time 608.51 seconds
Started Mar 10 12:24:54 PM PDT 24
Finished Mar 10 12:35:03 PM PDT 24
Peak memory 215568 kb
Host smart-2e449a58-50c1-4558-a1ed-0ba96ad1019c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017903350 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1017903350
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4234559349
Short name T707
Test name
Test status
Simulation time 56696528 ps
CPU time 0.7 seconds
Started Mar 10 12:24:57 PM PDT 24
Finished Mar 10 12:24:59 PM PDT 24
Peak memory 196116 kb
Host smart-8b1ed4a5-b752-48e0-8541-647ea5da2557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234559349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4234559349
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.177610303
Short name T604
Test name
Test status
Simulation time 16946869 ps
CPU time 0.58 seconds
Started Mar 10 12:24:50 PM PDT 24
Finished Mar 10 12:24:51 PM PDT 24
Peak memory 193472 kb
Host smart-d033a7c7-a8ec-4709-bee9-08fe6efc82ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177610303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.177610303
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2279582629
Short name T710
Test name
Test status
Simulation time 373493494 ps
CPU time 1.76 seconds
Started Mar 10 12:24:55 PM PDT 24
Finished Mar 10 12:24:57 PM PDT 24
Peak memory 199008 kb
Host smart-48d22d77-e842-4b6b-9747-9b7acb365d88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279582629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2279582629
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.1716550412
Short name T733
Test name
Test status
Simulation time 159785735 ps
CPU time 3.77 seconds
Started Mar 10 12:25:01 PM PDT 24
Finished Mar 10 12:25:05 PM PDT 24
Peak memory 198952 kb
Host smart-22666804-abd9-4853-81e1-63b2427ac958
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716550412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.1716550412
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3045364241
Short name T625
Test name
Test status
Simulation time 91669277 ps
CPU time 1.83 seconds
Started Mar 10 12:24:50 PM PDT 24
Finished Mar 10 12:24:51 PM PDT 24
Peak memory 199020 kb
Host smart-06970aec-90fa-41a0-8380-1bcd2b8ca5cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045364241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3045364241
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.3409860799
Short name T490
Test name
Test status
Simulation time 37770809 ps
CPU time 0.56 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:39:13 PM PDT 24
Peak memory 194272 kb
Host smart-b861276c-7102-42ba-8441-b294993b6ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409860799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.3409860799
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.1411147285
Short name T446
Test name
Test status
Simulation time 1250904396 ps
CPU time 41.53 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:40:03 PM PDT 24
Peak memory 216148 kb
Host smart-25a3d8f3-483f-4621-872a-89d621352812
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411147285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.1411147285
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3123633560
Short name T468
Test name
Test status
Simulation time 2096452263 ps
CPU time 32.09 seconds
Started Mar 10 01:39:12 PM PDT 24
Finished Mar 10 01:39:44 PM PDT 24
Peak memory 199888 kb
Host smart-c657f587-86b2-4d15-ae1f-99fa75a35d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123633560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3123633560
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1415619139
Short name T348
Test name
Test status
Simulation time 12452719027 ps
CPU time 42.69 seconds
Started Mar 10 01:39:06 PM PDT 24
Finished Mar 10 01:39:50 PM PDT 24
Peak memory 200028 kb
Host smart-53ff3f46-39b5-4f01-968d-e283c975e2c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1415619139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1415619139
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.3562875134
Short name T444
Test name
Test status
Simulation time 864874377 ps
CPU time 49.38 seconds
Started Mar 10 01:39:11 PM PDT 24
Finished Mar 10 01:40:01 PM PDT 24
Peak memory 199916 kb
Host smart-14fc6246-39d9-49ff-bdf3-462cb7ffdb95
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562875134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.3562875134
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.4206534877
Short name T188
Test name
Test status
Simulation time 5446237998 ps
CPU time 99.05 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:41:00 PM PDT 24
Peak memory 199840 kb
Host smart-afd0e851-69d2-41d0-b7b3-a3b736d3c8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206534877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.4206534877
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.2417872626
Short name T25
Test name
Test status
Simulation time 319206875 ps
CPU time 1.03 seconds
Started Mar 10 01:39:11 PM PDT 24
Finished Mar 10 01:39:12 PM PDT 24
Peak memory 219364 kb
Host smart-aeb7c5df-5bc4-4fcb-af52-02f7c26b8ed0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417872626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.2417872626
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1478344110
Short name T413
Test name
Test status
Simulation time 349072588 ps
CPU time 3.1 seconds
Started Mar 10 01:39:05 PM PDT 24
Finished Mar 10 01:39:09 PM PDT 24
Peak memory 199908 kb
Host smart-7e6a890b-3f12-4a77-af54-1f5ab2ca999e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478344110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1478344110
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2567424038
Short name T520
Test name
Test status
Simulation time 25759315260 ps
CPU time 1488.48 seconds
Started Mar 10 01:39:10 PM PDT 24
Finished Mar 10 02:03:59 PM PDT 24
Peak memory 216356 kb
Host smart-34173f1f-e4d0-4b4f-8b30-e15a96f71b97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567424038 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2567424038
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.92931307
Short name T162
Test name
Test status
Simulation time 586420163 ps
CPU time 0.95 seconds
Started Mar 10 01:39:15 PM PDT 24
Finished Mar 10 01:39:16 PM PDT 24
Peak memory 197988 kb
Host smart-c409341e-b3be-47a9-9a9f-9105ec49bf8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92931307 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 0.hmac_test_hmac_vectors.92931307
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3435419590
Short name T379
Test name
Test status
Simulation time 62641328359 ps
CPU time 526.07 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:47:59 PM PDT 24
Peak memory 200052 kb
Host smart-5ed275da-8a55-4b57-9d35-623e49986832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435419590 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3435419590
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3168051887
Short name T566
Test name
Test status
Simulation time 32806116255 ps
CPU time 33.68 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:39:47 PM PDT 24
Peak memory 200060 kb
Host smart-83b1ae1e-f617-463e-af9f-3a8771aca06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168051887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3168051887
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.4019519942
Short name T545
Test name
Test status
Simulation time 12606021 ps
CPU time 0.57 seconds
Started Mar 10 01:39:15 PM PDT 24
Finished Mar 10 01:39:15 PM PDT 24
Peak memory 194280 kb
Host smart-88334f58-663a-4df0-abd5-8dae3a4153fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019519942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4019519942
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3010712404
Short name T239
Test name
Test status
Simulation time 496317435 ps
CPU time 26.31 seconds
Started Mar 10 01:39:12 PM PDT 24
Finished Mar 10 01:39:38 PM PDT 24
Peak memory 225416 kb
Host smart-b149d047-ca03-44fc-94c1-01ca70296aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010712404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3010712404
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2742340552
Short name T373
Test name
Test status
Simulation time 5332896998 ps
CPU time 29 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 200028 kb
Host smart-1bfa2fc0-bf31-4944-8cd0-a8abe4b3a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742340552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2742340552
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1810404269
Short name T183
Test name
Test status
Simulation time 10317965965 ps
CPU time 157.46 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:41:51 PM PDT 24
Peak memory 199976 kb
Host smart-ea67a841-af38-4b4b-8d29-d23fc6a0f9cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1810404269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1810404269
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1709999071
Short name T155
Test name
Test status
Simulation time 3473670389 ps
CPU time 191.97 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:42:25 PM PDT 24
Peak memory 199900 kb
Host smart-65b4685f-4b8b-482f-a1f7-aded8fe266ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709999071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1709999071
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1424251363
Short name T336
Test name
Test status
Simulation time 7493338516 ps
CPU time 34.09 seconds
Started Mar 10 01:39:14 PM PDT 24
Finished Mar 10 01:39:48 PM PDT 24
Peak memory 199960 kb
Host smart-279ba03d-5eab-421f-a318-0b406299b9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424251363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1424251363
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.3195313741
Short name T32
Test name
Test status
Simulation time 75065197 ps
CPU time 0.83 seconds
Started Mar 10 01:39:12 PM PDT 24
Finished Mar 10 01:39:13 PM PDT 24
Peak memory 218396 kb
Host smart-fc32720f-f43a-43b8-9589-5d1a483fcfc4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195313741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.3195313741
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.3205521103
Short name T456
Test name
Test status
Simulation time 164835379 ps
CPU time 5.1 seconds
Started Mar 10 01:39:11 PM PDT 24
Finished Mar 10 01:39:16 PM PDT 24
Peak memory 199912 kb
Host smart-0d2f82b5-5fee-4c6a-970d-116e18239f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205521103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3205521103
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3879345983
Short name T252
Test name
Test status
Simulation time 13353206596 ps
CPU time 715.08 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:51:09 PM PDT 24
Peak memory 200032 kb
Host smart-50388f19-95ce-4d7c-96c8-eb1054e707a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879345983 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3879345983
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1293572529
Short name T167
Test name
Test status
Simulation time 76094971 ps
CPU time 1.38 seconds
Started Mar 10 01:39:09 PM PDT 24
Finished Mar 10 01:39:11 PM PDT 24
Peak memory 199844 kb
Host smart-a619e6d0-c384-4402-b939-79934b4dc987
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293572529 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.1293572529
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.2581533206
Short name T68
Test name
Test status
Simulation time 24518083983 ps
CPU time 463.91 seconds
Started Mar 10 01:39:15 PM PDT 24
Finished Mar 10 01:46:59 PM PDT 24
Peak memory 200020 kb
Host smart-9b0241f6-45b3-4d43-a389-7bf3b51a203f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581533206 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.2581533206
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1517081994
Short name T291
Test name
Test status
Simulation time 1240779077 ps
CPU time 59.54 seconds
Started Mar 10 01:39:12 PM PDT 24
Finished Mar 10 01:40:12 PM PDT 24
Peak memory 199820 kb
Host smart-6c184e15-31f1-4ad0-9cb2-63fdc30acc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517081994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1517081994
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.1598904158
Short name T433
Test name
Test status
Simulation time 30656569 ps
CPU time 0.56 seconds
Started Mar 10 01:39:38 PM PDT 24
Finished Mar 10 01:39:39 PM PDT 24
Peak memory 194248 kb
Host smart-f255558a-13c6-447d-95af-e197903bcc5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598904158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.1598904158
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.3530875027
Short name T186
Test name
Test status
Simulation time 1890257238 ps
CPU time 20.47 seconds
Started Mar 10 01:39:35 PM PDT 24
Finished Mar 10 01:39:56 PM PDT 24
Peak memory 208092 kb
Host smart-a9f6021f-ffca-4c24-a448-f00ffbb4aee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530875027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.3530875027
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2714887540
Short name T172
Test name
Test status
Simulation time 2639812928 ps
CPU time 30.91 seconds
Started Mar 10 01:39:37 PM PDT 24
Finished Mar 10 01:40:08 PM PDT 24
Peak memory 199972 kb
Host smart-60af6b71-8694-4211-b907-741682af077d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714887540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2714887540
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2093149770
Short name T258
Test name
Test status
Simulation time 7391495874 ps
CPU time 33.93 seconds
Started Mar 10 01:39:35 PM PDT 24
Finished Mar 10 01:40:09 PM PDT 24
Peak memory 199872 kb
Host smart-065be61b-f7c8-49c1-a8d9-89e1371fec6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2093149770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2093149770
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.740087156
Short name T211
Test name
Test status
Simulation time 2262192803 ps
CPU time 122.44 seconds
Started Mar 10 01:39:33 PM PDT 24
Finished Mar 10 01:41:36 PM PDT 24
Peak memory 199964 kb
Host smart-c7dc6fb4-ec95-4cb6-9a94-578500d3a0b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740087156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.740087156
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3890788638
Short name T374
Test name
Test status
Simulation time 8604454274 ps
CPU time 83.29 seconds
Started Mar 10 01:39:34 PM PDT 24
Finished Mar 10 01:40:57 PM PDT 24
Peak memory 200028 kb
Host smart-55269a32-cdcc-4e0a-9674-5bcbd8ae967d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890788638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3890788638
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.992723862
Short name T463
Test name
Test status
Simulation time 206863514 ps
CPU time 6.33 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:46 PM PDT 24
Peak memory 199912 kb
Host smart-31d7a479-c126-4d63-b129-9421dd235e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992723862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.992723862
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.155644198
Short name T266
Test name
Test status
Simulation time 3579761730 ps
CPU time 196.02 seconds
Started Mar 10 01:39:38 PM PDT 24
Finished Mar 10 01:42:55 PM PDT 24
Peak memory 199996 kb
Host smart-e9fa6b0e-a9e9-4dca-a446-ec77cfdfb79d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155644198 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.155644198
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2561727868
Short name T278
Test name
Test status
Simulation time 53813379 ps
CPU time 1.01 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:41 PM PDT 24
Peak memory 198660 kb
Host smart-a9632bdc-0206-4a3b-8b66-edb9eff1d270
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561727868 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2561727868
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.548257589
Short name T567
Test name
Test status
Simulation time 14105347764 ps
CPU time 367.46 seconds
Started Mar 10 01:39:35 PM PDT 24
Finished Mar 10 01:45:43 PM PDT 24
Peak memory 200016 kb
Host smart-99c761b6-07a4-47ff-97ba-cf86328b3d9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548257589 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.548257589
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.4077817204
Short name T187
Test name
Test status
Simulation time 2284572558 ps
CPU time 35.03 seconds
Started Mar 10 01:39:32 PM PDT 24
Finished Mar 10 01:40:07 PM PDT 24
Peak memory 199968 kb
Host smart-8889ffb0-a505-418c-8917-e30148b9e86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077817204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.4077817204
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/108.hmac_stress_all_with_rand_reset.4107819906
Short name T570
Test name
Test status
Simulation time 30222212897 ps
CPU time 813.83 seconds
Started Mar 10 01:43:09 PM PDT 24
Finished Mar 10 01:56:43 PM PDT 24
Peak memory 208260 kb
Host smart-e5312ada-9b72-45f8-89f5-256154a2aa50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4107819906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.hmac_stress_all_with_rand_reset.4107819906
Directory /workspace/108.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3716754771
Short name T216
Test name
Test status
Simulation time 10207885 ps
CPU time 0.56 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:41 PM PDT 24
Peak memory 194308 kb
Host smart-e356a87a-5458-44c0-aeb9-e75ef509d976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716754771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3716754771
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.4232372396
Short name T284
Test name
Test status
Simulation time 1561068749 ps
CPU time 14.21 seconds
Started Mar 10 01:39:38 PM PDT 24
Finished Mar 10 01:39:53 PM PDT 24
Peak memory 208096 kb
Host smart-f86170ea-cc82-472a-afdc-13366bf3bde8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4232372396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.4232372396
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.381636535
Short name T251
Test name
Test status
Simulation time 5668224513 ps
CPU time 23.37 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:40:04 PM PDT 24
Peak memory 200004 kb
Host smart-d9f7d9be-a233-4a96-8596-378c58abaa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381636535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.381636535
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3745064196
Short name T8
Test name
Test status
Simulation time 619175800 ps
CPU time 35.79 seconds
Started Mar 10 01:39:37 PM PDT 24
Finished Mar 10 01:40:13 PM PDT 24
Peak memory 199888 kb
Host smart-52297f24-4d94-42df-8007-f95fdf79499c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3745064196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3745064196
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.2163088162
Short name T149
Test name
Test status
Simulation time 10974273303 ps
CPU time 45.89 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:40:27 PM PDT 24
Peak memory 200028 kb
Host smart-a10fa929-612f-49aa-945d-10ae8f6f6692
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163088162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.2163088162
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1135536215
Short name T306
Test name
Test status
Simulation time 22821501306 ps
CPU time 125.1 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:41:45 PM PDT 24
Peak memory 199964 kb
Host smart-2109a9bc-11a8-4b1b-9718-02e6fc6a3f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135536215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1135536215
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1997670856
Short name T329
Test name
Test status
Simulation time 337502338 ps
CPU time 2.83 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 199912 kb
Host smart-096f11ab-6448-4e3e-b58f-b2841a94a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997670856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1997670856
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.1429302598
Short name T263
Test name
Test status
Simulation time 307386788440 ps
CPU time 2747.86 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 02:25:32 PM PDT 24
Peak memory 241000 kb
Host smart-8888eb4b-9f96-4cc7-be54-37e5523fbebd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429302598 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.1429302598
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.1799763426
Short name T227
Test name
Test status
Simulation time 407192134 ps
CPU time 1.32 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 199772 kb
Host smart-917d53d1-8e6b-4df8-8dd6-39fb12287bc8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799763426 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.1799763426
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.1378727604
Short name T311
Test name
Test status
Simulation time 15324050901 ps
CPU time 446.44 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:47:05 PM PDT 24
Peak memory 199980 kb
Host smart-1dc2dea8-da60-4a9c-aa70-8fa2b9fbf62b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378727604 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.1378727604
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3069324383
Short name T111
Test name
Test status
Simulation time 2742267163 ps
CPU time 37.5 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:40:18 PM PDT 24
Peak memory 199964 kb
Host smart-56b7f8fb-e39e-4ee6-a966-0e66eda08b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069324383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3069324383
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4290625601
Short name T123
Test name
Test status
Simulation time 14226107 ps
CPU time 0.57 seconds
Started Mar 10 01:39:37 PM PDT 24
Finished Mar 10 01:39:38 PM PDT 24
Peak memory 194904 kb
Host smart-e71987c6-5e8b-416d-9a49-2a5de54e4d40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290625601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4290625601
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2871793384
Short name T445
Test name
Test status
Simulation time 2468293442 ps
CPU time 24.79 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:40:04 PM PDT 24
Peak memory 223796 kb
Host smart-abc613a5-d8d1-4849-afb6-4fe3f0642fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2871793384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2871793384
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.29034670
Short name T194
Test name
Test status
Simulation time 178518565 ps
CPU time 2.66 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:39:44 PM PDT 24
Peak memory 199804 kb
Host smart-5f1a8412-8d6d-4095-984e-dd8fd6c5de68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29034670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.29034670
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2132975729
Short name T160
Test name
Test status
Simulation time 196225468 ps
CPU time 11.79 seconds
Started Mar 10 01:39:38 PM PDT 24
Finished Mar 10 01:39:50 PM PDT 24
Peak memory 199928 kb
Host smart-4a777f1d-9213-4661-95e5-27823cafec73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2132975729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2132975729
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3422365503
Short name T378
Test name
Test status
Simulation time 36985233589 ps
CPU time 143.56 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:42:03 PM PDT 24
Peak memory 199972 kb
Host smart-51294cb6-687d-4515-bc5a-f6b75276c5c3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422365503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3422365503
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3558095362
Short name T344
Test name
Test status
Simulation time 465960163 ps
CPU time 6.93 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:39:49 PM PDT 24
Peak memory 199896 kb
Host smart-15dc8ce1-2017-479c-8e3d-c8bfc4aaba35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558095362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3558095362
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.2738711383
Short name T393
Test name
Test status
Simulation time 324510535 ps
CPU time 1.68 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:39:46 PM PDT 24
Peak memory 199840 kb
Host smart-1686fc5b-1958-4ad1-a0d8-0e78517f0730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738711383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.2738711383
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.3205220666
Short name T400
Test name
Test status
Simulation time 390111406 ps
CPU time 1.29 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:39:44 PM PDT 24
Peak memory 199508 kb
Host smart-59afa50c-e1cb-4188-a5ac-712fe5c8437c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205220666 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.hmac_test_hmac_vectors.3205220666
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2592792026
Short name T148
Test name
Test status
Simulation time 33022957852 ps
CPU time 449.66 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:47:10 PM PDT 24
Peak memory 200000 kb
Host smart-cfd75c81-1edf-46d3-8ce2-03e2ce654732
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592792026 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2592792026
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2975086473
Short name T141
Test name
Test status
Simulation time 34774281741 ps
CPU time 33.04 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:40:15 PM PDT 24
Peak memory 200008 kb
Host smart-528e0c23-7497-4b2a-a4c6-a0537bd7cbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975086473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2975086473
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.3379760890
Short name T507
Test name
Test status
Simulation time 15140540 ps
CPU time 0.59 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 194904 kb
Host smart-5d012918-340c-453e-9a3a-4b367a534424
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379760890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.3379760890
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.707709918
Short name T465
Test name
Test status
Simulation time 803099139 ps
CPU time 2.48 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:39:44 PM PDT 24
Peak memory 199868 kb
Host smart-13e98264-6d98-4000-9b7d-f5cceeacb42e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=707709918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.707709918
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1296322457
Short name T585
Test name
Test status
Simulation time 1109158318 ps
CPU time 61.78 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:40:47 PM PDT 24
Peak memory 199932 kb
Host smart-a4ca9441-270c-4db3-a0f1-e7f9e242c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296322457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1296322457
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.3743095109
Short name T158
Test name
Test status
Simulation time 6362209586 ps
CPU time 86.68 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:41:06 PM PDT 24
Peak memory 199928 kb
Host smart-83411a00-eab5-4250-bb95-93c6398b7789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3743095109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.3743095109
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.2817076817
Short name T385
Test name
Test status
Simulation time 7190105283 ps
CPU time 180.44 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:42:42 PM PDT 24
Peak memory 200020 kb
Host smart-2df806d5-39d0-4269-b217-c9d2868b4f60
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817076817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.2817076817
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1959396653
Short name T313
Test name
Test status
Simulation time 888384406 ps
CPU time 14.13 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:39:55 PM PDT 24
Peak memory 199804 kb
Host smart-fe95f90c-1898-4874-aaa4-afcb9f3a4355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959396653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1959396653
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.1161046869
Short name T574
Test name
Test status
Simulation time 56028899 ps
CPU time 1.93 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 199900 kb
Host smart-acc62b67-2966-4989-9df7-f2c475e90c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161046869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.1161046869
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.1769271907
Short name T40
Test name
Test status
Simulation time 164231842231 ps
CPU time 2160.81 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 02:15:42 PM PDT 24
Peak memory 233800 kb
Host smart-a4fcc13c-a622-46a1-8350-4b30373635a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769271907 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.1769271907
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3295148273
Short name T121
Test name
Test status
Simulation time 126202300 ps
CPU time 1.19 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:39:43 PM PDT 24
Peak memory 199864 kb
Host smart-a790eae1-b0ee-421d-85be-fa963a0badea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295148273 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3295148273
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.175552777
Short name T79
Test name
Test status
Simulation time 126961985119 ps
CPU time 439.32 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:47:02 PM PDT 24
Peak memory 200032 kb
Host smart-6a33c1be-a206-409b-97fd-37e5eb452545
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175552777 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.175552777
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.540330282
Short name T522
Test name
Test status
Simulation time 6827003500 ps
CPU time 63.89 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:40:45 PM PDT 24
Peak memory 200024 kb
Host smart-13918312-91b9-484b-9367-d91f557deeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540330282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.540330282
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/134.hmac_stress_all_with_rand_reset.1234280376
Short name T82
Test name
Test status
Simulation time 491137218306 ps
CPU time 6592.55 seconds
Started Mar 10 01:43:22 PM PDT 24
Finished Mar 10 03:33:15 PM PDT 24
Peak memory 265528 kb
Host smart-a539ff18-6d55-4cd2-b790-8668d4e963d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1234280376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.hmac_stress_all_with_rand_reset.1234280376
Directory /workspace/134.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.hmac_alert_test.2491596155
Short name T210
Test name
Test status
Simulation time 18735257 ps
CPU time 0.56 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:39:45 PM PDT 24
Peak memory 194320 kb
Host smart-33a14249-ba57-4c56-a271-6f632b11adae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491596155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.2491596155
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3987161139
Short name T20
Test name
Test status
Simulation time 1256292844 ps
CPU time 51.06 seconds
Started Mar 10 01:39:46 PM PDT 24
Finished Mar 10 01:40:38 PM PDT 24
Peak memory 232692 kb
Host smart-6a3e1ccf-470f-41ab-a200-ae02d07bc8db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3987161139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3987161139
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.2025035782
Short name T414
Test name
Test status
Simulation time 473552165 ps
CPU time 10.87 seconds
Started Mar 10 01:39:46 PM PDT 24
Finished Mar 10 01:39:57 PM PDT 24
Peak memory 199900 kb
Host smart-ca8d2f66-0a6e-4e6d-93dc-3ff108b5ab21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025035782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.2025035782
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1428706312
Short name T272
Test name
Test status
Simulation time 48104187 ps
CPU time 1.98 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:39:45 PM PDT 24
Peak memory 199900 kb
Host smart-4ee48ef0-9855-4ade-b997-bea25cd5065f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428706312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1428706312
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.4227391689
Short name T562
Test name
Test status
Simulation time 40150597588 ps
CPU time 140.47 seconds
Started Mar 10 01:39:52 PM PDT 24
Finished Mar 10 01:42:12 PM PDT 24
Peak memory 200040 kb
Host smart-d1e17832-82a6-4a8e-b8c6-4c90d9901cf9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227391689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.4227391689
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.4131910854
Short name T389
Test name
Test status
Simulation time 259957339 ps
CPU time 16.38 seconds
Started Mar 10 01:39:41 PM PDT 24
Finished Mar 10 01:39:57 PM PDT 24
Peak memory 199884 kb
Host smart-830d8cb2-b04c-4312-9121-e1462751f73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131910854 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.4131910854
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.799374387
Short name T189
Test name
Test status
Simulation time 66098817 ps
CPU time 2.23 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:42 PM PDT 24
Peak memory 199828 kb
Host smart-d3b44a91-0517-4d1b-927b-2e0b792ef35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799374387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.799374387
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.2084535819
Short name T89
Test name
Test status
Simulation time 289413210 ps
CPU time 1.44 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:39:45 PM PDT 24
Peak memory 199640 kb
Host smart-c52c5a6e-684f-444d-9ae8-5eb65f2e8875
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084535819 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.2084535819
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3301545124
Short name T369
Test name
Test status
Simulation time 66370097915 ps
CPU time 479.55 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:47:44 PM PDT 24
Peak memory 199980 kb
Host smart-b97bf79a-a7b4-470d-b841-867b68f333fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301545124 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3301545124
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.3515654937
Short name T151
Test name
Test status
Simulation time 2280925900 ps
CPU time 33.47 seconds
Started Mar 10 01:39:46 PM PDT 24
Finished Mar 10 01:40:20 PM PDT 24
Peak memory 199940 kb
Host smart-6024d7c2-eb83-433e-ae96-e5e1c0f53768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515654937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.3515654937
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.4227579081
Short name T65
Test name
Test status
Simulation time 415487776539 ps
CPU time 1614.99 seconds
Started Mar 10 01:43:26 PM PDT 24
Finished Mar 10 02:10:22 PM PDT 24
Peak memory 258928 kb
Host smart-1ca7fff9-44dd-41fd-b5a5-c9ec1ca2ac2f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4227579081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.4227579081
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/148.hmac_stress_all_with_rand_reset.2181001163
Short name T63
Test name
Test status
Simulation time 39638309820 ps
CPU time 255.08 seconds
Started Mar 10 01:43:26 PM PDT 24
Finished Mar 10 01:47:41 PM PDT 24
Peak memory 215756 kb
Host smart-8d9c23f1-a951-4ca1-8266-7a8ee5fe8945
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2181001163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.hmac_stress_all_with_rand_reset.2181001163
Directory /workspace/148.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3399009093
Short name T51
Test name
Test status
Simulation time 13073072 ps
CPU time 0.58 seconds
Started Mar 10 01:39:45 PM PDT 24
Finished Mar 10 01:39:46 PM PDT 24
Peak memory 194924 kb
Host smart-feb5c116-987f-4e5d-a7ce-e1b104129b21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399009093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3399009093
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.113499067
Short name T478
Test name
Test status
Simulation time 5938746196 ps
CPU time 57.37 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 226924 kb
Host smart-7a9c1b15-6337-4fd1-a9c3-5211b864df72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113499067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.113499067
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1448680936
Short name T253
Test name
Test status
Simulation time 4807544844 ps
CPU time 53.1 seconds
Started Mar 10 01:39:46 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 200016 kb
Host smart-1391e9c4-de46-41fd-a567-e519d9fa5104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448680936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1448680936
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.956701822
Short name T318
Test name
Test status
Simulation time 2577395591 ps
CPU time 74.56 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:40:59 PM PDT 24
Peak memory 199992 kb
Host smart-c0d4a89c-4c85-40dd-b5cf-1d0c4508b58c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956701822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.956701822
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.156976592
Short name T44
Test name
Test status
Simulation time 10518297034 ps
CPU time 146.51 seconds
Started Mar 10 01:39:42 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 200016 kb
Host smart-947ffe0b-1273-485f-bba9-9cc42d96753d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156976592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.156976592
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.892685043
Short name T201
Test name
Test status
Simulation time 2839988708 ps
CPU time 87.81 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:41:13 PM PDT 24
Peak memory 200008 kb
Host smart-2f0c8ad2-5a1b-40fe-9788-5e2c6859d904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892685043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.892685043
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3099044221
Short name T485
Test name
Test status
Simulation time 2831687338 ps
CPU time 5.7 seconds
Started Mar 10 01:39:51 PM PDT 24
Finished Mar 10 01:39:57 PM PDT 24
Peak memory 200004 kb
Host smart-c36a89ad-416e-4304-adfd-f4ad8734c900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099044221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3099044221
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3286660562
Short name T72
Test name
Test status
Simulation time 34522663675 ps
CPU time 492.09 seconds
Started Mar 10 01:39:44 PM PDT 24
Finished Mar 10 01:47:56 PM PDT 24
Peak memory 200052 kb
Host smart-1ef50f23-c5e7-4f69-87f8-ae644e1cf05e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286660562 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3286660562
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1285016906
Short name T547
Test name
Test status
Simulation time 42879280 ps
CPU time 1.06 seconds
Started Mar 10 01:39:52 PM PDT 24
Finished Mar 10 01:39:53 PM PDT 24
Peak memory 198832 kb
Host smart-8d7923d9-980e-4d66-b5d1-bec4abc3098a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285016906 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1285016906
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3453453067
Short name T282
Test name
Test status
Simulation time 43423301032 ps
CPU time 520.2 seconds
Started Mar 10 01:39:47 PM PDT 24
Finished Mar 10 01:48:27 PM PDT 24
Peak memory 199884 kb
Host smart-593e6847-8e1a-41bb-931e-0a791b8b82cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453453067 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3453453067
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2684330697
Short name T396
Test name
Test status
Simulation time 1631461215 ps
CPU time 63.66 seconds
Started Mar 10 01:39:51 PM PDT 24
Finished Mar 10 01:40:55 PM PDT 24
Peak memory 199944 kb
Host smart-ad41c8c3-6fa3-4654-ae6c-08f9eebb4d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684330697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2684330697
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3980585208
Short name T473
Test name
Test status
Simulation time 40265977 ps
CPU time 0.58 seconds
Started Mar 10 01:39:48 PM PDT 24
Finished Mar 10 01:39:49 PM PDT 24
Peak memory 194296 kb
Host smart-af287fb3-f121-4294-8678-c286427e4a44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980585208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3980585208
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1293389623
Short name T49
Test name
Test status
Simulation time 5020641368 ps
CPU time 62.32 seconds
Started Mar 10 01:39:52 PM PDT 24
Finished Mar 10 01:40:54 PM PDT 24
Peak memory 236928 kb
Host smart-7c9e3eb3-e914-4908-bf37-f0046a98de9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293389623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1293389623
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.3656092875
Short name T376
Test name
Test status
Simulation time 1087717450 ps
CPU time 56.34 seconds
Started Mar 10 01:39:46 PM PDT 24
Finished Mar 10 01:40:43 PM PDT 24
Peak memory 199768 kb
Host smart-8c724c14-9d01-41f8-b841-a7ea0e95d06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656092875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.3656092875
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.1241224590
Short name T380
Test name
Test status
Simulation time 1522399357 ps
CPU time 47.87 seconds
Started Mar 10 01:39:43 PM PDT 24
Finished Mar 10 01:40:31 PM PDT 24
Peak memory 199856 kb
Host smart-7ff45669-630b-4d9a-a007-fb7fabd15ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241224590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.1241224590
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.641936001
Short name T517
Test name
Test status
Simulation time 16254012366 ps
CPU time 211.01 seconds
Started Mar 10 01:39:45 PM PDT 24
Finished Mar 10 01:43:17 PM PDT 24
Peak memory 200052 kb
Host smart-b8152f3c-be52-452f-85e7-2bc2a1de2c7c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641936001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.641936001
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3312577031
Short name T417
Test name
Test status
Simulation time 1489893157 ps
CPU time 47.01 seconds
Started Mar 10 01:39:47 PM PDT 24
Finished Mar 10 01:40:34 PM PDT 24
Peak memory 199764 kb
Host smart-0a1a8c5c-6549-4806-8bef-f2616f76fa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312577031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3312577031
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3855396161
Short name T130
Test name
Test status
Simulation time 451442096 ps
CPU time 6.83 seconds
Started Mar 10 01:39:52 PM PDT 24
Finished Mar 10 01:39:59 PM PDT 24
Peak memory 199912 kb
Host smart-c5d37285-5f06-4956-abbb-47bb7d05929a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855396161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3855396161
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3409430121
Short name T198
Test name
Test status
Simulation time 49998922439 ps
CPU time 614.9 seconds
Started Mar 10 01:39:49 PM PDT 24
Finished Mar 10 01:50:04 PM PDT 24
Peak memory 200016 kb
Host smart-fefab319-375c-441a-8836-236d9749f91c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409430121 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3409430121
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2703886035
Short name T178
Test name
Test status
Simulation time 270961481 ps
CPU time 1.02 seconds
Started Mar 10 01:39:50 PM PDT 24
Finished Mar 10 01:39:51 PM PDT 24
Peak memory 197828 kb
Host smart-56ce32cb-dd53-46db-82f0-4187c2cd5f6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703886035 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2703886035
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.1485653027
Short name T191
Test name
Test status
Simulation time 15059601915 ps
CPU time 409.43 seconds
Started Mar 10 01:39:48 PM PDT 24
Finished Mar 10 01:46:38 PM PDT 24
Peak memory 200048 kb
Host smart-65325434-7c51-4a75-b424-ab5e7a705a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485653027 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.1485653027
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3492713088
Short name T514
Test name
Test status
Simulation time 1224807197 ps
CPU time 24.29 seconds
Started Mar 10 01:39:50 PM PDT 24
Finished Mar 10 01:40:14 PM PDT 24
Peak memory 199872 kb
Host smart-c695719e-7730-47e1-bd80-cf51d177f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492713088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3492713088
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1165048839
Short name T381
Test name
Test status
Simulation time 44213306 ps
CPU time 0.59 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:39:55 PM PDT 24
Peak memory 194280 kb
Host smart-3fc61cca-43c6-43b9-88ec-f70b8b723c86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165048839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1165048839
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1899824724
Short name T424
Test name
Test status
Simulation time 1374741523 ps
CPU time 51.1 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:40:46 PM PDT 24
Peak memory 214420 kb
Host smart-2378c0ad-a048-4e7f-a789-976a0793e101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899824724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1899824724
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1334652170
Short name T438
Test name
Test status
Simulation time 803286325 ps
CPU time 18.06 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:40:12 PM PDT 24
Peak memory 199916 kb
Host smart-3ce4d933-900a-4072-b8e3-96c75ca74332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334652170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1334652170
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.1687310175
Short name T159
Test name
Test status
Simulation time 2010193596 ps
CPU time 129.27 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:42:03 PM PDT 24
Peak memory 199908 kb
Host smart-a7e989e7-4422-41ed-955c-cb27d497d6b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687310175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.1687310175
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.765454861
Short name T281
Test name
Test status
Simulation time 3134736300 ps
CPU time 41.98 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:40:36 PM PDT 24
Peak memory 199900 kb
Host smart-798246d5-0a6e-4740-bb90-16e7105d5761
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765454861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.765454861
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.759492520
Short name T156
Test name
Test status
Simulation time 4707242553 ps
CPU time 72.77 seconds
Started Mar 10 01:39:49 PM PDT 24
Finished Mar 10 01:41:02 PM PDT 24
Peak memory 200032 kb
Host smart-be633d3f-cd7f-4970-aa1f-15f22ef6a9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759492520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.759492520
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.3593934393
Short name T138
Test name
Test status
Simulation time 284455765 ps
CPU time 1.17 seconds
Started Mar 10 01:39:47 PM PDT 24
Finished Mar 10 01:39:49 PM PDT 24
Peak memory 199840 kb
Host smart-124fca1d-dd71-492a-961e-d99ca1aff608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593934393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.3593934393
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.1861749921
Short name T474
Test name
Test status
Simulation time 72268284167 ps
CPU time 824.56 seconds
Started Mar 10 01:39:51 PM PDT 24
Finished Mar 10 01:53:36 PM PDT 24
Peak memory 248068 kb
Host smart-79036e10-5800-493c-8108-dc26f0be5142
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861749921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.1861749921
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3958977900
Short name T423
Test name
Test status
Simulation time 255158520 ps
CPU time 1.09 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:39:55 PM PDT 24
Peak memory 198504 kb
Host smart-9358a013-7f56-4fe0-b2df-f6ae2717c20f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958977900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3958977900
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1976418083
Short name T261
Test name
Test status
Simulation time 46346355232 ps
CPU time 619.67 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:50:14 PM PDT 24
Peak memory 200024 kb
Host smart-a00dd359-39d9-4aa3-8855-674173635ffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976418083 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1976418083
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.759150971
Short name T529
Test name
Test status
Simulation time 352537221 ps
CPU time 22.29 seconds
Started Mar 10 01:39:53 PM PDT 24
Finished Mar 10 01:40:16 PM PDT 24
Peak memory 199872 kb
Host smart-e4ed5b8e-0eb1-4b9b-9d2c-a0d815beb667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759150971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.759150971
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/174.hmac_stress_all_with_rand_reset.2267121030
Short name T410
Test name
Test status
Simulation time 73938996732 ps
CPU time 940.92 seconds
Started Mar 10 01:43:49 PM PDT 24
Finished Mar 10 01:59:30 PM PDT 24
Peak memory 236972 kb
Host smart-a19d6069-c5fa-48ff-87cb-28bfe96c79f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2267121030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.hmac_stress_all_with_rand_reset.2267121030
Directory /workspace/174.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.hmac_alert_test.607056495
Short name T262
Test name
Test status
Simulation time 21572366 ps
CPU time 0.58 seconds
Started Mar 10 01:40:01 PM PDT 24
Finished Mar 10 01:40:02 PM PDT 24
Peak memory 194332 kb
Host smart-4577e6dd-902b-43d0-9ecc-c1a2fc384c79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607056495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.607056495
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.1726213614
Short name T399
Test name
Test status
Simulation time 779796718 ps
CPU time 27.8 seconds
Started Mar 10 01:40:01 PM PDT 24
Finished Mar 10 01:40:29 PM PDT 24
Peak memory 208056 kb
Host smart-1368d3d9-866c-4056-b680-47fdedb96ac6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726213614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.1726213614
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.339269525
Short name T134
Test name
Test status
Simulation time 1564300697 ps
CPU time 25.2 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:40:24 PM PDT 24
Peak memory 199812 kb
Host smart-ebd4f0c5-a811-48bd-9c63-465ce2b6ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339269525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.339269525
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1394046241
Short name T165
Test name
Test status
Simulation time 15383378462 ps
CPU time 60.83 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 01:41:01 PM PDT 24
Peak memory 200052 kb
Host smart-620739d8-3884-4f5c-983a-b3ac696372e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1394046241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1394046241
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.914391325
Short name T45
Test name
Test status
Simulation time 3421619955 ps
CPU time 184.58 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 01:43:05 PM PDT 24
Peak memory 199980 kb
Host smart-d349db24-da23-4374-814a-178910c63654
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914391325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.914391325
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.179456039
Short name T124
Test name
Test status
Simulation time 2068346350 ps
CPU time 12.05 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:40:11 PM PDT 24
Peak memory 199836 kb
Host smart-1c31d9b0-def5-4b20-9e2b-982fdcb7acc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179456039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.179456039
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.4262691797
Short name T147
Test name
Test status
Simulation time 2092058046 ps
CPU time 6.92 seconds
Started Mar 10 01:39:54 PM PDT 24
Finished Mar 10 01:40:01 PM PDT 24
Peak memory 199820 kb
Host smart-dc7ed62e-a682-4ad0-9117-054400ea07af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262691797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.4262691797
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.4250435427
Short name T136
Test name
Test status
Simulation time 1042942388 ps
CPU time 63.33 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:41:03 PM PDT 24
Peak memory 199880 kb
Host smart-0cf1a64a-c64f-4b62-a73a-acbc23a8cde0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250435427 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.4250435427
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3165419602
Short name T558
Test name
Test status
Simulation time 51918810 ps
CPU time 1.12 seconds
Started Mar 10 01:39:57 PM PDT 24
Finished Mar 10 01:39:58 PM PDT 24
Peak memory 199100 kb
Host smart-024866cf-2bc5-4f26-aeca-0bacf34eb1fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165419602 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3165419602
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.101090959
Short name T179
Test name
Test status
Simulation time 29100375361 ps
CPU time 420.27 seconds
Started Mar 10 01:39:57 PM PDT 24
Finished Mar 10 01:46:58 PM PDT 24
Peak memory 200088 kb
Host smart-0d8b4b0e-065e-447a-a3cb-abfdeb4c9b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101090959 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.101090959
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.4093346810
Short name T219
Test name
Test status
Simulation time 6485646631 ps
CPU time 94.93 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:41:35 PM PDT 24
Peak memory 199984 kb
Host smart-1c0a5240-37ab-45c8-8d68-61ffe31cf9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093346810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.4093346810
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.1610106067
Short name T586
Test name
Test status
Simulation time 13755513 ps
CPU time 0.61 seconds
Started Mar 10 01:40:03 PM PDT 24
Finished Mar 10 01:40:04 PM PDT 24
Peak memory 194324 kb
Host smart-168d4779-27de-416c-8715-fc0e517faf6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610106067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.1610106067
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3240450219
Short name T415
Test name
Test status
Simulation time 2118924249 ps
CPU time 47.33 seconds
Started Mar 10 01:39:57 PM PDT 24
Finished Mar 10 01:40:45 PM PDT 24
Peak memory 240908 kb
Host smart-acf6885a-b31b-4c67-a316-341b15e81c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3240450219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3240450219
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1346640243
Short name T503
Test name
Test status
Simulation time 1981161533 ps
CPU time 42.19 seconds
Started Mar 10 01:40:01 PM PDT 24
Finished Mar 10 01:40:44 PM PDT 24
Peak memory 199932 kb
Host smart-7df33767-705d-486d-a8c5-8eed932622f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346640243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1346640243
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.1330369175
Short name T137
Test name
Test status
Simulation time 1648420518 ps
CPU time 51.21 seconds
Started Mar 10 01:39:56 PM PDT 24
Finished Mar 10 01:40:47 PM PDT 24
Peak memory 199924 kb
Host smart-64013785-cd73-46fc-96c0-3529efaf012a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1330369175 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.1330369175
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2517206060
Short name T254
Test name
Test status
Simulation time 3327570430 ps
CPU time 26.3 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 01:40:27 PM PDT 24
Peak memory 199968 kb
Host smart-da22eb4d-6385-45fc-b09f-f7ce84c7419f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517206060 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2517206060
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3260744996
Short name T203
Test name
Test status
Simulation time 1062046493 ps
CPU time 65.87 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 01:41:06 PM PDT 24
Peak memory 199880 kb
Host smart-a594fc43-5484-4152-a021-bd4256b6a260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260744996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3260744996
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2217578243
Short name T368
Test name
Test status
Simulation time 314538497 ps
CPU time 4.98 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 01:40:05 PM PDT 24
Peak memory 199872 kb
Host smart-8d74c939-1722-4c22-bbac-2393fa765919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217578243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2217578243
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1737184137
Short name T78
Test name
Test status
Simulation time 119822441874 ps
CPU time 1793.26 seconds
Started Mar 10 01:40:00 PM PDT 24
Finished Mar 10 02:09:53 PM PDT 24
Peak memory 227112 kb
Host smart-15614218-f738-4dd8-83b4-1c9d6aae96f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737184137 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1737184137
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1620485179
Short name T2
Test name
Test status
Simulation time 98626556 ps
CPU time 1.33 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:40:01 PM PDT 24
Peak memory 199664 kb
Host smart-d222bcc1-db0b-4552-88c4-98de86f81ac7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620485179 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.1620485179
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.600385295
Short name T260
Test name
Test status
Simulation time 15568862234 ps
CPU time 449.03 seconds
Started Mar 10 01:39:57 PM PDT 24
Finished Mar 10 01:47:27 PM PDT 24
Peak memory 199996 kb
Host smart-0a7b50c7-f463-47f6-9307-6528b590dacd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600385295 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.600385295
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3077819242
Short name T273
Test name
Test status
Simulation time 285679809 ps
CPU time 18.05 seconds
Started Mar 10 01:39:59 PM PDT 24
Finished Mar 10 01:40:17 PM PDT 24
Peak memory 199912 kb
Host smart-40f45f2c-d5ae-474d-a6c5-7260d3e64200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077819242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3077819242
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/190.hmac_stress_all_with_rand_reset.3869114956
Short name T564
Test name
Test status
Simulation time 200426249059 ps
CPU time 1674.77 seconds
Started Mar 10 01:44:03 PM PDT 24
Finished Mar 10 02:11:58 PM PDT 24
Peak memory 251584 kb
Host smart-f42fee92-9cb5-4b22-9854-32dd09581670
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869114956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.hmac_stress_all_with_rand_reset.3869114956
Directory /workspace/190.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/194.hmac_stress_all_with_rand_reset.2498956975
Short name T14
Test name
Test status
Simulation time 87295736043 ps
CPU time 2017.27 seconds
Started Mar 10 01:44:04 PM PDT 24
Finished Mar 10 02:17:41 PM PDT 24
Peak memory 264912 kb
Host smart-87fbb8ec-1a56-4265-9d11-8de430edcace
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2498956975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.hmac_stress_all_with_rand_reset.2498956975
Directory /workspace/194.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.hmac_alert_test.267771440
Short name T581
Test name
Test status
Simulation time 14024968 ps
CPU time 0.6 seconds
Started Mar 10 01:39:15 PM PDT 24
Finished Mar 10 01:39:15 PM PDT 24
Peak memory 195332 kb
Host smart-757481f3-772b-47cf-aeed-088a6d8ab05d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267771440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.267771440
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.4146877018
Short name T338
Test name
Test status
Simulation time 600819314 ps
CPU time 27.56 seconds
Started Mar 10 01:39:16 PM PDT 24
Finished Mar 10 01:39:43 PM PDT 24
Peak memory 227380 kb
Host smart-266c8cdc-3680-4ad7-a948-98ff323c3d8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146877018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.4146877018
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.580979531
Short name T583
Test name
Test status
Simulation time 881376677 ps
CPU time 40.89 seconds
Started Mar 10 01:39:17 PM PDT 24
Finished Mar 10 01:39:58 PM PDT 24
Peak memory 199920 kb
Host smart-6e8b86ba-2fce-4454-a415-d4fe15ebe466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580979531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.580979531
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.3884160268
Short name T146
Test name
Test status
Simulation time 5123769082 ps
CPU time 178.71 seconds
Started Mar 10 01:39:14 PM PDT 24
Finished Mar 10 01:42:12 PM PDT 24
Peak memory 200008 kb
Host smart-5dc3ae96-dd11-4b9c-8e7c-03790d93cd41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3884160268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.3884160268
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4280571928
Short name T388
Test name
Test status
Simulation time 33669959771 ps
CPU time 155.62 seconds
Started Mar 10 01:39:15 PM PDT 24
Finished Mar 10 01:41:51 PM PDT 24
Peak memory 200048 kb
Host smart-550ebdf6-6fdb-4710-a9b8-3345d5af8e36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280571928 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4280571928
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3809036786
Short name T131
Test name
Test status
Simulation time 2953994552 ps
CPU time 25.02 seconds
Started Mar 10 01:39:11 PM PDT 24
Finished Mar 10 01:39:36 PM PDT 24
Peak memory 199952 kb
Host smart-8b73cf77-6f1a-4bc4-b5a4-2072cf2a05be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809036786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3809036786
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1486448479
Short name T31
Test name
Test status
Simulation time 34921124 ps
CPU time 0.85 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:21 PM PDT 24
Peak memory 217820 kb
Host smart-a232e0e4-cf65-42a3-859f-1ebdfa40c0a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486448479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1486448479
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2514741081
Short name T560
Test name
Test status
Simulation time 48236188 ps
CPU time 1.74 seconds
Started Mar 10 01:39:13 PM PDT 24
Finished Mar 10 01:39:14 PM PDT 24
Peak memory 199864 kb
Host smart-946f311d-06b9-46cf-b0de-82c9ee69858d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514741081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2514741081
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.2513748822
Short name T71
Test name
Test status
Simulation time 25341310934 ps
CPU time 389.37 seconds
Started Mar 10 01:39:18 PM PDT 24
Finished Mar 10 01:45:47 PM PDT 24
Peak memory 247580 kb
Host smart-311b0d41-8ff4-4c17-af44-4e3edf0d019b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513748822 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.2513748822
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.2513553606
Short name T180
Test name
Test status
Simulation time 90807530 ps
CPU time 1.12 seconds
Started Mar 10 01:39:17 PM PDT 24
Finished Mar 10 01:39:18 PM PDT 24
Peak memory 198912 kb
Host smart-9b6eac77-d557-4727-9fa0-95fd6d88874f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513553606 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.2513553606
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2346294647
Short name T555
Test name
Test status
Simulation time 162970150247 ps
CPU time 476.13 seconds
Started Mar 10 01:39:18 PM PDT 24
Finished Mar 10 01:47:14 PM PDT 24
Peak memory 199992 kb
Host smart-61933697-2d62-4b8c-ae50-67a17d7bdec9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346294647 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2346294647
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.171364967
Short name T118
Test name
Test status
Simulation time 7580837745 ps
CPU time 92.57 seconds
Started Mar 10 01:39:17 PM PDT 24
Finished Mar 10 01:40:49 PM PDT 24
Peak memory 200040 kb
Host smart-94432b97-b51f-43f8-b8fd-5716856505f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171364967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.171364967
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.1313980440
Short name T166
Test name
Test status
Simulation time 15838495 ps
CPU time 0.59 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:40:09 PM PDT 24
Peak memory 195336 kb
Host smart-13345f54-7430-47e1-8dd7-498b200e7b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313980440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.1313980440
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2883093966
Short name T195
Test name
Test status
Simulation time 750737325 ps
CPU time 29.78 seconds
Started Mar 10 01:40:08 PM PDT 24
Finished Mar 10 01:40:38 PM PDT 24
Peak memory 217324 kb
Host smart-9789862c-8876-45f4-b28e-888518809515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2883093966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2883093966
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.240290297
Short name T161
Test name
Test status
Simulation time 5125108463 ps
CPU time 68.01 seconds
Started Mar 10 01:40:06 PM PDT 24
Finished Mar 10 01:41:14 PM PDT 24
Peak memory 199892 kb
Host smart-acfd2ebd-5b11-4ba0-92e8-02f7292be6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240290297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.240290297
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3496426352
Short name T312
Test name
Test status
Simulation time 1241226249 ps
CPU time 37.59 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:40:46 PM PDT 24
Peak memory 199904 kb
Host smart-91818fb3-b464-4010-b6ed-9012dd2b7d60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3496426352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3496426352
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1342818323
Short name T397
Test name
Test status
Simulation time 13738395320 ps
CPU time 167.15 seconds
Started Mar 10 01:40:07 PM PDT 24
Finished Mar 10 01:42:54 PM PDT 24
Peak memory 199868 kb
Host smart-dd630441-9691-4b44-af08-8929a7a30cf4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342818323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1342818323
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.2643409053
Short name T87
Test name
Test status
Simulation time 1032620485 ps
CPU time 60.3 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:41:09 PM PDT 24
Peak memory 199848 kb
Host smart-5e009be8-6876-46d4-b192-c560a2e4c7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643409053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.2643409053
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1740772272
Short name T592
Test name
Test status
Simulation time 8127055311 ps
CPU time 6.31 seconds
Started Mar 10 01:40:07 PM PDT 24
Finished Mar 10 01:40:13 PM PDT 24
Peak memory 200004 kb
Host smart-09d05310-111b-47f7-8cb7-7b508885c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740772272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1740772272
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.2739945664
Short name T75
Test name
Test status
Simulation time 108124621007 ps
CPU time 1518.68 seconds
Started Mar 10 01:40:08 PM PDT 24
Finished Mar 10 02:05:27 PM PDT 24
Peak memory 241032 kb
Host smart-60c7a9e7-b649-4b44-a8d8-a41039d23a44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739945664 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.2739945664
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.1628890885
Short name T139
Test name
Test status
Simulation time 473068602 ps
CPU time 1.11 seconds
Started Mar 10 01:40:07 PM PDT 24
Finished Mar 10 01:40:09 PM PDT 24
Peak memory 199004 kb
Host smart-3aaacf2a-c29f-4b24-a20c-b13f43f56d5e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628890885 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.hmac_test_hmac_vectors.1628890885
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3118988595
Short name T431
Test name
Test status
Simulation time 27426632219 ps
CPU time 497.36 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:48:27 PM PDT 24
Peak memory 199960 kb
Host smart-7d0e8436-1331-44f0-97b4-48e2e5a7ba5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118988595 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3118988595
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.425061895
Short name T596
Test name
Test status
Simulation time 3816404498 ps
CPU time 54.37 seconds
Started Mar 10 01:40:05 PM PDT 24
Finished Mar 10 01:41:00 PM PDT 24
Peak memory 199904 kb
Host smart-0ee45d45-eb82-49ea-8987-79deb68fa734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425061895 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.425061895
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2681182006
Short name T117
Test name
Test status
Simulation time 22524602 ps
CPU time 0.57 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:40:15 PM PDT 24
Peak memory 195324 kb
Host smart-cc60a6d1-eee8-484d-8d8d-32b7c0e66a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681182006 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2681182006
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.600695466
Short name T357
Test name
Test status
Simulation time 1515483435 ps
CPU time 61.53 seconds
Started Mar 10 01:40:10 PM PDT 24
Finished Mar 10 01:41:13 PM PDT 24
Peak memory 226884 kb
Host smart-ed8f81af-fcb5-442a-8c33-3e1a517cca07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=600695466 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.600695466
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.678646884
Short name T435
Test name
Test status
Simulation time 4003783878 ps
CPU time 18.9 seconds
Started Mar 10 01:40:08 PM PDT 24
Finished Mar 10 01:40:27 PM PDT 24
Peak memory 199828 kb
Host smart-edd1b6e7-920f-491c-931f-f2da2d5fd594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678646884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.678646884
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1151602565
Short name T83
Test name
Test status
Simulation time 6563712734 ps
CPU time 94.46 seconds
Started Mar 10 01:40:10 PM PDT 24
Finished Mar 10 01:41:46 PM PDT 24
Peak memory 200020 kb
Host smart-87a5e43b-7595-4a86-8db4-da279f7ac9a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1151602565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1151602565
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3858409922
Short name T28
Test name
Test status
Simulation time 45603059477 ps
CPU time 192.71 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:43:22 PM PDT 24
Peak memory 200032 kb
Host smart-f5d108cd-3c63-4c09-b6c0-f87708acc297
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858409922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3858409922
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.752621562
Short name T483
Test name
Test status
Simulation time 2311963210 ps
CPU time 16.71 seconds
Started Mar 10 01:40:09 PM PDT 24
Finished Mar 10 01:40:26 PM PDT 24
Peak memory 199968 kb
Host smart-7c6d95ee-b653-4b97-9a87-310682a671b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752621562 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.752621562
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2949272775
Short name T289
Test name
Test status
Simulation time 22064746 ps
CPU time 0.82 seconds
Started Mar 10 01:40:11 PM PDT 24
Finished Mar 10 01:40:12 PM PDT 24
Peak memory 197752 kb
Host smart-4be672db-46d2-4b25-8a12-d575f2b7b5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949272775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2949272775
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3446235182
Short name T543
Test name
Test status
Simulation time 8075090349 ps
CPU time 192.56 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:43:27 PM PDT 24
Peak memory 199972 kb
Host smart-dd71c4f2-6604-439d-8e24-58ce4f91203a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446235182 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3446235182
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.2476827335
Short name T454
Test name
Test status
Simulation time 111022459 ps
CPU time 1.1 seconds
Started Mar 10 01:40:12 PM PDT 24
Finished Mar 10 01:40:15 PM PDT 24
Peak memory 197604 kb
Host smart-376f5d0e-02d1-4086-92db-1e21d230a3ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476827335 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.2476827335
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.980332712
Short name T304
Test name
Test status
Simulation time 97966000177 ps
CPU time 453.82 seconds
Started Mar 10 01:40:11 PM PDT 24
Finished Mar 10 01:47:46 PM PDT 24
Peak memory 199916 kb
Host smart-c8c25d51-aaa4-416e-8a57-e45cb4c2c8a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980332712 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.980332712
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3510816818
Short name T407
Test name
Test status
Simulation time 2709007723 ps
CPU time 23.22 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:40:38 PM PDT 24
Peak memory 199960 kb
Host smart-60cc8176-49ba-4802-8b9e-807c59e5a09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510816818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3510816818
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.2987427168
Short name T452
Test name
Test status
Simulation time 37224437 ps
CPU time 0.6 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:40:19 PM PDT 24
Peak memory 195300 kb
Host smart-0972a700-52d8-414f-8ced-194f928dad88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987427168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.2987427168
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3000807154
Short name T434
Test name
Test status
Simulation time 565208279 ps
CPU time 21.18 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:40:35 PM PDT 24
Peak memory 216280 kb
Host smart-f8c2dc09-dc0c-4c30-bf1f-f0c4ad6f3fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3000807154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3000807154
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.1563175405
Short name T359
Test name
Test status
Simulation time 4996299218 ps
CPU time 25.37 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 199908 kb
Host smart-dab0b6e9-4eb7-45b0-9521-fb8b20eaad1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563175405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.1563175405
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2467784434
Short name T387
Test name
Test status
Simulation time 3003132220 ps
CPU time 39.73 seconds
Started Mar 10 01:40:13 PM PDT 24
Finished Mar 10 01:40:54 PM PDT 24
Peak memory 199968 kb
Host smart-77ef6c8d-07a1-4c0d-a3c1-72213660528d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2467784434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2467784434
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3517587020
Short name T275
Test name
Test status
Simulation time 1729979146 ps
CPU time 96.93 seconds
Started Mar 10 01:40:16 PM PDT 24
Finished Mar 10 01:41:54 PM PDT 24
Peak memory 199864 kb
Host smart-5ba4a453-882f-4e54-8a50-1d3142254d77
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517587020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3517587020
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3849715103
Short name T288
Test name
Test status
Simulation time 142096544 ps
CPU time 6.57 seconds
Started Mar 10 01:40:15 PM PDT 24
Finished Mar 10 01:40:23 PM PDT 24
Peak memory 199864 kb
Host smart-6071383c-b2ee-47a8-9b49-16c0355396a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849715103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3849715103
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2960524675
Short name T150
Test name
Test status
Simulation time 312670797 ps
CPU time 1.56 seconds
Started Mar 10 01:40:12 PM PDT 24
Finished Mar 10 01:40:16 PM PDT 24
Peak memory 199828 kb
Host smart-2666c4ae-1291-4f6e-8e4a-a86f1e7e0607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960524675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2960524675
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1200724229
Short name T486
Test name
Test status
Simulation time 77044039207 ps
CPU time 1010.96 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:57:09 PM PDT 24
Peak memory 224628 kb
Host smart-0516b193-c72d-4dd1-b9f6-6123a3ca564f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200724229 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1200724229
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.2680500951
Short name T394
Test name
Test status
Simulation time 31319763 ps
CPU time 1.22 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:40:19 PM PDT 24
Peak memory 199900 kb
Host smart-47eda9b6-0ecd-41c7-ba29-ccd65e09e484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680500951 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.2680500951
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.343438152
Short name T409
Test name
Test status
Simulation time 137701914787 ps
CPU time 523.86 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:49:01 PM PDT 24
Peak memory 200056 kb
Host smart-e1218073-ade9-47c8-9bcb-600593d6916f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343438152 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.343438152
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.762235468
Short name T132
Test name
Test status
Simulation time 92240554431 ps
CPU time 81.55 seconds
Started Mar 10 01:40:21 PM PDT 24
Finished Mar 10 01:41:42 PM PDT 24
Peak memory 200056 kb
Host smart-345d2bbc-9c2c-4d83-902b-c57bcdf635a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762235468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.762235468
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.2457355732
Short name T350
Test name
Test status
Simulation time 23580165 ps
CPU time 0.57 seconds
Started Mar 10 01:40:27 PM PDT 24
Finished Mar 10 01:40:28 PM PDT 24
Peak memory 195280 kb
Host smart-ddacfa52-f9c0-4b2c-9972-786585f4d9bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457355732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.2457355732
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1478599497
Short name T21
Test name
Test status
Simulation time 1133158675 ps
CPU time 12.41 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:40:30 PM PDT 24
Peak memory 208796 kb
Host smart-d6df3c3b-fe64-42ae-bdd4-b075845ff549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478599497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1478599497
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.969315663
Short name T500
Test name
Test status
Simulation time 2079040339 ps
CPU time 11.73 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:40:30 PM PDT 24
Peak memory 199752 kb
Host smart-1ff18999-adda-4fb6-8317-3c0a170b63b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969315663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.969315663
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.535434869
Short name T112
Test name
Test status
Simulation time 2258389842 ps
CPU time 65.88 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:41:24 PM PDT 24
Peak memory 199964 kb
Host smart-22e339aa-7a53-433a-b780-f86d6efda1cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=535434869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.535434869
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.1210051511
Short name T464
Test name
Test status
Simulation time 20970124 ps
CPU time 0.69 seconds
Started Mar 10 01:40:20 PM PDT 24
Finished Mar 10 01:40:21 PM PDT 24
Peak memory 195664 kb
Host smart-396a68dd-adae-41f0-8489-7afdd4e44a56
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210051511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.1210051511
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3917092825
Short name T488
Test name
Test status
Simulation time 47644893723 ps
CPU time 102.55 seconds
Started Mar 10 01:40:20 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 199980 kb
Host smart-71067111-4c80-47d6-85be-fa9dd0dc0265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917092825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3917092825
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.159556000
Short name T429
Test name
Test status
Simulation time 353144056 ps
CPU time 4.55 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:40:22 PM PDT 24
Peak memory 199812 kb
Host smart-5d20582c-2fe5-4c98-b5eb-454152af7322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159556000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.159556000
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.667768395
Short name T91
Test name
Test status
Simulation time 25968681833 ps
CPU time 695.03 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:51:53 PM PDT 24
Peak memory 212564 kb
Host smart-81ba94ce-06e6-40ba-82ff-3f3b02af5c75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667768395 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.667768395
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.612967259
Short name T163
Test name
Test status
Simulation time 61587489 ps
CPU time 1.28 seconds
Started Mar 10 01:40:19 PM PDT 24
Finished Mar 10 01:40:21 PM PDT 24
Peak memory 199624 kb
Host smart-c280835e-c970-4060-8061-eddd7d939845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612967259 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.612967259
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1959302833
Short name T114
Test name
Test status
Simulation time 75356488202 ps
CPU time 481.82 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:48:20 PM PDT 24
Peak memory 200040 kb
Host smart-2ba149df-3ce4-4dcb-8747-55307620b2b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959302833 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1959302833
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2931378332
Short name T366
Test name
Test status
Simulation time 1891387988 ps
CPU time 86.05 seconds
Started Mar 10 01:40:17 PM PDT 24
Finished Mar 10 01:41:43 PM PDT 24
Peak memory 199832 kb
Host smart-7987c056-ec70-4cc3-892f-c7bfb89b411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931378332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2931378332
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2673982782
Short name T457
Test name
Test status
Simulation time 12809683 ps
CPU time 0.57 seconds
Started Mar 10 01:40:23 PM PDT 24
Finished Mar 10 01:40:24 PM PDT 24
Peak memory 194904 kb
Host smart-093f68bc-a63e-4ca3-9fb5-f3ec652a37ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673982782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2673982782
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3247521530
Short name T462
Test name
Test status
Simulation time 2671613480 ps
CPU time 35.75 seconds
Started Mar 10 01:40:24 PM PDT 24
Finished Mar 10 01:41:00 PM PDT 24
Peak memory 214672 kb
Host smart-933628ec-0ee1-48dd-9003-bae0b588267b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3247521530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3247521530
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2282975962
Short name T324
Test name
Test status
Simulation time 1044891736 ps
CPU time 54.9 seconds
Started Mar 10 01:40:24 PM PDT 24
Finished Mar 10 01:41:19 PM PDT 24
Peak memory 199876 kb
Host smart-7f0634d3-7e4f-41e5-9171-4af0c349cb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282975962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2282975962
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.426959445
Short name T382
Test name
Test status
Simulation time 1384044846 ps
CPU time 83.5 seconds
Started Mar 10 01:40:24 PM PDT 24
Finished Mar 10 01:41:47 PM PDT 24
Peak memory 199840 kb
Host smart-0c9a2ed0-3de7-48db-9392-83bb0c0b3547
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426959445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.426959445
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.203660176
Short name T422
Test name
Test status
Simulation time 3099446135 ps
CPU time 61.76 seconds
Started Mar 10 01:40:24 PM PDT 24
Finished Mar 10 01:41:26 PM PDT 24
Peak memory 199972 kb
Host smart-6f90a55b-627a-4da2-88cd-39db1f7fc8a3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203660176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.203660176
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1922703127
Short name T532
Test name
Test status
Simulation time 8075859055 ps
CPU time 52.32 seconds
Started Mar 10 01:40:24 PM PDT 24
Finished Mar 10 01:41:17 PM PDT 24
Peak memory 199920 kb
Host smart-e1206fb3-4aa6-4c71-8f37-581fc16ac18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922703127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1922703127
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2493475370
Short name T140
Test name
Test status
Simulation time 307716318 ps
CPU time 4.87 seconds
Started Mar 10 01:40:23 PM PDT 24
Finished Mar 10 01:40:28 PM PDT 24
Peak memory 199936 kb
Host smart-5b28b8d0-c411-4f77-aba7-b942083bffb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493475370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2493475370
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2358760610
Short name T534
Test name
Test status
Simulation time 26642162099 ps
CPU time 166.41 seconds
Started Mar 10 01:40:23 PM PDT 24
Finished Mar 10 01:43:10 PM PDT 24
Peak memory 216468 kb
Host smart-f6c49a0c-7e0c-4cc1-8d64-82c61040ce7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358760610 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2358760610
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.3139914179
Short name T144
Test name
Test status
Simulation time 43537181 ps
CPU time 1.04 seconds
Started Mar 10 01:40:25 PM PDT 24
Finished Mar 10 01:40:26 PM PDT 24
Peak memory 197972 kb
Host smart-bcaf592c-4481-4269-816a-dd21ccbbf36d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139914179 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.3139914179
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3867967831
Short name T85
Test name
Test status
Simulation time 266161836278 ps
CPU time 534.35 seconds
Started Mar 10 01:40:23 PM PDT 24
Finished Mar 10 01:49:18 PM PDT 24
Peak memory 200016 kb
Host smart-225ce755-2ece-4cce-9690-213aacbbb8f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867967831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3867967831
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.719613054
Short name T220
Test name
Test status
Simulation time 1722907526 ps
CPU time 65.96 seconds
Started Mar 10 01:40:23 PM PDT 24
Finished Mar 10 01:41:29 PM PDT 24
Peak memory 199932 kb
Host smart-e3f7f28f-9def-4fe9-b1be-3b29310b1891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719613054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.719613054
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4021410514
Short name T436
Test name
Test status
Simulation time 20213766 ps
CPU time 0.59 seconds
Started Mar 10 01:40:28 PM PDT 24
Finished Mar 10 01:40:28 PM PDT 24
Peak memory 194264 kb
Host smart-2512ab08-ea76-4ae0-be2a-dbe82c18ef67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021410514 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4021410514
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.1709527754
Short name T370
Test name
Test status
Simulation time 906594937 ps
CPU time 11.93 seconds
Started Mar 10 01:40:30 PM PDT 24
Finished Mar 10 01:40:42 PM PDT 24
Peak memory 208088 kb
Host smart-7be959c7-1e58-4241-a653-735b942be389
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709527754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.1709527754
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4073648746
Short name T352
Test name
Test status
Simulation time 3291101845 ps
CPU time 49.7 seconds
Started Mar 10 01:40:28 PM PDT 24
Finished Mar 10 01:41:17 PM PDT 24
Peak memory 199956 kb
Host smart-8e85d23a-c26c-4669-a03b-b811ba59fb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073648746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4073648746
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.1860088344
Short name T283
Test name
Test status
Simulation time 1585951696 ps
CPU time 101.77 seconds
Started Mar 10 01:40:28 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 199888 kb
Host smart-4f0a4b8a-edf2-4039-ba0c-4ed8b8ca2157
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1860088344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.1860088344
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.3278364415
Short name T521
Test name
Test status
Simulation time 7237317026 ps
CPU time 93.48 seconds
Started Mar 10 01:40:29 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 200028 kb
Host smart-3ea44f63-9e4d-485b-8658-5249f15ceef7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278364415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.3278364415
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1426768800
Short name T265
Test name
Test status
Simulation time 108623764 ps
CPU time 2.02 seconds
Started Mar 10 01:40:29 PM PDT 24
Finished Mar 10 01:40:31 PM PDT 24
Peak memory 199832 kb
Host smart-adbc1411-7f36-40ab-ad5d-90e45441be7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426768800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1426768800
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2453184047
Short name T383
Test name
Test status
Simulation time 320930208 ps
CPU time 1.67 seconds
Started Mar 10 01:40:27 PM PDT 24
Finished Mar 10 01:40:29 PM PDT 24
Peak memory 199840 kb
Host smart-a0dbcaa7-758a-4fee-9544-619707a8ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453184047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2453184047
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3179722394
Short name T76
Test name
Test status
Simulation time 1075984723551 ps
CPU time 1583.03 seconds
Started Mar 10 01:40:27 PM PDT 24
Finished Mar 10 02:06:51 PM PDT 24
Peak memory 200040 kb
Host smart-106c2b23-7a60-479e-8b5d-ec751e99e06f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179722394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3179722394
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.549436477
Short name T301
Test name
Test status
Simulation time 53303184 ps
CPU time 1.02 seconds
Started Mar 10 01:40:26 PM PDT 24
Finished Mar 10 01:40:28 PM PDT 24
Peak memory 199044 kb
Host smart-b72105ac-60a9-46e0-8c28-9a360890c440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549436477 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.hmac_test_hmac_vectors.549436477
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.1889881635
Short name T533
Test name
Test status
Simulation time 14325303712 ps
CPU time 426.47 seconds
Started Mar 10 01:40:29 PM PDT 24
Finished Mar 10 01:47:35 PM PDT 24
Peak memory 200060 kb
Host smart-057f0431-7d64-432b-876d-51c402196333
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889881635 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.1889881635
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2729792164
Short name T133
Test name
Test status
Simulation time 10432871401 ps
CPU time 52.8 seconds
Started Mar 10 01:40:26 PM PDT 24
Finished Mar 10 01:41:19 PM PDT 24
Peak memory 200044 kb
Host smart-d461691a-8105-4780-a739-c304e32a2633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729792164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2729792164
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3366467999
Short name T226
Test name
Test status
Simulation time 26556971 ps
CPU time 0.59 seconds
Started Mar 10 01:40:39 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 195280 kb
Host smart-c530c519-b17e-499a-aa22-96deda99ddbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366467999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3366467999
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.3384806372
Short name T390
Test name
Test status
Simulation time 1188299257 ps
CPU time 5.26 seconds
Started Mar 10 01:40:37 PM PDT 24
Finished Mar 10 01:40:42 PM PDT 24
Peak memory 208064 kb
Host smart-c5f88340-37e2-479d-a5a0-ddb66a000575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3384806372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.3384806372
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.3133433374
Short name T448
Test name
Test status
Simulation time 1498456994 ps
CPU time 13.64 seconds
Started Mar 10 01:40:33 PM PDT 24
Finished Mar 10 01:40:47 PM PDT 24
Peak memory 199828 kb
Host smart-bc76b252-e3a4-4929-91db-9221f74b0261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133433374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.3133433374
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4126723934
Short name T419
Test name
Test status
Simulation time 17425826879 ps
CPU time 141.39 seconds
Started Mar 10 01:40:36 PM PDT 24
Finished Mar 10 01:42:58 PM PDT 24
Peak memory 199968 kb
Host smart-57fbc28d-bf1d-4383-9980-76dcaff9fce6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126723934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4126723934
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.2845063247
Short name T257
Test name
Test status
Simulation time 3684518116 ps
CPU time 47.78 seconds
Started Mar 10 01:40:32 PM PDT 24
Finished Mar 10 01:41:20 PM PDT 24
Peak memory 199952 kb
Host smart-1f695e21-8145-487e-a313-a3e100050f80
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845063247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.2845063247
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.1682701467
Short name T466
Test name
Test status
Simulation time 2225948802 ps
CPU time 33.78 seconds
Started Mar 10 01:40:35 PM PDT 24
Finished Mar 10 01:41:09 PM PDT 24
Peak memory 199964 kb
Host smart-e1e9c17f-cddc-4e43-a87d-ae377c53276e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682701467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.1682701467
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.551004176
Short name T319
Test name
Test status
Simulation time 29628213 ps
CPU time 1.13 seconds
Started Mar 10 01:40:34 PM PDT 24
Finished Mar 10 01:40:35 PM PDT 24
Peak memory 199424 kb
Host smart-f3c86187-0d7e-4008-ab0f-8474a4dc674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551004176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.551004176
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3483491605
Short name T29
Test name
Test status
Simulation time 56944877922 ps
CPU time 820.52 seconds
Started Mar 10 01:40:34 PM PDT 24
Finished Mar 10 01:54:15 PM PDT 24
Peak memory 200052 kb
Host smart-ede13f92-c7a1-45ca-9afb-26897542a3c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483491605 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3483491605
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.801870472
Short name T242
Test name
Test status
Simulation time 59816462 ps
CPU time 1.12 seconds
Started Mar 10 01:40:36 PM PDT 24
Finished Mar 10 01:40:37 PM PDT 24
Peak memory 199324 kb
Host smart-dfa1fcfe-90e6-4bee-83e4-29f4630b0571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801870472 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.hmac_test_hmac_vectors.801870472
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.200329895
Short name T207
Test name
Test status
Simulation time 221577802018 ps
CPU time 527.23 seconds
Started Mar 10 01:40:35 PM PDT 24
Finished Mar 10 01:49:22 PM PDT 24
Peak memory 200064 kb
Host smart-46d1d5ee-6e81-4fac-8cea-300cb9bb21b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200329895 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.200329895
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.3434148309
Short name T6
Test name
Test status
Simulation time 12194075652 ps
CPU time 39.94 seconds
Started Mar 10 01:40:33 PM PDT 24
Finished Mar 10 01:41:13 PM PDT 24
Peak memory 200024 kb
Host smart-3a819cff-8bbc-47d3-965d-90ab63a9a629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434148309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3434148309
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.3837641346
Short name T492
Test name
Test status
Simulation time 46246396 ps
CPU time 0.58 seconds
Started Mar 10 01:40:42 PM PDT 24
Finished Mar 10 01:40:42 PM PDT 24
Peak memory 194896 kb
Host smart-879c4d96-310c-46de-be51-4f52b6fc5f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837641346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.3837641346
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4200406504
Short name T48
Test name
Test status
Simulation time 2282006976 ps
CPU time 14.29 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 01:40:53 PM PDT 24
Peak memory 199960 kb
Host smart-33b3722c-bcb9-43c6-9151-ebfecce32252
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4200406504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4200406504
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.459739087
Short name T224
Test name
Test status
Simulation time 3709080995 ps
CPU time 50.74 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 01:41:29 PM PDT 24
Peak memory 199980 kb
Host smart-73237aaf-3510-4092-ba0e-4475aa925f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459739087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.459739087
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.587229050
Short name T365
Test name
Test status
Simulation time 8998984887 ps
CPU time 143.71 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 01:43:02 PM PDT 24
Peak memory 200032 kb
Host smart-fbb7fdd2-8fd5-4ad4-817b-930920ee5f50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587229050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.587229050
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2715202408
Short name T200
Test name
Test status
Simulation time 2240589569 ps
CPU time 134.93 seconds
Started Mar 10 01:40:37 PM PDT 24
Finished Mar 10 01:42:53 PM PDT 24
Peak memory 199976 kb
Host smart-bf357d87-8c8c-4cd8-b90a-7f7af040e69d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715202408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2715202408
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3269558633
Short name T280
Test name
Test status
Simulation time 9414980242 ps
CPU time 81.25 seconds
Started Mar 10 01:40:40 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 199992 kb
Host smart-fa364030-87ba-44cd-a556-a57eed9192a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269558633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3269558633
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2678282702
Short name T367
Test name
Test status
Simulation time 86333682 ps
CPU time 1.09 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 199368 kb
Host smart-be306bae-e05d-41a7-b649-31012d185131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678282702 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2678282702
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2294944952
Short name T295
Test name
Test status
Simulation time 313435662903 ps
CPU time 1186.25 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 02:00:24 PM PDT 24
Peak memory 200012 kb
Host smart-4e744363-b91f-4ec2-874b-5a39bd10b465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294944952 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2294944952
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3316883487
Short name T467
Test name
Test status
Simulation time 172456956 ps
CPU time 1.01 seconds
Started Mar 10 01:40:39 PM PDT 24
Finished Mar 10 01:40:40 PM PDT 24
Peak memory 197488 kb
Host smart-dc4fc62e-6443-4d89-b462-54de1802ff25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316883487 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.3316883487
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.409302796
Short name T267
Test name
Test status
Simulation time 44461918040 ps
CPU time 546.89 seconds
Started Mar 10 01:40:39 PM PDT 24
Finished Mar 10 01:49:46 PM PDT 24
Peak memory 200056 kb
Host smart-d2f43069-5359-48e6-8193-67fb49d0b8d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409302796 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.409302796
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3926224183
Short name T7
Test name
Test status
Simulation time 22554785044 ps
CPU time 78.96 seconds
Started Mar 10 01:40:38 PM PDT 24
Finished Mar 10 01:41:57 PM PDT 24
Peak memory 200040 kb
Host smart-c666db23-0230-4d23-b4dc-bcc6867aeee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926224183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3926224183
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.724713614
Short name T129
Test name
Test status
Simulation time 12996766 ps
CPU time 0.62 seconds
Started Mar 10 01:40:48 PM PDT 24
Finished Mar 10 01:40:49 PM PDT 24
Peak memory 195288 kb
Host smart-9c8ee749-7f3a-4592-8c2c-a89115a9c357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724713614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.724713614
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2574683665
Short name T185
Test name
Test status
Simulation time 1498173725 ps
CPU time 64.44 seconds
Started Mar 10 01:40:44 PM PDT 24
Finished Mar 10 01:41:48 PM PDT 24
Peak memory 224596 kb
Host smart-e414b761-309e-471c-86ac-49e0f2c8aade
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574683665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2574683665
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.2712240129
Short name T115
Test name
Test status
Simulation time 10713677852 ps
CPU time 15.42 seconds
Started Mar 10 01:40:43 PM PDT 24
Finished Mar 10 01:40:58 PM PDT 24
Peak memory 200048 kb
Host smart-068f5d0c-bd84-4602-9e26-d8aa74e893ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712240129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.2712240129
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.3834260046
Short name T511
Test name
Test status
Simulation time 4120303275 ps
CPU time 46.3 seconds
Started Mar 10 01:40:44 PM PDT 24
Finished Mar 10 01:41:30 PM PDT 24
Peak memory 199904 kb
Host smart-bc561b8f-3f74-453f-81d3-80ac907f3a78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834260046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.3834260046
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1883246930
Short name T3
Test name
Test status
Simulation time 21416935237 ps
CPU time 102.78 seconds
Started Mar 10 01:40:44 PM PDT 24
Finished Mar 10 01:42:27 PM PDT 24
Peak memory 200044 kb
Host smart-5c11fca3-9b25-4314-8a5a-2a968c0f601c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883246930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1883246930
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.1104941641
Short name T568
Test name
Test status
Simulation time 1192906275 ps
CPU time 6.37 seconds
Started Mar 10 01:40:44 PM PDT 24
Finished Mar 10 01:40:50 PM PDT 24
Peak memory 199880 kb
Host smart-d8d64326-d2a4-49f0-aa28-bd9392fee1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104941641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.1104941641
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1180182939
Short name T589
Test name
Test status
Simulation time 589763315 ps
CPU time 3.37 seconds
Started Mar 10 01:40:41 PM PDT 24
Finished Mar 10 01:40:45 PM PDT 24
Peak memory 199892 kb
Host smart-14edd44b-a6d4-4db2-bc77-48ac54a7c424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180182939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1180182939
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.3765845199
Short name T460
Test name
Test status
Simulation time 12973689103 ps
CPU time 155.39 seconds
Started Mar 10 01:40:50 PM PDT 24
Finished Mar 10 01:43:25 PM PDT 24
Peak memory 208248 kb
Host smart-74cbef39-0363-44e4-8b4d-248163b56b28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765845199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.3765845199
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.1816645967
Short name T455
Test name
Test status
Simulation time 69601221 ps
CPU time 1.32 seconds
Started Mar 10 01:40:48 PM PDT 24
Finished Mar 10 01:40:50 PM PDT 24
Peak memory 198520 kb
Host smart-cc897040-ac54-405c-bcdd-e6f32c56ee03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816645967 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.1816645967
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1573465417
Short name T411
Test name
Test status
Simulation time 170653931747 ps
CPU time 554.59 seconds
Started Mar 10 01:40:47 PM PDT 24
Finished Mar 10 01:50:02 PM PDT 24
Peak memory 199988 kb
Host smart-5f77f331-f2d5-42e8-b86b-7826b01f9f8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573465417 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1573465417
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4263394804
Short name T152
Test name
Test status
Simulation time 1590057538 ps
CPU time 27.64 seconds
Started Mar 10 01:40:44 PM PDT 24
Finished Mar 10 01:41:12 PM PDT 24
Peak memory 199892 kb
Host smart-64f54ee1-8192-4ff9-a671-f55ef98d0c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263394804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4263394804
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.3692992483
Short name T231
Test name
Test status
Simulation time 14418181 ps
CPU time 0.61 seconds
Started Mar 10 01:40:55 PM PDT 24
Finished Mar 10 01:40:56 PM PDT 24
Peak memory 195352 kb
Host smart-9df25664-13ee-46e6-80ef-6f0d0da796ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692992483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.3692992483
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1748193740
Short name T229
Test name
Test status
Simulation time 4862767925 ps
CPU time 49.55 seconds
Started Mar 10 01:40:52 PM PDT 24
Finished Mar 10 01:41:42 PM PDT 24
Peak memory 226700 kb
Host smart-0430ef6c-09c7-4fd9-9138-4bd3e81a520f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748193740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1748193740
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.2362479085
Short name T549
Test name
Test status
Simulation time 16576854082 ps
CPU time 55.23 seconds
Started Mar 10 01:40:48 PM PDT 24
Finished Mar 10 01:41:44 PM PDT 24
Peak memory 199892 kb
Host smart-98d0f163-c731-4f48-aeac-3300724f14dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362479085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.2362479085
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3537666139
Short name T126
Test name
Test status
Simulation time 1091628516 ps
CPU time 12.61 seconds
Started Mar 10 01:40:52 PM PDT 24
Finished Mar 10 01:41:05 PM PDT 24
Peak memory 199940 kb
Host smart-1b2c9525-286a-40cb-9e32-b7467721cb24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3537666139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3537666139
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2282586572
Short name T321
Test name
Test status
Simulation time 18113003177 ps
CPU time 125.84 seconds
Started Mar 10 01:40:53 PM PDT 24
Finished Mar 10 01:42:58 PM PDT 24
Peak memory 200044 kb
Host smart-346e1ea1-5364-4fb8-bc95-d447f58156f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282586572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2282586572
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.89719638
Short name T375
Test name
Test status
Simulation time 4859985242 ps
CPU time 82.01 seconds
Started Mar 10 01:40:51 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 200048 kb
Host smart-e6cbdd23-0337-408b-a048-2abd991a7731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89719638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.89719638
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2651370547
Short name T120
Test name
Test status
Simulation time 1630489265 ps
CPU time 5.75 seconds
Started Mar 10 01:40:49 PM PDT 24
Finished Mar 10 01:40:55 PM PDT 24
Peak memory 199884 kb
Host smart-d7268ee4-c1ac-476c-9bef-ef2edda4e8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651370547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2651370547
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.3846539250
Short name T17
Test name
Test status
Simulation time 110390841913 ps
CPU time 1432.16 seconds
Started Mar 10 01:40:47 PM PDT 24
Finished Mar 10 02:04:39 PM PDT 24
Peak memory 235940 kb
Host smart-8affde20-e03f-431c-b20b-568b37254da8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846539250 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.3846539250
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1915061348
Short name T402
Test name
Test status
Simulation time 219993958 ps
CPU time 1.09 seconds
Started Mar 10 01:40:50 PM PDT 24
Finished Mar 10 01:40:51 PM PDT 24
Peak memory 198860 kb
Host smart-7ac500e5-8edd-4a51-9afa-ae6c77db4464
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915061348 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1915061348
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.3699408806
Short name T236
Test name
Test status
Simulation time 27389561044 ps
CPU time 491.36 seconds
Started Mar 10 01:40:52 PM PDT 24
Finished Mar 10 01:49:03 PM PDT 24
Peak memory 200044 kb
Host smart-a8de459f-0101-427d-9da4-fb8d0bdb2b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699408806 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.3699408806
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3445068681
Short name T335
Test name
Test status
Simulation time 1062755112 ps
CPU time 8.02 seconds
Started Mar 10 01:40:49 PM PDT 24
Finished Mar 10 01:40:57 PM PDT 24
Peak memory 199872 kb
Host smart-aaddc64e-7751-4515-be9f-36af127513d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445068681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3445068681
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.252966594
Short name T355
Test name
Test status
Simulation time 16275876 ps
CPU time 0.62 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:21 PM PDT 24
Peak memory 195388 kb
Host smart-47a4fa68-610e-4cb8-b1d2-2aa10da8d1e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252966594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.252966594
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2244347510
Short name T332
Test name
Test status
Simulation time 1462182146 ps
CPU time 62.62 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:40:22 PM PDT 24
Peak memory 208072 kb
Host smart-d5cae732-4ca3-4fd5-b0c8-eed8193ec791
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2244347510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2244347510
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3643982550
Short name T243
Test name
Test status
Simulation time 7499060011 ps
CPU time 38.38 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:39:58 PM PDT 24
Peak memory 199984 kb
Host smart-433faea8-efc4-4890-b943-60f8cc78d995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643982550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3643982550
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.564144371
Short name T372
Test name
Test status
Simulation time 58097538 ps
CPU time 3.25 seconds
Started Mar 10 01:39:18 PM PDT 24
Finished Mar 10 01:39:21 PM PDT 24
Peak memory 199908 kb
Host smart-2505aba1-5a49-40c6-b9ae-f4f420e506fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564144371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.564144371
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.3384993337
Short name T536
Test name
Test status
Simulation time 3785746322 ps
CPU time 12.29 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:39:31 PM PDT 24
Peak memory 199840 kb
Host smart-4ba37fb2-8335-4c78-9f7b-145a5476780b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384993337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.3384993337
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2099212997
Short name T248
Test name
Test status
Simulation time 7941904878 ps
CPU time 111.67 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:41:12 PM PDT 24
Peak memory 199984 kb
Host smart-64e6233d-ac91-448f-8831-4876ff781497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099212997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2099212997
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.57305317
Short name T34
Test name
Test status
Simulation time 338983121 ps
CPU time 4.29 seconds
Started Mar 10 01:39:16 PM PDT 24
Finished Mar 10 01:39:20 PM PDT 24
Peak memory 199820 kb
Host smart-7ec0945c-01d8-4d61-9879-9a60206a037e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57305317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.57305317
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.1731782809
Short name T208
Test name
Test status
Simulation time 9883497792 ps
CPU time 549.4 seconds
Started Mar 10 01:39:16 PM PDT 24
Finished Mar 10 01:48:25 PM PDT 24
Peak memory 200104 kb
Host smart-f1c1c595-1c55-4be6-ad8c-e32cd62261fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731782809 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.1731782809
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.674296505
Short name T470
Test name
Test status
Simulation time 248331843 ps
CPU time 1.03 seconds
Started Mar 10 01:39:17 PM PDT 24
Finished Mar 10 01:39:18 PM PDT 24
Peak memory 197952 kb
Host smart-ba89f732-df68-4007-9d5d-cdb1c6803bc1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674296505 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.674296505
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.667441603
Short name T482
Test name
Test status
Simulation time 67868446345 ps
CPU time 500.71 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:47:39 PM PDT 24
Peak memory 200072 kb
Host smart-5fb58c81-acbb-45d5-8e4b-9bb22f215da3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667441603 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.667441603
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.2888442093
Short name T364
Test name
Test status
Simulation time 26320367879 ps
CPU time 55.8 seconds
Started Mar 10 01:39:16 PM PDT 24
Finished Mar 10 01:40:12 PM PDT 24
Peak memory 199980 kb
Host smart-5b2d27f0-faf6-4845-8926-b513ece4d777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888442093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.2888442093
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.897238740
Short name T127
Test name
Test status
Simulation time 17999096 ps
CPU time 0.6 seconds
Started Mar 10 01:40:55 PM PDT 24
Finished Mar 10 01:40:56 PM PDT 24
Peak memory 195356 kb
Host smart-f10ad8e4-fed6-4046-94cc-29ff683e55bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897238740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.897238740
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.3238004839
Short name T506
Test name
Test status
Simulation time 121055596 ps
CPU time 7.87 seconds
Started Mar 10 01:40:56 PM PDT 24
Finished Mar 10 01:41:04 PM PDT 24
Peak memory 220816 kb
Host smart-8bb565d1-8aa6-493f-a877-d2368b24816c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238004839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.3238004839
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.627415024
Short name T197
Test name
Test status
Simulation time 3329618879 ps
CPU time 39.8 seconds
Started Mar 10 01:40:51 PM PDT 24
Finished Mar 10 01:41:30 PM PDT 24
Peak memory 199912 kb
Host smart-24a01604-2f37-492f-a2e8-0ae28e09c457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627415024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.627415024
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.998075554
Short name T323
Test name
Test status
Simulation time 1922017259 ps
CPU time 115.51 seconds
Started Mar 10 01:40:56 PM PDT 24
Finished Mar 10 01:42:52 PM PDT 24
Peak memory 199912 kb
Host smart-d7f34bdc-0ddf-48e0-9742-fb289d0285a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=998075554 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.998075554
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1381173333
Short name T544
Test name
Test status
Simulation time 9849978620 ps
CPU time 144.66 seconds
Started Mar 10 01:40:53 PM PDT 24
Finished Mar 10 01:43:19 PM PDT 24
Peak memory 200028 kb
Host smart-b884de57-d3af-4a9a-b482-149a94a01d0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381173333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1381173333
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.2775908258
Short name T584
Test name
Test status
Simulation time 18711895185 ps
CPU time 79.42 seconds
Started Mar 10 01:40:54 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 199964 kb
Host smart-acae14d2-6dff-4b5e-a57a-bd5bd5ed1d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775908258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.2775908258
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.651848197
Short name T192
Test name
Test status
Simulation time 569395696 ps
CPU time 2.57 seconds
Started Mar 10 01:40:54 PM PDT 24
Finished Mar 10 01:40:57 PM PDT 24
Peak memory 199848 kb
Host smart-15ea0e8c-9c39-43de-8836-89570c57670d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651848197 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.651848197
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.1400859145
Short name T540
Test name
Test status
Simulation time 60245302864 ps
CPU time 1105.19 seconds
Started Mar 10 01:40:54 PM PDT 24
Finished Mar 10 01:59:20 PM PDT 24
Peak memory 248608 kb
Host smart-90dce527-db3a-4ce8-b676-f48383802bed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400859145 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.1400859145
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2406695314
Short name T425
Test name
Test status
Simulation time 816745044 ps
CPU time 1.25 seconds
Started Mar 10 01:40:51 PM PDT 24
Finished Mar 10 01:40:52 PM PDT 24
Peak memory 199420 kb
Host smart-b44431b4-6163-4c17-93c3-82b0e00f400e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406695314 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2406695314
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.2393146894
Short name T588
Test name
Test status
Simulation time 7588638127 ps
CPU time 432.29 seconds
Started Mar 10 01:40:52 PM PDT 24
Finished Mar 10 01:48:04 PM PDT 24
Peak memory 199992 kb
Host smart-9ae0fdc6-0d09-42a8-ade3-5bbe14d39968
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393146894 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.2393146894
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2700850103
Short name T209
Test name
Test status
Simulation time 5451167332 ps
CPU time 105.72 seconds
Started Mar 10 01:40:53 PM PDT 24
Finished Mar 10 01:42:40 PM PDT 24
Peak memory 200024 kb
Host smart-742dc57a-adc9-4eba-b4cf-29b0a20aa65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700850103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2700850103
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.512220260
Short name T300
Test name
Test status
Simulation time 13538247 ps
CPU time 0.61 seconds
Started Mar 10 01:41:02 PM PDT 24
Finished Mar 10 01:41:03 PM PDT 24
Peak memory 195304 kb
Host smart-21cf0636-04e3-42e0-91d0-c38bee59a78c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512220260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.512220260
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3302064132
Short name T546
Test name
Test status
Simulation time 1258338582 ps
CPU time 49.92 seconds
Started Mar 10 01:40:59 PM PDT 24
Finished Mar 10 01:41:49 PM PDT 24
Peak memory 231716 kb
Host smart-328b2eba-13df-4885-9c18-8fa0e48f3c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3302064132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3302064132
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2856288992
Short name T371
Test name
Test status
Simulation time 3329256490 ps
CPU time 16.71 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:41:14 PM PDT 24
Peak memory 199984 kb
Host smart-be204114-2abe-4735-95ea-b22c5b97d370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856288992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2856288992
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2309977937
Short name T196
Test name
Test status
Simulation time 6555022817 ps
CPU time 103.01 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:42:40 PM PDT 24
Peak memory 200048 kb
Host smart-4b4a67be-49e2-4be7-a5f8-790842b8c54b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309977937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2309977937
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3604456587
Short name T19
Test name
Test status
Simulation time 6221027028 ps
CPU time 86.27 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:42:23 PM PDT 24
Peak memory 200024 kb
Host smart-b239cb98-e9a5-4577-bad1-43136ea4a0b6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604456587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3604456587
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.3346074516
Short name T4
Test name
Test status
Simulation time 1936975166 ps
CPU time 34.58 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:41:32 PM PDT 24
Peak memory 199820 kb
Host smart-ad843b6d-498b-4972-9bdb-28adcb4ac943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346074516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.3346074516
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.2635018107
Short name T418
Test name
Test status
Simulation time 461710303 ps
CPU time 6.57 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:41:03 PM PDT 24
Peak memory 199900 kb
Host smart-bf5be9fd-2afd-4965-945d-151bf8c72ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635018107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.2635018107
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.196961175
Short name T268
Test name
Test status
Simulation time 1968925952 ps
CPU time 27.08 seconds
Started Mar 10 01:41:03 PM PDT 24
Finished Mar 10 01:41:30 PM PDT 24
Peak memory 199920 kb
Host smart-41e5cd4c-6ef2-4220-b03d-cc41ec7b1808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196961175 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.196961175
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_stress_all_with_rand_reset.2233843643
Short name T552
Test name
Test status
Simulation time 70835540810 ps
CPU time 1945.95 seconds
Started Mar 10 01:41:05 PM PDT 24
Finished Mar 10 02:13:32 PM PDT 24
Peak memory 241168 kb
Host smart-e06ac6d8-a8cf-4e88-9ca3-341329c57da8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233843643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all_with_rand_reset.2233843643
Directory /workspace/31.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.1978705186
Short name T340
Test name
Test status
Simulation time 88440087 ps
CPU time 1.03 seconds
Started Mar 10 01:41:03 PM PDT 24
Finished Mar 10 01:41:04 PM PDT 24
Peak memory 198920 kb
Host smart-cd450557-3555-45d6-b010-b78fc7067f97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978705186 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.1978705186
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.2936788273
Short name T459
Test name
Test status
Simulation time 7958429662 ps
CPU time 404.17 seconds
Started Mar 10 01:41:06 PM PDT 24
Finished Mar 10 01:47:50 PM PDT 24
Peak memory 200072 kb
Host smart-36361ac8-6a5e-4590-a503-67003582eaff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936788273 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.2936788273
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3997245987
Short name T508
Test name
Test status
Simulation time 6105211107 ps
CPU time 93.09 seconds
Started Mar 10 01:40:57 PM PDT 24
Finished Mar 10 01:42:31 PM PDT 24
Peak memory 200080 kb
Host smart-ee68d68b-698e-41d7-8ed3-1381cf247225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997245987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3997245987
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3566864267
Short name T526
Test name
Test status
Simulation time 12213723 ps
CPU time 0.58 seconds
Started Mar 10 01:41:09 PM PDT 24
Finished Mar 10 01:41:09 PM PDT 24
Peak memory 194308 kb
Host smart-c091b7e0-8d13-4d94-9432-63a69c2b5498
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566864267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3566864267
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2913009063
Short name T290
Test name
Test status
Simulation time 11376487489 ps
CPU time 39.3 seconds
Started Mar 10 01:41:03 PM PDT 24
Finished Mar 10 01:41:43 PM PDT 24
Peak memory 208196 kb
Host smart-a1cfa3d4-79ca-482d-9658-ce4131deab8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2913009063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2913009063
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3716546288
Short name T103
Test name
Test status
Simulation time 1133339148 ps
CPU time 59.31 seconds
Started Mar 10 01:41:02 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 199880 kb
Host smart-055bce52-e646-4430-b2ea-581307df855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716546288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3716546288
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.3487199597
Short name T563
Test name
Test status
Simulation time 3447434009 ps
CPU time 115.32 seconds
Started Mar 10 01:41:03 PM PDT 24
Finished Mar 10 01:42:59 PM PDT 24
Peak memory 199968 kb
Host smart-7035a2cc-544f-4f13-9e44-2088105bc9f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487199597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.3487199597
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3210699612
Short name T174
Test name
Test status
Simulation time 2853691512 ps
CPU time 39.64 seconds
Started Mar 10 01:41:03 PM PDT 24
Finished Mar 10 01:41:43 PM PDT 24
Peak memory 199924 kb
Host smart-53d4e07d-6ac6-4537-bed7-73279df65e96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210699612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3210699612
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3826094653
Short name T481
Test name
Test status
Simulation time 4557951535 ps
CPU time 21.64 seconds
Started Mar 10 01:41:02 PM PDT 24
Finished Mar 10 01:41:24 PM PDT 24
Peak memory 200008 kb
Host smart-e8b94546-815d-4c37-b8da-1da74defd39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826094653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3826094653
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1786891875
Short name T177
Test name
Test status
Simulation time 98401263 ps
CPU time 3.23 seconds
Started Mar 10 01:41:02 PM PDT 24
Finished Mar 10 01:41:05 PM PDT 24
Peak memory 199820 kb
Host smart-a9c9b3db-15e2-498d-9ddf-e4f8c9417cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786891875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1786891875
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3525616167
Short name T561
Test name
Test status
Simulation time 11925796680 ps
CPU time 132.11 seconds
Started Mar 10 01:41:04 PM PDT 24
Finished Mar 10 01:43:17 PM PDT 24
Peak memory 200028 kb
Host smart-004dbf6c-6f41-4040-a225-9cc5b323e168
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525616167 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3525616167
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.857655415
Short name T143
Test name
Test status
Simulation time 530997376 ps
CPU time 1.32 seconds
Started Mar 10 01:41:05 PM PDT 24
Finished Mar 10 01:41:07 PM PDT 24
Peak memory 199680 kb
Host smart-56f103c9-082a-475e-b481-f8de1cf3ab42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857655415 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.857655415
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.3095366572
Short name T279
Test name
Test status
Simulation time 17216992617 ps
CPU time 527.41 seconds
Started Mar 10 01:41:04 PM PDT 24
Finished Mar 10 01:49:52 PM PDT 24
Peak memory 200028 kb
Host smart-7b1150d0-8de9-4ecc-90c4-a354d9e98c4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095366572 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.3095366572
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.1684665208
Short name T27
Test name
Test status
Simulation time 33659368536 ps
CPU time 61.91 seconds
Started Mar 10 01:41:04 PM PDT 24
Finished Mar 10 01:42:06 PM PDT 24
Peak memory 200024 kb
Host smart-2d383713-5ae4-40d4-8f20-9df00e69149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684665208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.1684665208
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2235566142
Short name T116
Test name
Test status
Simulation time 17885833 ps
CPU time 0.6 seconds
Started Mar 10 01:41:13 PM PDT 24
Finished Mar 10 01:41:13 PM PDT 24
Peak memory 195332 kb
Host smart-d01d6b31-b0c4-4c54-995a-00c57f4cf57f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235566142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2235566142
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.4164807217
Short name T299
Test name
Test status
Simulation time 3441265432 ps
CPU time 42.87 seconds
Started Mar 10 01:41:08 PM PDT 24
Finished Mar 10 01:41:51 PM PDT 24
Peak memory 230800 kb
Host smart-2b50c671-7926-4ef0-b726-2fac1e41c99e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4164807217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.4164807217
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.428310351
Short name T241
Test name
Test status
Simulation time 3933652138 ps
CPU time 27.5 seconds
Started Mar 10 01:41:07 PM PDT 24
Finished Mar 10 01:41:35 PM PDT 24
Peak memory 199988 kb
Host smart-98170423-e77e-4e7f-821a-9a4b9a12be38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428310351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.428310351
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1357752612
Short name T401
Test name
Test status
Simulation time 2821230336 ps
CPU time 181.27 seconds
Started Mar 10 01:41:06 PM PDT 24
Finished Mar 10 01:44:08 PM PDT 24
Peak memory 200000 kb
Host smart-491f89c5-f0f3-47a5-b93d-8dc554876e2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1357752612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1357752612
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.3310699750
Short name T42
Test name
Test status
Simulation time 19835880768 ps
CPU time 179.06 seconds
Started Mar 10 01:41:05 PM PDT 24
Finished Mar 10 01:44:04 PM PDT 24
Peak memory 200052 kb
Host smart-88cbfb1a-6966-4ba5-baa7-64655d6c052f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310699750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.3310699750
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3636743115
Short name T556
Test name
Test status
Simulation time 3762321923 ps
CPU time 12.31 seconds
Started Mar 10 01:41:07 PM PDT 24
Finished Mar 10 01:41:20 PM PDT 24
Peak memory 199972 kb
Host smart-01aff751-aca7-4272-8386-92c0e8f3375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636743115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3636743115
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2115925575
Short name T476
Test name
Test status
Simulation time 950081336 ps
CPU time 1.89 seconds
Started Mar 10 01:41:07 PM PDT 24
Finished Mar 10 01:41:09 PM PDT 24
Peak memory 199864 kb
Host smart-66008265-28b6-4fa7-a2c1-45a8e936b911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115925575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2115925575
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1109968945
Short name T73
Test name
Test status
Simulation time 82448726185 ps
CPU time 513.31 seconds
Started Mar 10 01:41:13 PM PDT 24
Finished Mar 10 01:49:46 PM PDT 24
Peak memory 199992 kb
Host smart-1dc4bbb2-39bb-4cb1-992e-414d813d4933
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109968945 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1109968945
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2304279293
Short name T269
Test name
Test status
Simulation time 90665764 ps
CPU time 1.02 seconds
Started Mar 10 01:41:13 PM PDT 24
Finished Mar 10 01:41:14 PM PDT 24
Peak memory 198280 kb
Host smart-7dbad87f-a518-4ed3-8354-bf313bdc594a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304279293 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2304279293
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2069451243
Short name T479
Test name
Test status
Simulation time 67402012218 ps
CPU time 522.4 seconds
Started Mar 10 01:41:08 PM PDT 24
Finished Mar 10 01:49:50 PM PDT 24
Peak memory 200048 kb
Host smart-c77f0c6c-c6cb-4642-8d08-08ee40d66257
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069451243 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2069451243
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2460220217
Short name T524
Test name
Test status
Simulation time 1749362446 ps
CPU time 71.18 seconds
Started Mar 10 01:41:08 PM PDT 24
Finished Mar 10 01:42:19 PM PDT 24
Peak memory 199876 kb
Host smart-2cb31686-2873-435e-a3f3-f6fd270c2ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460220217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2460220217
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.30114580
Short name T86
Test name
Test status
Simulation time 28475009 ps
CPU time 0.59 seconds
Started Mar 10 01:41:19 PM PDT 24
Finished Mar 10 01:41:20 PM PDT 24
Peak memory 195312 kb
Host smart-abb8c631-ea70-42f1-9bed-70256b8339a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.30114580
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2086534116
Short name T469
Test name
Test status
Simulation time 1239736772 ps
CPU time 48.4 seconds
Started Mar 10 01:41:12 PM PDT 24
Finished Mar 10 01:42:00 PM PDT 24
Peak memory 216308 kb
Host smart-ff07385f-f78e-48c0-aa31-34e2c67408ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2086534116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2086534116
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.181019062
Short name T326
Test name
Test status
Simulation time 3062846480 ps
CPU time 31.19 seconds
Started Mar 10 01:41:17 PM PDT 24
Finished Mar 10 01:41:49 PM PDT 24
Peak memory 199964 kb
Host smart-12580b92-f95b-4781-a953-93c17600fb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181019062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.181019062
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3260372531
Short name T250
Test name
Test status
Simulation time 2848570940 ps
CPU time 161.79 seconds
Started Mar 10 01:41:21 PM PDT 24
Finished Mar 10 01:44:04 PM PDT 24
Peak memory 199844 kb
Host smart-be2f7121-26bf-493a-b183-1bf97abd97d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3260372531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3260372531
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1235558327
Short name T228
Test name
Test status
Simulation time 26468239804 ps
CPU time 245.75 seconds
Started Mar 10 01:41:18 PM PDT 24
Finished Mar 10 01:45:25 PM PDT 24
Peak memory 199996 kb
Host smart-5e908731-a3e9-4a1c-957b-493a6dbc3c73
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235558327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1235558327
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3428614851
Short name T565
Test name
Test status
Simulation time 474349908 ps
CPU time 7.41 seconds
Started Mar 10 01:41:13 PM PDT 24
Finished Mar 10 01:41:21 PM PDT 24
Peak memory 199928 kb
Host smart-b2b91c0b-3f55-44b3-a0d8-23e81982c3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428614851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3428614851
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.965456215
Short name T582
Test name
Test status
Simulation time 270442128 ps
CPU time 4.53 seconds
Started Mar 10 01:41:19 PM PDT 24
Finished Mar 10 01:41:24 PM PDT 24
Peak memory 199788 kb
Host smart-b7c6687c-e823-4204-883b-d4def72bfa88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965456215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.965456215
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.4041389357
Short name T206
Test name
Test status
Simulation time 370614347930 ps
CPU time 1730.4 seconds
Started Mar 10 01:41:19 PM PDT 24
Finished Mar 10 02:10:10 PM PDT 24
Peak memory 216364 kb
Host smart-128992f6-8795-4f10-85df-db1561db17a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041389357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.4041389357
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2982562443
Short name T245
Test name
Test status
Simulation time 65613943 ps
CPU time 1.18 seconds
Started Mar 10 01:41:18 PM PDT 24
Finished Mar 10 01:41:20 PM PDT 24
Peak memory 199872 kb
Host smart-0e4c063b-31b2-4bc6-8fdb-81de8e9254e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982562443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2982562443
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.3778593361
Short name T287
Test name
Test status
Simulation time 101309370245 ps
CPU time 481.88 seconds
Started Mar 10 01:41:22 PM PDT 24
Finished Mar 10 01:49:24 PM PDT 24
Peak memory 199908 kb
Host smart-978e3634-cc86-4fec-b6af-d5c2ca7c3659
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778593361 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.3778593361
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1580787347
Short name T298
Test name
Test status
Simulation time 1741269980 ps
CPU time 80.33 seconds
Started Mar 10 01:41:17 PM PDT 24
Finished Mar 10 01:42:38 PM PDT 24
Peak memory 199912 kb
Host smart-04ad26f5-e1f4-4e8d-aa05-50c23fd7089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580787347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1580787347
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2120416260
Short name T153
Test name
Test status
Simulation time 13723829 ps
CPU time 0.57 seconds
Started Mar 10 01:41:23 PM PDT 24
Finished Mar 10 01:41:23 PM PDT 24
Peak memory 194224 kb
Host smart-58377b58-3284-4e8e-9dd3-0952fc488f76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120416260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2120416260
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.579071762
Short name T238
Test name
Test status
Simulation time 159305716 ps
CPU time 6.16 seconds
Started Mar 10 01:41:18 PM PDT 24
Finished Mar 10 01:41:25 PM PDT 24
Peak memory 201948 kb
Host smart-3d59675d-bad0-4e57-91f1-898691ba9321
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579071762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.579071762
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.3913854798
Short name T395
Test name
Test status
Simulation time 3539824946 ps
CPU time 54.54 seconds
Started Mar 10 01:41:22 PM PDT 24
Finished Mar 10 01:42:17 PM PDT 24
Peak memory 199916 kb
Host smart-3ac2527a-7a94-4ee1-98a2-83e0ddde8ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913854798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.3913854798
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.962663069
Short name T475
Test name
Test status
Simulation time 2018685231 ps
CPU time 58.98 seconds
Started Mar 10 01:41:17 PM PDT 24
Finished Mar 10 01:42:17 PM PDT 24
Peak memory 199888 kb
Host smart-2f1d6310-bf0a-4af2-8bb1-060da5b7667f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=962663069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.962663069
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3773850559
Short name T215
Test name
Test status
Simulation time 4670733268 ps
CPU time 85.87 seconds
Started Mar 10 01:41:24 PM PDT 24
Finished Mar 10 01:42:50 PM PDT 24
Peak memory 200044 kb
Host smart-d8e5765c-6b78-46e0-a940-61e41072d6ac
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773850559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3773850559
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.3744219626
Short name T493
Test name
Test status
Simulation time 3042507705 ps
CPU time 45.23 seconds
Started Mar 10 01:41:22 PM PDT 24
Finished Mar 10 01:42:07 PM PDT 24
Peak memory 199796 kb
Host smart-03530350-c983-4548-83c8-6fe60f027777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744219626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.3744219626
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2544239230
Short name T461
Test name
Test status
Simulation time 3021414189 ps
CPU time 6.9 seconds
Started Mar 10 01:41:18 PM PDT 24
Finished Mar 10 01:41:26 PM PDT 24
Peak memory 199956 kb
Host smart-ae5746c1-a93c-45f8-8db8-b385f2d3d615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544239230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2544239230
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.4214476084
Short name T164
Test name
Test status
Simulation time 80837014700 ps
CPU time 880.92 seconds
Started Mar 10 01:41:22 PM PDT 24
Finished Mar 10 01:56:04 PM PDT 24
Peak memory 232832 kb
Host smart-565fbcaf-963c-45da-ac1b-7cebb7a3278d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214476084 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.4214476084
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_stress_all_with_rand_reset.3238725075
Short name T15
Test name
Test status
Simulation time 107620796676 ps
CPU time 644.36 seconds
Started Mar 10 01:41:23 PM PDT 24
Finished Mar 10 01:52:08 PM PDT 24
Peak memory 216536 kb
Host smart-f5b4affb-6e51-4af2-ae6a-d96900241224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3238725075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all_with_rand_reset.3238725075
Directory /workspace/35.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.439037035
Short name T249
Test name
Test status
Simulation time 79530000 ps
CPU time 1.45 seconds
Started Mar 10 01:41:25 PM PDT 24
Finished Mar 10 01:41:26 PM PDT 24
Peak memory 199876 kb
Host smart-7202dd10-7b04-476a-8f68-3b919f0427cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439037035 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.hmac_test_hmac_vectors.439037035
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2429579050
Short name T428
Test name
Test status
Simulation time 152386503625 ps
CPU time 517.54 seconds
Started Mar 10 01:41:26 PM PDT 24
Finished Mar 10 01:50:04 PM PDT 24
Peak memory 200044 kb
Host smart-ceccff61-a983-4fd7-8279-98daf34ea05f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429579050 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2429579050
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.3673310290
Short name T247
Test name
Test status
Simulation time 4211122681 ps
CPU time 33.37 seconds
Started Mar 10 01:41:25 PM PDT 24
Finished Mar 10 01:41:59 PM PDT 24
Peak memory 199964 kb
Host smart-867fe92f-fad1-463d-8c1b-9869f4e6447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673310290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.3673310290
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3340418254
Short name T453
Test name
Test status
Simulation time 40662542 ps
CPU time 0.56 seconds
Started Mar 10 01:41:27 PM PDT 24
Finished Mar 10 01:41:28 PM PDT 24
Peak memory 195288 kb
Host smart-31db3bac-e69d-4efd-b351-0a6ef5412cc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340418254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3340418254
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.1061248104
Short name T193
Test name
Test status
Simulation time 22620898869 ps
CPU time 54.98 seconds
Started Mar 10 01:41:26 PM PDT 24
Finished Mar 10 01:42:21 PM PDT 24
Peak memory 232564 kb
Host smart-21e6bef7-edf2-4338-bdd6-82259a05a53c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1061248104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.1061248104
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.3575235319
Short name T501
Test name
Test status
Simulation time 3502167100 ps
CPU time 56.28 seconds
Started Mar 10 01:41:29 PM PDT 24
Finished Mar 10 01:42:25 PM PDT 24
Peak memory 199924 kb
Host smart-cee50ebf-c174-4c73-9669-ddeabdf41b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575235319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.3575235319
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.243347611
Short name T527
Test name
Test status
Simulation time 244870598 ps
CPU time 14.63 seconds
Started Mar 10 01:41:24 PM PDT 24
Finished Mar 10 01:41:39 PM PDT 24
Peak memory 199840 kb
Host smart-40eca78e-12b1-462f-8489-e3ef6a5f4969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243347611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.243347611
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1790716376
Short name T39
Test name
Test status
Simulation time 16075356953 ps
CPU time 58.56 seconds
Started Mar 10 01:41:23 PM PDT 24
Finished Mar 10 01:42:22 PM PDT 24
Peak memory 200028 kb
Host smart-b27f13fa-c1a3-4e11-b0a4-a6bac35c65a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790716376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1790716376
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.2845753052
Short name T342
Test name
Test status
Simulation time 1506916194 ps
CPU time 92.62 seconds
Started Mar 10 01:41:24 PM PDT 24
Finished Mar 10 01:42:57 PM PDT 24
Peak memory 199880 kb
Host smart-2cb0cda7-91a7-4d09-b029-c65c5f58f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845753052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.2845753052
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.1639334552
Short name T122
Test name
Test status
Simulation time 176845746 ps
CPU time 5.78 seconds
Started Mar 10 01:41:23 PM PDT 24
Finished Mar 10 01:41:29 PM PDT 24
Peak memory 199808 kb
Host smart-49bddcac-10df-463b-8f1c-459ed1aa0b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639334552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1639334552
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.4037446220
Short name T420
Test name
Test status
Simulation time 200447167810 ps
CPU time 949.02 seconds
Started Mar 10 01:41:26 PM PDT 24
Finished Mar 10 01:57:15 PM PDT 24
Peak memory 200032 kb
Host smart-b0bf8ebe-0c21-488f-93a9-463c975bf4cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037446220 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.4037446220
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2983493446
Short name T217
Test name
Test status
Simulation time 45556710 ps
CPU time 1.13 seconds
Started Mar 10 01:41:31 PM PDT 24
Finished Mar 10 01:41:32 PM PDT 24
Peak memory 199048 kb
Host smart-8a7be212-b84b-4e70-bdcd-b4175dddeffc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983493446 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.2983493446
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.1888220410
Short name T322
Test name
Test status
Simulation time 30764293974 ps
CPU time 544.68 seconds
Started Mar 10 01:41:31 PM PDT 24
Finished Mar 10 01:50:35 PM PDT 24
Peak memory 199992 kb
Host smart-cc83cc40-c5d4-455c-9c9f-c2234c31b547
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888220410 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.1888220410
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.325953268
Short name T53
Test name
Test status
Simulation time 653645874 ps
CPU time 25.21 seconds
Started Mar 10 01:41:22 PM PDT 24
Finished Mar 10 01:41:48 PM PDT 24
Peak memory 199824 kb
Host smart-17d9e9e6-95bb-4dcf-85d7-270f83f7049c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325953268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.325953268
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2320225264
Short name T408
Test name
Test status
Simulation time 37740801 ps
CPU time 0.58 seconds
Started Mar 10 01:41:33 PM PDT 24
Finished Mar 10 01:41:33 PM PDT 24
Peak memory 194304 kb
Host smart-2d1ec8c1-7830-4328-a1ec-887f70e53cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320225264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2320225264
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3355810253
Short name T391
Test name
Test status
Simulation time 3765097471 ps
CPU time 30.78 seconds
Started Mar 10 01:41:31 PM PDT 24
Finished Mar 10 01:42:01 PM PDT 24
Peak memory 226592 kb
Host smart-886efd90-0fdc-462f-a557-64e9802226c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3355810253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3355810253
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.745008078
Short name T497
Test name
Test status
Simulation time 7067002548 ps
CPU time 25.01 seconds
Started Mar 10 01:41:31 PM PDT 24
Finished Mar 10 01:41:56 PM PDT 24
Peak memory 200016 kb
Host smart-8c0579a5-1b54-4230-9de3-64dcc75ab795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745008078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.745008078
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.1216164078
Short name T412
Test name
Test status
Simulation time 3096454129 ps
CPU time 24.01 seconds
Started Mar 10 01:41:33 PM PDT 24
Finished Mar 10 01:41:57 PM PDT 24
Peak memory 199988 kb
Host smart-26343dcc-db81-40dd-b710-aafcbefd8bd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216164078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.1216164078
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2691961210
Short name T587
Test name
Test status
Simulation time 47505633151 ps
CPU time 166.78 seconds
Started Mar 10 01:41:27 PM PDT 24
Finished Mar 10 01:44:14 PM PDT 24
Peak memory 200016 kb
Host smart-308e62fd-10f4-4238-ad07-fcb3e88196a8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691961210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2691961210
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.1573767673
Short name T515
Test name
Test status
Simulation time 699909308 ps
CPU time 3.87 seconds
Started Mar 10 01:41:29 PM PDT 24
Finished Mar 10 01:41:33 PM PDT 24
Peak memory 199920 kb
Host smart-a9ab6371-f54a-4df0-b598-2da901007928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573767673 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.1573767673
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2790055482
Short name T84
Test name
Test status
Simulation time 225518331 ps
CPU time 0.82 seconds
Started Mar 10 01:41:28 PM PDT 24
Finished Mar 10 01:41:29 PM PDT 24
Peak memory 196872 kb
Host smart-67eddbac-e91e-44be-8f54-69e7ec232eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790055482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2790055482
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.4127551241
Short name T361
Test name
Test status
Simulation time 23932415490 ps
CPU time 648.26 seconds
Started Mar 10 01:41:32 PM PDT 24
Finished Mar 10 01:52:21 PM PDT 24
Peak memory 200092 kb
Host smart-0f44742f-4fa6-4a5e-a9e4-4dbe216a8e34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127551241 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.4127551241
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2940528972
Short name T302
Test name
Test status
Simulation time 69786530 ps
CPU time 1.28 seconds
Started Mar 10 01:41:33 PM PDT 24
Finished Mar 10 01:41:35 PM PDT 24
Peak memory 199772 kb
Host smart-eee1e80d-2af3-46cd-abcc-2455261b8fc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940528972 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2940528972
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1889708972
Short name T495
Test name
Test status
Simulation time 94323385087 ps
CPU time 445.39 seconds
Started Mar 10 01:41:36 PM PDT 24
Finished Mar 10 01:49:02 PM PDT 24
Peak memory 200036 kb
Host smart-4df382d2-9106-4873-b51a-2ec53c449409
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889708972 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1889708972
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3643627943
Short name T274
Test name
Test status
Simulation time 1063728792 ps
CPU time 3.18 seconds
Started Mar 10 01:41:28 PM PDT 24
Finished Mar 10 01:41:31 PM PDT 24
Peak memory 199872 kb
Host smart-29446f66-bd4b-448e-b4fd-75a6cf0b934d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643627943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3643627943
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.3997656946
Short name T256
Test name
Test status
Simulation time 10671295 ps
CPU time 0.6 seconds
Started Mar 10 01:41:39 PM PDT 24
Finished Mar 10 01:41:40 PM PDT 24
Peak memory 194284 kb
Host smart-817e41eb-1080-40a0-9bd1-049cfa5adcd4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997656946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.3997656946
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2247036481
Short name T518
Test name
Test status
Simulation time 1052032571 ps
CPU time 19.71 seconds
Started Mar 10 01:41:37 PM PDT 24
Finished Mar 10 01:41:57 PM PDT 24
Peak memory 208108 kb
Host smart-11073aac-99b5-4fff-9a46-8e7b743dd617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2247036481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2247036481
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.2846270070
Short name T554
Test name
Test status
Simulation time 3388533214 ps
CPU time 22.76 seconds
Started Mar 10 01:41:34 PM PDT 24
Finished Mar 10 01:41:57 PM PDT 24
Peak memory 200004 kb
Host smart-3e97d90b-0cd1-446a-9c31-bd0a27efa873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846270070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.2846270070
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2824456196
Short name T597
Test name
Test status
Simulation time 1064201206 ps
CPU time 32.34 seconds
Started Mar 10 01:41:34 PM PDT 24
Finished Mar 10 01:42:06 PM PDT 24
Peak memory 199916 kb
Host smart-5d716262-c471-4dcb-823e-818d45342322
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2824456196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2824456196
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3886405920
Short name T244
Test name
Test status
Simulation time 18538763568 ps
CPU time 59.29 seconds
Started Mar 10 01:41:37 PM PDT 24
Finished Mar 10 01:42:37 PM PDT 24
Peak memory 199884 kb
Host smart-69c7451a-da2e-4f30-a4cf-af492cbc011e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886405920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3886405920
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.583659013
Short name T432
Test name
Test status
Simulation time 602408700 ps
CPU time 9.82 seconds
Started Mar 10 01:41:34 PM PDT 24
Finished Mar 10 01:41:44 PM PDT 24
Peak memory 199920 kb
Host smart-de35a75e-8df5-4e1f-9a69-108824f4f859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583659013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.583659013
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1847166172
Short name T168
Test name
Test status
Simulation time 565380127 ps
CPU time 6.87 seconds
Started Mar 10 01:41:32 PM PDT 24
Finished Mar 10 01:41:40 PM PDT 24
Peak memory 199908 kb
Host smart-416c126f-be15-41ca-ab3e-adbb9753f907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847166172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1847166172
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.216710099
Short name T573
Test name
Test status
Simulation time 213704449245 ps
CPU time 1451.61 seconds
Started Mar 10 01:41:39 PM PDT 24
Finished Mar 10 02:05:51 PM PDT 24
Peak memory 208268 kb
Host smart-b8fc0c2e-02ea-4c29-b256-77531dbeb5b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216710099 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.216710099
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.3295910475
Short name T578
Test name
Test status
Simulation time 169712424 ps
CPU time 1.04 seconds
Started Mar 10 01:41:43 PM PDT 24
Finished Mar 10 01:41:44 PM PDT 24
Peak memory 198840 kb
Host smart-d68b9c4b-225e-428b-9fdc-d41be5b6a852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295910475 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.3295910475
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1218442078
Short name T221
Test name
Test status
Simulation time 35443968451 ps
CPU time 543.35 seconds
Started Mar 10 01:41:40 PM PDT 24
Finished Mar 10 01:50:44 PM PDT 24
Peak memory 200072 kb
Host smart-311304f9-7e03-4e7f-9530-a77335b9c6a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218442078 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1218442078
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3383171246
Short name T233
Test name
Test status
Simulation time 7799884665 ps
CPU time 64.08 seconds
Started Mar 10 01:41:37 PM PDT 24
Finished Mar 10 01:42:42 PM PDT 24
Peak memory 200056 kb
Host smart-8b3f36de-2c7b-4d46-bf9f-7d432092cc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383171246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3383171246
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3425205134
Short name T525
Test name
Test status
Simulation time 12386896 ps
CPU time 0.59 seconds
Started Mar 10 01:41:44 PM PDT 24
Finished Mar 10 01:41:45 PM PDT 24
Peak memory 194304 kb
Host smart-4ab13cfd-7ef0-472b-be25-6cbf19ca932e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425205134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3425205134
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.2857867605
Short name T477
Test name
Test status
Simulation time 1155502260 ps
CPU time 42.55 seconds
Started Mar 10 01:41:40 PM PDT 24
Finished Mar 10 01:42:23 PM PDT 24
Peak memory 208112 kb
Host smart-1b67f874-518d-4485-9e88-e177943b27ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857867605 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.2857867605
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.615480585
Short name T591
Test name
Test status
Simulation time 1645432002 ps
CPU time 22.65 seconds
Started Mar 10 01:41:38 PM PDT 24
Finished Mar 10 01:42:01 PM PDT 24
Peak memory 199908 kb
Host smart-846b85dc-d27a-412e-a624-bcf643ee1295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615480585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.615480585
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1071653497
Short name T430
Test name
Test status
Simulation time 644887207 ps
CPU time 39.84 seconds
Started Mar 10 01:41:37 PM PDT 24
Finished Mar 10 01:42:17 PM PDT 24
Peak memory 199852 kb
Host smart-c548e07f-8258-4838-9a2c-90070075f175
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071653497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1071653497
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.958197670
Short name T43
Test name
Test status
Simulation time 1909716187 ps
CPU time 24.06 seconds
Started Mar 10 01:41:48 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 199784 kb
Host smart-f4ebb6a5-6197-4b93-bb44-074c7f61b941
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958197670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.958197670
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.2096962750
Short name T362
Test name
Test status
Simulation time 2552885009 ps
CPU time 35.23 seconds
Started Mar 10 01:41:37 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 199864 kb
Host smart-3ffea9df-b760-427c-bd9d-b3323b11b8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096962750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.2096962750
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.588920666
Short name T542
Test name
Test status
Simulation time 346999191 ps
CPU time 1.58 seconds
Started Mar 10 01:41:39 PM PDT 24
Finished Mar 10 01:41:41 PM PDT 24
Peak memory 199840 kb
Host smart-80fc72c8-c43e-49df-9c8f-5b14fd130847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588920666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.588920666
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3686023627
Short name T441
Test name
Test status
Simulation time 1622264109 ps
CPU time 87.38 seconds
Started Mar 10 01:41:44 PM PDT 24
Finished Mar 10 01:43:12 PM PDT 24
Peak memory 199928 kb
Host smart-ace56752-ca3a-4678-ad2d-2657c64211b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686023627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3686023627
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1154980148
Short name T571
Test name
Test status
Simulation time 89912935 ps
CPU time 1.12 seconds
Started Mar 10 01:41:42 PM PDT 24
Finished Mar 10 01:41:44 PM PDT 24
Peak memory 199092 kb
Host smart-9a87942a-7cdc-447b-a22d-e1fc2222a17b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154980148 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.1154980148
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3541784542
Short name T235
Test name
Test status
Simulation time 36350035789 ps
CPU time 462.25 seconds
Started Mar 10 01:41:41 PM PDT 24
Finished Mar 10 01:49:24 PM PDT 24
Peak memory 200052 kb
Host smart-b8deef6e-c308-4435-85b5-9f8222352e59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541784542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3541784542
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3722850177
Short name T145
Test name
Test status
Simulation time 1785440374 ps
CPU time 37.82 seconds
Started Mar 10 01:41:42 PM PDT 24
Finished Mar 10 01:42:21 PM PDT 24
Peak memory 199924 kb
Host smart-a0b8d179-1e35-41e2-b5fe-374a5f2ab23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722850177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3722850177
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.1407047951
Short name T404
Test name
Test status
Simulation time 22611935 ps
CPU time 0.56 seconds
Started Mar 10 01:39:22 PM PDT 24
Finished Mar 10 01:39:23 PM PDT 24
Peak memory 195296 kb
Host smart-d991df16-8686-42ad-bbe7-e7445a5af56b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407047951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.1407047951
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3776529357
Short name T502
Test name
Test status
Simulation time 6587318381 ps
CPU time 28.65 seconds
Started Mar 10 01:39:22 PM PDT 24
Finished Mar 10 01:39:50 PM PDT 24
Peak memory 208224 kb
Host smart-c1383401-c7ef-41ea-8b9b-e3b7217b805e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776529357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3776529357
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.897160302
Short name T337
Test name
Test status
Simulation time 328579521 ps
CPU time 16.42 seconds
Started Mar 10 01:39:18 PM PDT 24
Finished Mar 10 01:39:35 PM PDT 24
Peak memory 199912 kb
Host smart-f357741c-1f15-4e2c-a538-e4cb1fdcb010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897160302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.897160302
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3536024524
Short name T214
Test name
Test status
Simulation time 960662750 ps
CPU time 51.91 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:40:12 PM PDT 24
Peak memory 199860 kb
Host smart-b5e74b13-898c-47bd-8300-f7ce299ad623
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3536024524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3536024524
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.2613980912
Short name T405
Test name
Test status
Simulation time 408225409 ps
CPU time 24.04 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:39:43 PM PDT 24
Peak memory 199848 kb
Host smart-16c466c3-1b8c-4f24-9702-d0dd21046866
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613980912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.2613980912
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.3586112908
Short name T199
Test name
Test status
Simulation time 23133094149 ps
CPU time 88.41 seconds
Started Mar 10 01:39:18 PM PDT 24
Finished Mar 10 01:40:47 PM PDT 24
Peak memory 200036 kb
Host smart-d55e2e61-8cda-4ac4-b45a-bc1a4eae630a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586112908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.3586112908
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3407688124
Short name T33
Test name
Test status
Simulation time 65360027 ps
CPU time 0.93 seconds
Started Mar 10 01:39:22 PM PDT 24
Finished Mar 10 01:39:23 PM PDT 24
Peak memory 218344 kb
Host smart-cb620b25-6bea-423a-affe-870099792612
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407688124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3407688124
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2084233334
Short name T1
Test name
Test status
Simulation time 27280063 ps
CPU time 0.83 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:21 PM PDT 24
Peak memory 196696 kb
Host smart-aaf69a07-60c4-40ac-a649-289bca60d310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084233334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2084233334
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.505315961
Short name T74
Test name
Test status
Simulation time 22586948300 ps
CPU time 393.74 seconds
Started Mar 10 01:39:23 PM PDT 24
Finished Mar 10 01:45:57 PM PDT 24
Peak memory 232684 kb
Host smart-7115298e-1ca3-4358-b57f-7aa8d0006ba5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505315961 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.505315961
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.1535834911
Short name T204
Test name
Test status
Simulation time 107479109 ps
CPU time 1.24 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:39:20 PM PDT 24
Peak memory 199920 kb
Host smart-ccd40889-0c0d-4790-99e4-9a4d9b4960db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535834911 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.1535834911
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.1429423861
Short name T443
Test name
Test status
Simulation time 127198189961 ps
CPU time 442.3 seconds
Started Mar 10 01:39:17 PM PDT 24
Finished Mar 10 01:46:39 PM PDT 24
Peak memory 200084 kb
Host smart-9d33fe4f-8949-4b1d-9c07-2affbd4b8a8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429423861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.1429423861
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.4086288828
Short name T450
Test name
Test status
Simulation time 7776619342 ps
CPU time 112.83 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:41:13 PM PDT 24
Peak memory 200024 kb
Host smart-09c044d7-fc1b-4b7c-8a9e-3f2fbca1fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086288828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.4086288828
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2746552244
Short name T504
Test name
Test status
Simulation time 21926656 ps
CPU time 0.58 seconds
Started Mar 10 01:41:48 PM PDT 24
Finished Mar 10 01:41:48 PM PDT 24
Peak memory 194908 kb
Host smart-0a2343ce-8abe-42a8-a3b7-bf046d6011d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746552244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2746552244
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.872474433
Short name T406
Test name
Test status
Simulation time 1550885512 ps
CPU time 14.82 seconds
Started Mar 10 01:41:54 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 231472 kb
Host smart-1f0643ac-d986-4f0d-9461-c7632c741d85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872474433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.872474433
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.3118385354
Short name T81
Test name
Test status
Simulation time 5158902873 ps
CPU time 18.58 seconds
Started Mar 10 01:41:48 PM PDT 24
Finished Mar 10 01:42:07 PM PDT 24
Peak memory 200024 kb
Host smart-943cfdd8-790d-433f-9e19-c1feb451a5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118385354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.3118385354
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.2552266141
Short name T440
Test name
Test status
Simulation time 683379249 ps
CPU time 39.98 seconds
Started Mar 10 01:41:50 PM PDT 24
Finished Mar 10 01:42:30 PM PDT 24
Peak memory 199888 kb
Host smart-fc0ce59c-3571-4f65-85c0-34582009503c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552266141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.2552266141
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2044776015
Short name T354
Test name
Test status
Simulation time 6309227293 ps
CPU time 181.34 seconds
Started Mar 10 01:41:47 PM PDT 24
Finished Mar 10 01:44:49 PM PDT 24
Peak memory 200036 kb
Host smart-bf9f718a-5d48-4dca-9ecb-8cb6fe5fbb6d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044776015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2044776015
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2407350058
Short name T472
Test name
Test status
Simulation time 1237887006 ps
CPU time 68.45 seconds
Started Mar 10 01:41:41 PM PDT 24
Finished Mar 10 01:42:50 PM PDT 24
Peak memory 199888 kb
Host smart-ef631795-604d-4058-81e6-5523e035ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407350058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2407350058
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1306608869
Short name T316
Test name
Test status
Simulation time 42631681 ps
CPU time 1.53 seconds
Started Mar 10 01:41:41 PM PDT 24
Finished Mar 10 01:41:43 PM PDT 24
Peak memory 199876 kb
Host smart-e906a9f7-dc5e-4207-88f6-e5aadc6fecc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306608869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1306608869
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.1188109140
Short name T37
Test name
Test status
Simulation time 312327605167 ps
CPU time 991.1 seconds
Started Mar 10 01:41:54 PM PDT 24
Finished Mar 10 01:58:25 PM PDT 24
Peak memory 235600 kb
Host smart-e7c3fce3-dcd5-4ee0-bdc2-06cf58a8d2e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188109140 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.1188109140
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3225506160
Short name T223
Test name
Test status
Simulation time 134072182 ps
CPU time 1.34 seconds
Started Mar 10 01:41:52 PM PDT 24
Finished Mar 10 01:41:53 PM PDT 24
Peak memory 199188 kb
Host smart-59fe27cd-a195-45b7-9ee9-affae221bae4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225506160 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3225506160
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.457981953
Short name T169
Test name
Test status
Simulation time 140524476414 ps
CPU time 473.97 seconds
Started Mar 10 01:41:50 PM PDT 24
Finished Mar 10 01:49:44 PM PDT 24
Peak memory 200048 kb
Host smart-bc4cdca0-39c7-450c-9b6d-0bb7cc9668d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457981953 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.457981953
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.1712894915
Short name T384
Test name
Test status
Simulation time 13458229464 ps
CPU time 55.39 seconds
Started Mar 10 01:41:50 PM PDT 24
Finished Mar 10 01:42:46 PM PDT 24
Peak memory 199940 kb
Host smart-1feabb68-9437-4d3b-864f-fece5ff0fe96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712894915 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.1712894915
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1249780626
Short name T505
Test name
Test status
Simulation time 48528238 ps
CPU time 0.61 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:41:53 PM PDT 24
Peak memory 195228 kb
Host smart-dd8e276f-4d5a-4174-9b47-24d29e619f5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249780626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1249780626
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3896500278
Short name T349
Test name
Test status
Simulation time 1051509524 ps
CPU time 35.25 seconds
Started Mar 10 01:41:49 PM PDT 24
Finished Mar 10 01:42:24 PM PDT 24
Peak memory 208080 kb
Host smart-4983b281-b56d-4680-a071-0f99339bd275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3896500278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3896500278
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.3875151043
Short name T491
Test name
Test status
Simulation time 935774309 ps
CPU time 42.98 seconds
Started Mar 10 01:41:50 PM PDT 24
Finished Mar 10 01:42:33 PM PDT 24
Peak memory 199820 kb
Host smart-113370e4-50d0-4a2b-b3e9-0e7223dc5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875151043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.3875151043
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.772019751
Short name T580
Test name
Test status
Simulation time 2833201493 ps
CPU time 48.64 seconds
Started Mar 10 01:41:48 PM PDT 24
Finished Mar 10 01:42:36 PM PDT 24
Peak memory 199936 kb
Host smart-2f49b532-d729-49de-b4a5-de941124361b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772019751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.772019751
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.38945651
Short name T351
Test name
Test status
Simulation time 1166629620 ps
CPU time 16.56 seconds
Started Mar 10 01:41:54 PM PDT 24
Finished Mar 10 01:42:10 PM PDT 24
Peak memory 199900 kb
Host smart-03ca44af-f878-48a4-be2e-a472dba09097
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38945651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.38945651
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3873280185
Short name T35
Test name
Test status
Simulation time 2896836043 ps
CPU time 53.79 seconds
Started Mar 10 01:41:54 PM PDT 24
Finished Mar 10 01:42:48 PM PDT 24
Peak memory 199668 kb
Host smart-7c7ee46c-8f34-4fa1-8814-6c26fcde3eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873280185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3873280185
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.720385901
Short name T170
Test name
Test status
Simulation time 516885127 ps
CPU time 3.98 seconds
Started Mar 10 01:41:50 PM PDT 24
Finished Mar 10 01:41:54 PM PDT 24
Peak memory 199932 kb
Host smart-632c4513-31a3-42b8-a51a-23e855a2d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720385901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.720385901
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.343264756
Short name T16
Test name
Test status
Simulation time 178975270317 ps
CPU time 2488.55 seconds
Started Mar 10 01:41:54 PM PDT 24
Finished Mar 10 02:23:23 PM PDT 24
Peak memory 241048 kb
Host smart-ee7e2b95-c978-4c33-afd2-2c0d96cc61e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343264756 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.343264756
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.1652845443
Short name T234
Test name
Test status
Simulation time 148406053 ps
CPU time 1.3 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:41:54 PM PDT 24
Peak memory 199676 kb
Host smart-b42421ae-9f16-4dea-a7b5-39d6cbd2e14d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652845443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.1652845443
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.2423744324
Short name T398
Test name
Test status
Simulation time 36392101805 ps
CPU time 542.19 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 200064 kb
Host smart-8873e397-f568-4c02-9adb-412bef23b115
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423744324 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.2423744324
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.4033071416
Short name T575
Test name
Test status
Simulation time 1373046697 ps
CPU time 5.24 seconds
Started Mar 10 01:41:52 PM PDT 24
Finished Mar 10 01:41:58 PM PDT 24
Peak memory 199856 kb
Host smart-4edc06a6-fe95-437e-a96d-70fab1ab0369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033071416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.4033071416
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.1357564926
Short name T327
Test name
Test status
Simulation time 12628626 ps
CPU time 0.6 seconds
Started Mar 10 01:42:01 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 195316 kb
Host smart-41fe66ef-3a5c-4356-8801-0c60d7349385
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357564926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.1357564926
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2568307264
Short name T572
Test name
Test status
Simulation time 1828120620 ps
CPU time 35.41 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:42:29 PM PDT 24
Peak memory 208116 kb
Host smart-ea86d67d-552d-4c00-a437-a1df0cc568ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568307264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2568307264
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2172087815
Short name T175
Test name
Test status
Simulation time 9691178551 ps
CPU time 32.6 seconds
Started Mar 10 01:41:59 PM PDT 24
Finished Mar 10 01:42:31 PM PDT 24
Peak memory 199928 kb
Host smart-625bdabb-529e-4fc1-8541-b8ddef63a412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172087815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2172087815
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.834361097
Short name T190
Test name
Test status
Simulation time 61342638 ps
CPU time 1.8 seconds
Started Mar 10 01:41:59 PM PDT 24
Finished Mar 10 01:42:01 PM PDT 24
Peak memory 199928 kb
Host smart-3a7911ac-4bfb-4887-bde2-01e240922f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834361097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.834361097
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.3398024081
Short name T277
Test name
Test status
Simulation time 22478343877 ps
CPU time 102.66 seconds
Started Mar 10 01:41:59 PM PDT 24
Finished Mar 10 01:43:41 PM PDT 24
Peak memory 200028 kb
Host smart-c9cfac07-5c11-48ee-935e-56b587b7c7e2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398024081 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.3398024081
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.533455381
Short name T537
Test name
Test status
Simulation time 6364731683 ps
CPU time 46.79 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:42:40 PM PDT 24
Peak memory 199924 kb
Host smart-b9edfdf9-3a0d-485c-8ad5-ba518ddead91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533455381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.533455381
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.174131356
Short name T184
Test name
Test status
Simulation time 182790275 ps
CPU time 5.47 seconds
Started Mar 10 01:41:53 PM PDT 24
Finished Mar 10 01:41:59 PM PDT 24
Peak memory 199924 kb
Host smart-56a4c8af-af17-402e-997e-debe59703203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174131356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.174131356
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.3430119439
Short name T181
Test name
Test status
Simulation time 16400332986 ps
CPU time 228.77 seconds
Started Mar 10 01:42:00 PM PDT 24
Finished Mar 10 01:45:49 PM PDT 24
Peak memory 200036 kb
Host smart-0c415c74-fed6-4191-a7ea-3a7b3f79e784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430119439 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.3430119439
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.4274873494
Short name T264
Test name
Test status
Simulation time 564898976 ps
CPU time 1.01 seconds
Started Mar 10 01:41:58 PM PDT 24
Finished Mar 10 01:41:59 PM PDT 24
Peak memory 198232 kb
Host smart-6a4a889b-7e6f-4ea8-8d99-f547f3b25133
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274873494 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.4274873494
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.1444976943
Short name T579
Test name
Test status
Simulation time 12839828936 ps
CPU time 406.49 seconds
Started Mar 10 01:41:59 PM PDT 24
Finished Mar 10 01:48:46 PM PDT 24
Peak memory 200064 kb
Host smart-c377b528-322a-4f38-a43f-0ef74251275d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444976943 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.1444976943
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1449466780
Short name T437
Test name
Test status
Simulation time 1574228913 ps
CPU time 23.79 seconds
Started Mar 10 01:41:58 PM PDT 24
Finished Mar 10 01:42:22 PM PDT 24
Peak memory 199932 kb
Host smart-3a5f9cd5-0d31-42b1-8ada-eec10740dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449466780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1449466780
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2083357536
Short name T230
Test name
Test status
Simulation time 12730498 ps
CPU time 0.59 seconds
Started Mar 10 01:42:08 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 194268 kb
Host smart-64c9cd28-0124-4134-9c88-34c2b631eeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083357536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2083357536
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1921992808
Short name T259
Test name
Test status
Simulation time 712973069 ps
CPU time 7.07 seconds
Started Mar 10 01:42:03 PM PDT 24
Finished Mar 10 01:42:11 PM PDT 24
Peak memory 208120 kb
Host smart-204a4bd6-a708-42d3-a967-54be6ebd0d36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921992808 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1921992808
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.2135921697
Short name T271
Test name
Test status
Simulation time 877554880 ps
CPU time 8.21 seconds
Started Mar 10 01:42:01 PM PDT 24
Finished Mar 10 01:42:10 PM PDT 24
Peak memory 199868 kb
Host smart-e881c431-a8c9-48ec-99fd-fb520b49f2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135921697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.2135921697
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.2858849809
Short name T489
Test name
Test status
Simulation time 21278185368 ps
CPU time 94.92 seconds
Started Mar 10 01:42:02 PM PDT 24
Finished Mar 10 01:43:37 PM PDT 24
Peak memory 199880 kb
Host smart-b220744f-fd8e-4d5a-ad61-cf3605fbdfc3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2858849809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.2858849809
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.829088114
Short name T205
Test name
Test status
Simulation time 20278546637 ps
CPU time 197.49 seconds
Started Mar 10 01:42:03 PM PDT 24
Finished Mar 10 01:45:21 PM PDT 24
Peak memory 199940 kb
Host smart-4dddfb53-a708-463b-82c8-03c6860b61c1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829088114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.829088114
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1607796726
Short name T471
Test name
Test status
Simulation time 5092984059 ps
CPU time 20.47 seconds
Started Mar 10 01:42:04 PM PDT 24
Finished Mar 10 01:42:25 PM PDT 24
Peak memory 199984 kb
Host smart-ed47fe2f-b34b-4be5-affd-b8d67c37b1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607796726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1607796726
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.1029095102
Short name T345
Test name
Test status
Simulation time 275731591 ps
CPU time 3.89 seconds
Started Mar 10 01:42:01 PM PDT 24
Finished Mar 10 01:42:05 PM PDT 24
Peak memory 199892 kb
Host smart-96fc7a46-76d0-46a7-996a-8ce933ef372e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029095102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.1029095102
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.1967935321
Short name T494
Test name
Test status
Simulation time 84943207645 ps
CPU time 1146.85 seconds
Started Mar 10 01:42:06 PM PDT 24
Finished Mar 10 02:01:13 PM PDT 24
Peak memory 229824 kb
Host smart-909ecdab-e04a-4439-b188-770c56e95123
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967935321 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.1967935321
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_stress_all_with_rand_reset.2762598506
Short name T36
Test name
Test status
Simulation time 47021103666 ps
CPU time 1799.07 seconds
Started Mar 10 01:42:09 PM PDT 24
Finished Mar 10 02:12:08 PM PDT 24
Peak memory 246824 kb
Host smart-5b1d009a-b0ec-483d-a26c-eefbd1789874
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2762598506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all_with_rand_reset.2762598506
Directory /workspace/43.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.2056950900
Short name T317
Test name
Test status
Simulation time 351087983 ps
CPU time 1.34 seconds
Started Mar 10 01:42:07 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 199440 kb
Host smart-920bf89c-f5df-4371-9450-fff4dfed3629
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056950900 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.2056950900
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2570591742
Short name T309
Test name
Test status
Simulation time 35716122937 ps
CPU time 500.7 seconds
Started Mar 10 01:42:03 PM PDT 24
Finished Mar 10 01:50:24 PM PDT 24
Peak memory 200060 kb
Host smart-b18e5e90-a0ac-4737-88ff-b18d9b8e55fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570591742 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2570591742
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.2344748104
Short name T80
Test name
Test status
Simulation time 7644206510 ps
CPU time 49.73 seconds
Started Mar 10 01:42:02 PM PDT 24
Finished Mar 10 01:42:52 PM PDT 24
Peak memory 200024 kb
Host smart-58f1b773-99bd-4dd3-94e4-c6b59230477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344748104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.2344748104
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2924045825
Short name T212
Test name
Test status
Simulation time 35564274 ps
CPU time 0.55 seconds
Started Mar 10 01:42:18 PM PDT 24
Finished Mar 10 01:42:19 PM PDT 24
Peak memory 195292 kb
Host smart-d75dcdc3-315a-446e-9d53-26c4752c60a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924045825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2924045825
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.1854777028
Short name T47
Test name
Test status
Simulation time 893059072 ps
CPU time 39.08 seconds
Started Mar 10 01:42:06 PM PDT 24
Finished Mar 10 01:42:45 PM PDT 24
Peak memory 240896 kb
Host smart-b753fce5-dd0d-444f-9081-78dbad3e3ebb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1854777028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.1854777028
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.4287222097
Short name T26
Test name
Test status
Simulation time 1609299454 ps
CPU time 76.25 seconds
Started Mar 10 01:42:06 PM PDT 24
Finished Mar 10 01:43:23 PM PDT 24
Peak memory 199936 kb
Host smart-49f8e64d-7bbd-46fa-bf6b-91528193f556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287222097 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.4287222097
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.354841167
Short name T594
Test name
Test status
Simulation time 467624191 ps
CPU time 29.56 seconds
Started Mar 10 01:42:06 PM PDT 24
Finished Mar 10 01:42:36 PM PDT 24
Peak memory 199844 kb
Host smart-b89a2461-33bf-42b1-822c-ba1a88d2fbfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354841167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.354841167
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.2381029399
Short name T18
Test name
Test status
Simulation time 2975466558 ps
CPU time 154.62 seconds
Started Mar 10 01:42:12 PM PDT 24
Finished Mar 10 01:44:47 PM PDT 24
Peak memory 199952 kb
Host smart-564af82e-b674-4511-a7b5-8070e02a93af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381029399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.2381029399
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2469504264
Short name T293
Test name
Test status
Simulation time 3868488099 ps
CPU time 121.97 seconds
Started Mar 10 01:42:07 PM PDT 24
Finished Mar 10 01:44:09 PM PDT 24
Peak memory 199948 kb
Host smart-3d44a497-dd48-49c9-840f-cae7941cb07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469504264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2469504264
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.322042440
Short name T67
Test name
Test status
Simulation time 238924244 ps
CPU time 4.1 seconds
Started Mar 10 01:42:07 PM PDT 24
Finished Mar 10 01:42:11 PM PDT 24
Peak memory 199808 kb
Host smart-e35a2139-6e6d-4dbe-8ce3-2495a13ef44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322042440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.322042440
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.2331827869
Short name T595
Test name
Test status
Simulation time 6723084717 ps
CPU time 330.68 seconds
Started Mar 10 01:42:13 PM PDT 24
Finished Mar 10 01:47:43 PM PDT 24
Peak memory 224584 kb
Host smart-0ef1d4cc-e628-4393-93f0-845541708b9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331827869 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.2331827869
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.874136055
Short name T541
Test name
Test status
Simulation time 28239577 ps
CPU time 1.01 seconds
Started Mar 10 01:42:11 PM PDT 24
Finished Mar 10 01:42:13 PM PDT 24
Peak memory 199040 kb
Host smart-1c134fa1-fac3-4d39-9e23-e4453ff8a81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874136055 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.hmac_test_hmac_vectors.874136055
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1409409795
Short name T392
Test name
Test status
Simulation time 7460370554 ps
CPU time 457.49 seconds
Started Mar 10 01:42:12 PM PDT 24
Finished Mar 10 01:49:49 PM PDT 24
Peak memory 200064 kb
Host smart-2dab2890-61ec-48e4-8933-7a36aedc0272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409409795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1409409795
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.2505771517
Short name T325
Test name
Test status
Simulation time 4957733029 ps
CPU time 35.29 seconds
Started Mar 10 01:42:12 PM PDT 24
Finished Mar 10 01:42:48 PM PDT 24
Peak memory 200004 kb
Host smart-da3da521-ff2a-4dd1-ac29-094f43434291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505771517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.2505771517
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.762044433
Short name T427
Test name
Test status
Simulation time 47298164 ps
CPU time 0.6 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:42:18 PM PDT 24
Peak memory 195344 kb
Host smart-3c3a97a7-6916-426a-a4c7-5dbaa03d7263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762044433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.762044433
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1714457601
Short name T310
Test name
Test status
Simulation time 926720687 ps
CPU time 31.44 seconds
Started Mar 10 01:42:18 PM PDT 24
Finished Mar 10 01:42:50 PM PDT 24
Peak memory 221332 kb
Host smart-8da7acc9-4282-4541-8c1f-ef01a762051f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714457601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1714457601
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.621240863
Short name T246
Test name
Test status
Simulation time 316725038 ps
CPU time 13.83 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:42:32 PM PDT 24
Peak memory 199924 kb
Host smart-7effef38-ed0f-47c9-bb43-cf6722c1925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621240863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.621240863
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3636621598
Short name T553
Test name
Test status
Simulation time 8210810798 ps
CPU time 117.94 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:44:16 PM PDT 24
Peak memory 199960 kb
Host smart-682c0276-dd4d-4a4e-b67d-fa9d15725090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3636621598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3636621598
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.3266311718
Short name T551
Test name
Test status
Simulation time 2547050588 ps
CPU time 143.04 seconds
Started Mar 10 01:42:18 PM PDT 24
Finished Mar 10 01:44:42 PM PDT 24
Peak memory 199892 kb
Host smart-74be59eb-f76f-4f6b-8a13-03f4651e9acf
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266311718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.3266311718
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1453772782
Short name T531
Test name
Test status
Simulation time 3493816181 ps
CPU time 109.55 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:44:07 PM PDT 24
Peak memory 199964 kb
Host smart-429bac57-d4f4-4a2b-ab20-28348e8960af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453772782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1453772782
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.2144307495
Short name T484
Test name
Test status
Simulation time 1591476202 ps
CPU time 5.8 seconds
Started Mar 10 01:42:19 PM PDT 24
Finished Mar 10 01:42:25 PM PDT 24
Peak memory 199840 kb
Host smart-d6589e33-f132-4647-a4fe-d7ea66792538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144307495 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.2144307495
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2137839032
Short name T498
Test name
Test status
Simulation time 29105819 ps
CPU time 0.99 seconds
Started Mar 10 01:42:18 PM PDT 24
Finished Mar 10 01:42:19 PM PDT 24
Peak memory 198260 kb
Host smart-7f522e8a-2f9b-4e74-9b0b-78d86e53c924
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137839032 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2137839032
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.1379610490
Short name T52
Test name
Test status
Simulation time 54307986406 ps
CPU time 517.58 seconds
Started Mar 10 01:42:18 PM PDT 24
Finished Mar 10 01:50:55 PM PDT 24
Peak memory 200044 kb
Host smart-d0cfc11f-8a3b-4441-be12-af003b23783f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379610490 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.1379610490
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.965033621
Short name T426
Test name
Test status
Simulation time 9544262802 ps
CPU time 90.02 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:43:48 PM PDT 24
Peak memory 199964 kb
Host smart-720677ed-6fc2-44cb-90f2-47d72032389e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965033621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.965033621
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3887260643
Short name T320
Test name
Test status
Simulation time 51850766 ps
CPU time 0.56 seconds
Started Mar 10 01:42:21 PM PDT 24
Finished Mar 10 01:42:22 PM PDT 24
Peak memory 194296 kb
Host smart-07997d42-630a-4856-a9b8-0023d9648b4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887260643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3887260643
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.3407782639
Short name T347
Test name
Test status
Simulation time 1424812149 ps
CPU time 64.55 seconds
Started Mar 10 01:42:22 PM PDT 24
Finished Mar 10 01:43:27 PM PDT 24
Peak memory 235640 kb
Host smart-85bd5f0b-963f-4ca0-9671-f54eae49aebf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3407782639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.3407782639
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2240785218
Short name T499
Test name
Test status
Simulation time 967355216 ps
CPU time 21.78 seconds
Started Mar 10 01:42:22 PM PDT 24
Finished Mar 10 01:42:44 PM PDT 24
Peak memory 199892 kb
Host smart-6c2b91b3-8391-43ee-9069-e3cf54ec1a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240785218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2240785218
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.2203559083
Short name T213
Test name
Test status
Simulation time 2812213984 ps
CPU time 128.7 seconds
Started Mar 10 01:42:23 PM PDT 24
Finished Mar 10 01:44:32 PM PDT 24
Peak memory 199928 kb
Host smart-e1232858-315c-4188-84e7-be8a6353f715
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2203559083 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.2203559083
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.994037107
Short name T88
Test name
Test status
Simulation time 2163107786 ps
CPU time 123.79 seconds
Started Mar 10 01:42:23 PM PDT 24
Finished Mar 10 01:44:27 PM PDT 24
Peak memory 199952 kb
Host smart-168421ee-07c7-4bad-8f19-264b49cef52c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994037107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.994037107
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1266943027
Short name T557
Test name
Test status
Simulation time 11129567509 ps
CPU time 58.56 seconds
Started Mar 10 01:42:23 PM PDT 24
Finished Mar 10 01:43:22 PM PDT 24
Peak memory 199960 kb
Host smart-c758097a-2062-4988-ad0d-e891b2eef878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266943027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1266943027
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.951986884
Short name T449
Test name
Test status
Simulation time 938673839 ps
CPU time 2.9 seconds
Started Mar 10 01:42:17 PM PDT 24
Finished Mar 10 01:42:20 PM PDT 24
Peak memory 199868 kb
Host smart-4d8a046b-2599-4463-8c93-82a1c5d1a0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951986884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.951986884
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.4152962901
Short name T530
Test name
Test status
Simulation time 33528348 ps
CPU time 1.25 seconds
Started Mar 10 01:42:23 PM PDT 24
Finished Mar 10 01:42:24 PM PDT 24
Peak memory 199872 kb
Host smart-53cb80bf-24bc-4994-8add-f56c83ee49b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152962901 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.4152962901
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.2194192875
Short name T270
Test name
Test status
Simulation time 73988304671 ps
CPU time 515.25 seconds
Started Mar 10 01:42:21 PM PDT 24
Finished Mar 10 01:50:57 PM PDT 24
Peak memory 200044 kb
Host smart-2474585a-2091-4e32-8484-e1c82af5fcd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194192875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.2194192875
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1937505952
Short name T113
Test name
Test status
Simulation time 514004704 ps
CPU time 10.99 seconds
Started Mar 10 01:42:22 PM PDT 24
Finished Mar 10 01:42:34 PM PDT 24
Peak memory 199908 kb
Host smart-13466903-f5b1-4cd8-8322-662443cc6029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937505952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1937505952
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1015329874
Short name T297
Test name
Test status
Simulation time 1274111941 ps
CPU time 48.84 seconds
Started Mar 10 01:42:26 PM PDT 24
Finished Mar 10 01:43:15 PM PDT 24
Peak memory 226948 kb
Host smart-6cc30f3e-72d5-4f97-b3fc-0f34560424cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015329874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1015329874
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4071198001
Short name T451
Test name
Test status
Simulation time 5458779956 ps
CPU time 39.89 seconds
Started Mar 10 01:42:28 PM PDT 24
Finished Mar 10 01:43:08 PM PDT 24
Peak memory 200020 kb
Host smart-6af4d6cf-59d6-4b50-a816-0fcf722120db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071198001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4071198001
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.661306330
Short name T305
Test name
Test status
Simulation time 3890808379 ps
CPU time 122.39 seconds
Started Mar 10 01:42:29 PM PDT 24
Finished Mar 10 01:44:31 PM PDT 24
Peak memory 199864 kb
Host smart-4d3d5c43-f56c-49e1-a839-05777297c1c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661306330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.661306330
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.350080227
Short name T218
Test name
Test status
Simulation time 7373424874 ps
CPU time 105.35 seconds
Started Mar 10 01:42:29 PM PDT 24
Finished Mar 10 01:44:14 PM PDT 24
Peak memory 199916 kb
Host smart-5d8b866f-488f-4869-8b5f-4f12181ec319
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350080227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.350080227
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2046846114
Short name T358
Test name
Test status
Simulation time 1979725725 ps
CPU time 29.65 seconds
Started Mar 10 01:42:28 PM PDT 24
Finished Mar 10 01:42:58 PM PDT 24
Peak memory 199912 kb
Host smart-dfad060f-5282-49d3-97c7-61c0e0a368f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046846114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2046846114
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3924131342
Short name T339
Test name
Test status
Simulation time 395663421 ps
CPU time 6.59 seconds
Started Mar 10 01:42:22 PM PDT 24
Finished Mar 10 01:42:28 PM PDT 24
Peak memory 199932 kb
Host smart-757cb91f-731b-43fe-93e5-5ae20c8a85fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924131342 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3924131342
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.78084560
Short name T334
Test name
Test status
Simulation time 231761352435 ps
CPU time 366.55 seconds
Started Mar 10 01:42:26 PM PDT 24
Finished Mar 10 01:48:33 PM PDT 24
Peak memory 230112 kb
Host smart-dbbf0aa4-ee4c-40ad-bc56-f7d30e9f97fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78084560 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.78084560
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.3373588396
Short name T69
Test name
Test status
Simulation time 90435560 ps
CPU time 0.99 seconds
Started Mar 10 01:42:28 PM PDT 24
Finished Mar 10 01:42:29 PM PDT 24
Peak memory 198724 kb
Host smart-122c1270-c770-433c-a68f-6d36e8cabb8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373588396 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.3373588396
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.3102746257
Short name T225
Test name
Test status
Simulation time 8773290812 ps
CPU time 390.11 seconds
Started Mar 10 01:42:25 PM PDT 24
Finished Mar 10 01:48:55 PM PDT 24
Peak memory 199968 kb
Host smart-a9ea3cb9-04e2-413c-820b-9a1ea5e7ab65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102746257 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.3102746257
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1742197753
Short name T447
Test name
Test status
Simulation time 9109497190 ps
CPU time 36.07 seconds
Started Mar 10 01:42:28 PM PDT 24
Finished Mar 10 01:43:04 PM PDT 24
Peak memory 199996 kb
Host smart-fb2493b4-809a-48e2-aa73-8c739a5b0c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742197753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1742197753
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.390944153
Short name T539
Test name
Test status
Simulation time 15596152 ps
CPU time 0.6 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:42:37 PM PDT 24
Peak memory 195320 kb
Host smart-3c50f7aa-6d1e-4481-b065-2e0e6b53b125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390944153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.390944153
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2755741238
Short name T548
Test name
Test status
Simulation time 180974439 ps
CPU time 2.28 seconds
Started Mar 10 01:42:31 PM PDT 24
Finished Mar 10 01:42:34 PM PDT 24
Peak memory 199924 kb
Host smart-9e7d8d76-3e07-43b2-9fbb-714011eb9590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2755741238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2755741238
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.469497182
Short name T535
Test name
Test status
Simulation time 5982534438 ps
CPU time 24.93 seconds
Started Mar 10 01:42:31 PM PDT 24
Finished Mar 10 01:42:56 PM PDT 24
Peak memory 200008 kb
Host smart-d6be0d38-d9ac-42ca-8225-7eff8522a7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469497182 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.469497182
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1638209282
Short name T125
Test name
Test status
Simulation time 3217110274 ps
CPU time 116.89 seconds
Started Mar 10 01:42:31 PM PDT 24
Finished Mar 10 01:44:28 PM PDT 24
Peak memory 199924 kb
Host smart-4fc8a9ee-a43d-4cee-a038-968c55234ca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1638209282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1638209282
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.2410235788
Short name T458
Test name
Test status
Simulation time 8120084114 ps
CPU time 116.96 seconds
Started Mar 10 01:42:32 PM PDT 24
Finished Mar 10 01:44:29 PM PDT 24
Peak memory 200012 kb
Host smart-c5b91a85-9fa7-4f79-9c5d-d4377ebf72ba
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410235788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.2410235788
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3262620080
Short name T314
Test name
Test status
Simulation time 1122330367 ps
CPU time 18.89 seconds
Started Mar 10 01:42:31 PM PDT 24
Finished Mar 10 01:42:50 PM PDT 24
Peak memory 199904 kb
Host smart-2efa3a94-3cc0-4097-8d48-41cb4ba77b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262620080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3262620080
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3587899560
Short name T519
Test name
Test status
Simulation time 878678836 ps
CPU time 5.74 seconds
Started Mar 10 01:42:30 PM PDT 24
Finished Mar 10 01:42:36 PM PDT 24
Peak memory 199820 kb
Host smart-87ee94bc-088a-4b0a-a303-63a05e4deee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587899560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3587899560
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.3585070961
Short name T363
Test name
Test status
Simulation time 333068342098 ps
CPU time 1649.15 seconds
Started Mar 10 01:42:38 PM PDT 24
Finished Mar 10 02:10:07 PM PDT 24
Peak memory 232816 kb
Host smart-1d962af8-00b7-4e9a-9bc3-49795d2e42c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585070961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.3585070961
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.1771108738
Short name T90
Test name
Test status
Simulation time 210343613 ps
CPU time 1.06 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:42:38 PM PDT 24
Peak memory 198152 kb
Host smart-16200bdc-7eb0-48dc-afe2-697cd40ff253
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771108738 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.1771108738
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2569131806
Short name T182
Test name
Test status
Simulation time 352641597180 ps
CPU time 600.22 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:52:38 PM PDT 24
Peak memory 199992 kb
Host smart-c9649699-05f1-4cd5-bf9e-36e19b32f8f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569131806 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2569131806
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.3896428981
Short name T285
Test name
Test status
Simulation time 3199293231 ps
CPU time 43.26 seconds
Started Mar 10 01:42:38 PM PDT 24
Finished Mar 10 01:43:21 PM PDT 24
Peak memory 199952 kb
Host smart-73201b04-9b27-4db5-9fcb-77e572157b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896428981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.3896428981
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1246929551
Short name T24
Test name
Test status
Simulation time 54582883 ps
CPU time 0.6 seconds
Started Mar 10 01:42:41 PM PDT 24
Finished Mar 10 01:42:42 PM PDT 24
Peak memory 195300 kb
Host smart-73daacda-878a-4d7d-b55f-a6391819763c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246929551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1246929551
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.970778008
Short name T50
Test name
Test status
Simulation time 128012539 ps
CPU time 2.05 seconds
Started Mar 10 01:42:39 PM PDT 24
Finished Mar 10 01:42:41 PM PDT 24
Peak memory 199808 kb
Host smart-a84871a8-77e8-4472-8df7-833ed06396d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970778008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.970778008
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2151299775
Short name T128
Test name
Test status
Simulation time 1741606306 ps
CPU time 28.98 seconds
Started Mar 10 01:42:39 PM PDT 24
Finished Mar 10 01:43:08 PM PDT 24
Peak memory 199852 kb
Host smart-c38c6442-19ba-4bab-95d4-dafc2f9f4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151299775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2151299775
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2840687888
Short name T353
Test name
Test status
Simulation time 777112579 ps
CPU time 48.44 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:43:25 PM PDT 24
Peak memory 199856 kb
Host smart-ec28d34f-65cb-4036-ae3f-edf7fa9c495e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2840687888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2840687888
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1836594484
Short name T171
Test name
Test status
Simulation time 7052565669 ps
CPU time 92.81 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:44:10 PM PDT 24
Peak memory 199956 kb
Host smart-d1c5effc-0cd5-4aa9-bd50-c08cf3a2e45b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836594484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1836594484
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.684398238
Short name T416
Test name
Test status
Simulation time 14368163162 ps
CPU time 56.1 seconds
Started Mar 10 01:42:34 PM PDT 24
Finished Mar 10 01:43:31 PM PDT 24
Peak memory 200032 kb
Host smart-4056133a-1fa4-4ef1-b25b-914cddfe1a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684398238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.684398238
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.3873940383
Short name T509
Test name
Test status
Simulation time 1188261607 ps
CPU time 3.65 seconds
Started Mar 10 01:42:34 PM PDT 24
Finished Mar 10 01:42:38 PM PDT 24
Peak memory 199876 kb
Host smart-f22bf91b-87a9-492d-a69e-d50fbea87f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873940383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.3873940383
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.338853345
Short name T559
Test name
Test status
Simulation time 8368897181 ps
CPU time 19.24 seconds
Started Mar 10 01:42:40 PM PDT 24
Finished Mar 10 01:43:00 PM PDT 24
Peak memory 199984 kb
Host smart-a2caec2a-7102-4675-afa3-b7c042a0b837
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338853345 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.338853345
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.1379483349
Short name T308
Test name
Test status
Simulation time 101540115 ps
CPU time 1 seconds
Started Mar 10 01:42:40 PM PDT 24
Finished Mar 10 01:42:41 PM PDT 24
Peak memory 197868 kb
Host smart-d27857a6-767b-4ee7-94a8-08060e0e0a85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379483349 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.hmac_test_hmac_vectors.1379483349
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.741876901
Short name T442
Test name
Test status
Simulation time 8472378146 ps
CPU time 492.9 seconds
Started Mar 10 01:42:41 PM PDT 24
Finished Mar 10 01:50:54 PM PDT 24
Peak memory 200056 kb
Host smart-fea0e8b3-c29c-47ef-b9c0-296cd2d4e858
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741876901 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.741876901
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.1807815442
Short name T276
Test name
Test status
Simulation time 4594965598 ps
CPU time 65.35 seconds
Started Mar 10 01:42:37 PM PDT 24
Finished Mar 10 01:43:43 PM PDT 24
Peak memory 199984 kb
Host smart-1dcd0bc1-25a7-45db-ba5e-0d580f6180ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807815442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.1807815442
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.3972605192
Short name T22
Test name
Test status
Simulation time 43759734 ps
CPU time 0.58 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:21 PM PDT 24
Peak memory 195312 kb
Host smart-cdb96076-7ce5-4940-865c-26f94a4f3b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972605192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.3972605192
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.4177620350
Short name T255
Test name
Test status
Simulation time 1608639305 ps
CPU time 60.58 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:40:20 PM PDT 24
Peak memory 232380 kb
Host smart-4d04aaf4-0761-456e-8258-ad51067191ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177620350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.4177620350
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1870720037
Short name T512
Test name
Test status
Simulation time 1203149743 ps
CPU time 17.58 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:38 PM PDT 24
Peak memory 199816 kb
Host smart-0444d934-f374-496f-a4bd-4b836ddf8703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870720037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1870720037
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.3951142799
Short name T328
Test name
Test status
Simulation time 5015060813 ps
CPU time 146.68 seconds
Started Mar 10 01:39:23 PM PDT 24
Finished Mar 10 01:41:50 PM PDT 24
Peak memory 200020 kb
Host smart-3f7c27b0-087f-420e-b2ce-ecf5716e88a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3951142799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.3951142799
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.725286850
Short name T173
Test name
Test status
Simulation time 95935509267 ps
CPU time 167.88 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:42:09 PM PDT 24
Peak memory 199964 kb
Host smart-47dddd3a-88c9-4c84-b639-97145e25d322
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725286850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.725286850
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3066352711
Short name T66
Test name
Test status
Simulation time 39137357595 ps
CPU time 54.54 seconds
Started Mar 10 01:39:19 PM PDT 24
Finished Mar 10 01:40:14 PM PDT 24
Peak memory 200020 kb
Host smart-83e2f6df-d746-4c57-8b3e-b43217a4173d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066352711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3066352711
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.3626655602
Short name T154
Test name
Test status
Simulation time 93740004 ps
CPU time 2.87 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:23 PM PDT 24
Peak memory 199872 kb
Host smart-f2239118-b11a-4aaa-878f-64eec1d6554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626655602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.3626655602
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1338288847
Short name T569
Test name
Test status
Simulation time 15453318084 ps
CPU time 825.43 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:53:05 PM PDT 24
Peak memory 199972 kb
Host smart-e3f7e058-14ff-40a1-9939-0549fce922fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338288847 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1338288847
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.4271353138
Short name T294
Test name
Test status
Simulation time 31255218 ps
CPU time 1.27 seconds
Started Mar 10 01:39:20 PM PDT 24
Finished Mar 10 01:39:22 PM PDT 24
Peak memory 199720 kb
Host smart-f306f9ff-95c5-45e3-8479-8b92beada78a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271353138 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.4271353138
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.1767793961
Short name T421
Test name
Test status
Simulation time 35607691783 ps
CPU time 458.97 seconds
Started Mar 10 01:39:23 PM PDT 24
Finished Mar 10 01:47:03 PM PDT 24
Peak memory 200024 kb
Host smart-b34f7b87-b907-42f0-ac44-05ff92be722e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767793961 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.1767793961
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.715823906
Short name T142
Test name
Test status
Simulation time 28427006469 ps
CPU time 40.16 seconds
Started Mar 10 01:39:21 PM PDT 24
Finished Mar 10 01:40:01 PM PDT 24
Peak memory 199976 kb
Host smart-4bb998ae-7b8b-4fa1-98c4-53c7dedaf1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715823906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.715823906
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.6253592
Short name T577
Test name
Test status
Simulation time 40924458 ps
CPU time 0.6 seconds
Started Mar 10 01:39:27 PM PDT 24
Finished Mar 10 01:39:28 PM PDT 24
Peak memory 195308 kb
Host smart-e325fbc4-103f-4f7e-ad8a-3d47ab50781e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6253592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.6253592
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3353543867
Short name T343
Test name
Test status
Simulation time 2729536131 ps
CPU time 53.61 seconds
Started Mar 10 01:39:24 PM PDT 24
Finished Mar 10 01:40:18 PM PDT 24
Peak memory 225524 kb
Host smart-581a48f4-d11a-4ec5-9e93-3142018ded30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3353543867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3353543867
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.668837373
Short name T70
Test name
Test status
Simulation time 1726737789 ps
CPU time 13.8 seconds
Started Mar 10 01:39:25 PM PDT 24
Finished Mar 10 01:39:39 PM PDT 24
Peak memory 199908 kb
Host smart-e6bf3667-53c3-40a4-b10c-1c49ba53f1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668837373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.668837373
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2843474950
Short name T296
Test name
Test status
Simulation time 534458393 ps
CPU time 7.05 seconds
Started Mar 10 01:39:27 PM PDT 24
Finished Mar 10 01:39:35 PM PDT 24
Peak memory 199776 kb
Host smart-cf6168f3-343d-4d64-b53a-31abfab43a39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843474950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2843474950
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.31502908
Short name T576
Test name
Test status
Simulation time 4295221152 ps
CPU time 99.44 seconds
Started Mar 10 01:39:27 PM PDT 24
Finished Mar 10 01:41:07 PM PDT 24
Peak memory 200016 kb
Host smart-96f66844-9830-42fa-b2e4-938ae35f1cd2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31502908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.31502908
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.586464468
Short name T360
Test name
Test status
Simulation time 672529820 ps
CPU time 40.83 seconds
Started Mar 10 01:39:26 PM PDT 24
Finished Mar 10 01:40:07 PM PDT 24
Peak memory 199868 kb
Host smart-85763d7d-01f1-4458-93b8-229d0047db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586464468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.586464468
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1702774921
Short name T237
Test name
Test status
Simulation time 555277163 ps
CPU time 3.53 seconds
Started Mar 10 01:39:27 PM PDT 24
Finished Mar 10 01:39:31 PM PDT 24
Peak memory 199808 kb
Host smart-afe2c7a9-ed0c-428f-aae9-06773c571c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702774921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1702774921
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.3985588070
Short name T480
Test name
Test status
Simulation time 15421353553 ps
CPU time 155.51 seconds
Started Mar 10 01:39:26 PM PDT 24
Finished Mar 10 01:42:02 PM PDT 24
Peak memory 224412 kb
Host smart-fec948d6-4966-47c9-bfa9-d0cde9b818f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985588070 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.3985588070
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.4291246591
Short name T135
Test name
Test status
Simulation time 106327824 ps
CPU time 1.08 seconds
Started Mar 10 01:39:23 PM PDT 24
Finished Mar 10 01:39:24 PM PDT 24
Peak memory 198868 kb
Host smart-e19f4347-9ceb-4da2-8122-7d942e3825c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291246591 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.4291246591
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.3828258810
Short name T240
Test name
Test status
Simulation time 70413931549 ps
CPU time 466.6 seconds
Started Mar 10 01:39:25 PM PDT 24
Finished Mar 10 01:47:12 PM PDT 24
Peak memory 199944 kb
Host smart-66662ce5-eb82-4084-8428-a4149303c6b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828258810 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.3828258810
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2080475670
Short name T487
Test name
Test status
Simulation time 4670479666 ps
CPU time 42.88 seconds
Started Mar 10 01:39:26 PM PDT 24
Finished Mar 10 01:40:09 PM PDT 24
Peak memory 200036 kb
Host smart-02859ff1-62b4-429a-b01e-b42c91467efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080475670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2080475670
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/69.hmac_stress_all_with_rand_reset.2566655113
Short name T64
Test name
Test status
Simulation time 30294395903 ps
CPU time 1474.69 seconds
Started Mar 10 01:42:46 PM PDT 24
Finished Mar 10 02:07:22 PM PDT 24
Peak memory 224684 kb
Host smart-a05a80b5-069b-4b79-94bd-55ac8954c117
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566655113 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.hmac_stress_all_with_rand_reset.2566655113
Directory /workspace/69.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.hmac_alert_test.574803678
Short name T386
Test name
Test status
Simulation time 20796155 ps
CPU time 0.59 seconds
Started Mar 10 01:39:28 PM PDT 24
Finished Mar 10 01:39:29 PM PDT 24
Peak memory 195312 kb
Host smart-d7e99647-2633-4134-843c-a03a511e99ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574803678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.574803678
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.2114517696
Short name T307
Test name
Test status
Simulation time 684438987 ps
CPU time 11.94 seconds
Started Mar 10 01:39:25 PM PDT 24
Finished Mar 10 01:39:37 PM PDT 24
Peak memory 199824 kb
Host smart-c6c272c4-b3ea-485d-a304-b13b6cbd0789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114517696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.2114517696
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3954454616
Short name T513
Test name
Test status
Simulation time 1253095949 ps
CPU time 24.6 seconds
Started Mar 10 01:39:26 PM PDT 24
Finished Mar 10 01:39:51 PM PDT 24
Peak memory 199904 kb
Host smart-b409a632-e587-400f-ae5a-94173c2e924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954454616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3954454616
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1800009880
Short name T222
Test name
Test status
Simulation time 89961393 ps
CPU time 6.24 seconds
Started Mar 10 01:39:27 PM PDT 24
Finished Mar 10 01:39:34 PM PDT 24
Peak memory 199800 kb
Host smart-e6e6ce3a-1bf4-435c-92dc-088899ed96c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1800009880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1800009880
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.1924775968
Short name T176
Test name
Test status
Simulation time 6504196772 ps
CPU time 58.19 seconds
Started Mar 10 01:39:25 PM PDT 24
Finished Mar 10 01:40:24 PM PDT 24
Peak memory 199924 kb
Host smart-a4d742cf-06f5-49a3-b711-db23d75dd7c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924775968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.1924775968
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_smoke.1551450867
Short name T333
Test name
Test status
Simulation time 344335465 ps
CPU time 2.99 seconds
Started Mar 10 01:39:28 PM PDT 24
Finished Mar 10 01:39:31 PM PDT 24
Peak memory 199856 kb
Host smart-2f547b00-856a-4b2c-a99e-33f18a57086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551450867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.1551450867
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.698301607
Short name T403
Test name
Test status
Simulation time 54400291131 ps
CPU time 765.37 seconds
Started Mar 10 01:39:32 PM PDT 24
Finished Mar 10 01:52:18 PM PDT 24
Peak memory 199904 kb
Host smart-8b9820f5-4a6c-48d2-9b53-5dd69757c087
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698301607 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.698301607
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2010736944
Short name T550
Test name
Test status
Simulation time 55752866 ps
CPU time 1.3 seconds
Started Mar 10 01:39:29 PM PDT 24
Finished Mar 10 01:39:31 PM PDT 24
Peak memory 199332 kb
Host smart-c710ec94-0fed-44da-bb55-fd2ca031e777
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010736944 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.2010736944
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.3297188861
Short name T356
Test name
Test status
Simulation time 50537164385 ps
CPU time 451.91 seconds
Started Mar 10 01:39:28 PM PDT 24
Finished Mar 10 01:47:00 PM PDT 24
Peak memory 200044 kb
Host smart-e66c5d03-15c3-495c-a59c-0f990bf2b1a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297188861 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.3297188861
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1871688886
Short name T292
Test name
Test status
Simulation time 1982653447 ps
CPU time 13.72 seconds
Started Mar 10 01:39:24 PM PDT 24
Finished Mar 10 01:39:37 PM PDT 24
Peak memory 199852 kb
Host smart-1626cdf2-71a3-48e6-b247-dc6a802ab1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871688886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1871688886
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.1169041339
Short name T12
Test name
Test status
Simulation time 120881749084 ps
CPU time 998.04 seconds
Started Mar 10 01:42:49 PM PDT 24
Finished Mar 10 01:59:28 PM PDT 24
Peak memory 248144 kb
Host smart-37c7da38-06b0-4e94-9917-5f624e7a4b34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1169041339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.1169041339
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2499436068
Short name T590
Test name
Test status
Simulation time 21631262 ps
CPU time 0.59 seconds
Started Mar 10 01:39:29 PM PDT 24
Finished Mar 10 01:39:30 PM PDT 24
Peak memory 195332 kb
Host smart-fdba31b9-fbcd-4a0b-be87-200cb2a6cfbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499436068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2499436068
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1342267573
Short name T528
Test name
Test status
Simulation time 941465450 ps
CPU time 34.31 seconds
Started Mar 10 01:39:29 PM PDT 24
Finished Mar 10 01:40:03 PM PDT 24
Peak memory 216288 kb
Host smart-e142eb0d-8b2f-4d34-b73b-d1debddb0b8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1342267573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1342267573
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.389426541
Short name T523
Test name
Test status
Simulation time 4073761969 ps
CPU time 21.92 seconds
Started Mar 10 01:39:28 PM PDT 24
Finished Mar 10 01:39:50 PM PDT 24
Peak memory 199972 kb
Host smart-bd9a5d4e-488a-4cce-928e-dc55594d9122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389426541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.389426541
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.1012119110
Short name T538
Test name
Test status
Simulation time 6881310279 ps
CPU time 101.42 seconds
Started Mar 10 01:39:30 PM PDT 24
Finished Mar 10 01:41:12 PM PDT 24
Peak memory 200064 kb
Host smart-5f56d972-57ed-485a-aed2-0f551cd48032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012119110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.1012119110
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1201751781
Short name T593
Test name
Test status
Simulation time 2413818424 ps
CPU time 62.38 seconds
Started Mar 10 01:39:30 PM PDT 24
Finished Mar 10 01:40:32 PM PDT 24
Peak memory 199860 kb
Host smart-ee8f0749-ade7-49ac-a83f-7ef46eda4237
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201751781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1201751781
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3497571086
Short name T341
Test name
Test status
Simulation time 4702703248 ps
CPU time 59.8 seconds
Started Mar 10 01:39:30 PM PDT 24
Finished Mar 10 01:40:30 PM PDT 24
Peak memory 200044 kb
Host smart-6afca9b5-1d8e-4702-a603-888d5e093cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497571086 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3497571086
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.3276617446
Short name T439
Test name
Test status
Simulation time 1733060439 ps
CPU time 5.25 seconds
Started Mar 10 01:39:29 PM PDT 24
Finished Mar 10 01:39:35 PM PDT 24
Peak memory 199912 kb
Host smart-4d6be560-3f4a-41a2-8468-3291a74a1bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276617446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.3276617446
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1246074236
Short name T77
Test name
Test status
Simulation time 128348325833 ps
CPU time 513.61 seconds
Started Mar 10 01:39:33 PM PDT 24
Finished Mar 10 01:48:07 PM PDT 24
Peak memory 241984 kb
Host smart-833e3cff-ba4b-4299-b597-81d3173fb440
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246074236 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1246074236
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1820935391
Short name T516
Test name
Test status
Simulation time 73032244 ps
CPU time 1.32 seconds
Started Mar 10 01:39:33 PM PDT 24
Finished Mar 10 01:39:34 PM PDT 24
Peak memory 199592 kb
Host smart-4638b80b-d13c-478f-abec-64a65665cd6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820935391 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1820935391
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.2284866623
Short name T232
Test name
Test status
Simulation time 68995302674 ps
CPU time 513.43 seconds
Started Mar 10 01:39:31 PM PDT 24
Finished Mar 10 01:48:05 PM PDT 24
Peak memory 200084 kb
Host smart-a1fe7ff5-a1e0-434e-bf5f-c867ca2c94f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284866623 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.2284866623
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1425364692
Short name T315
Test name
Test status
Simulation time 7998764946 ps
CPU time 81.13 seconds
Started Mar 10 01:39:30 PM PDT 24
Finished Mar 10 01:40:51 PM PDT 24
Peak memory 199892 kb
Host smart-3f7f9d61-3fbd-4ce0-9925-eac863991dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425364692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1425364692
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2045426307
Short name T331
Test name
Test status
Simulation time 24419082 ps
CPU time 0.61 seconds
Started Mar 10 01:39:31 PM PDT 24
Finished Mar 10 01:39:32 PM PDT 24
Peak memory 194800 kb
Host smart-144bd4da-e3ed-4070-a2cc-abe05fdfd66c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045426307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2045426307
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.682605538
Short name T510
Test name
Test status
Simulation time 298352992 ps
CPU time 3 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:39:43 PM PDT 24
Peak memory 215924 kb
Host smart-5e5401f7-35c3-42e3-98f4-58dcf1b6d40f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682605538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.682605538
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.723935015
Short name T9
Test name
Test status
Simulation time 719408454 ps
CPU time 6.09 seconds
Started Mar 10 01:39:35 PM PDT 24
Finished Mar 10 01:39:41 PM PDT 24
Peak memory 199728 kb
Host smart-398efbe8-7098-4ce0-819a-1149906b33ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723935015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.723935015
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.2664550353
Short name T303
Test name
Test status
Simulation time 6529982553 ps
CPU time 100.41 seconds
Started Mar 10 01:39:30 PM PDT 24
Finished Mar 10 01:41:11 PM PDT 24
Peak memory 200028 kb
Host smart-169f2e00-58f7-49b3-bf82-6a2f56a7e8ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2664550353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.2664550353
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.1239815248
Short name T346
Test name
Test status
Simulation time 3144843507 ps
CPU time 129.59 seconds
Started Mar 10 01:39:36 PM PDT 24
Finished Mar 10 01:41:46 PM PDT 24
Peak memory 199852 kb
Host smart-073c92dd-6778-4c13-9f37-e40223d43645
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239815248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.1239815248
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.2701659285
Short name T496
Test name
Test status
Simulation time 11386409837 ps
CPU time 59.02 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:40:39 PM PDT 24
Peak memory 200012 kb
Host smart-a50d122d-7d48-4fad-8e96-7ae9f56a0f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701659285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.2701659285
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.2499255799
Short name T157
Test name
Test status
Simulation time 89445812 ps
CPU time 2.7 seconds
Started Mar 10 01:39:29 PM PDT 24
Finished Mar 10 01:39:32 PM PDT 24
Peak memory 199868 kb
Host smart-07e4b117-2e5c-42f6-ae2c-c8f26ebffe9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499255799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.2499255799
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3144053107
Short name T377
Test name
Test status
Simulation time 15342763551 ps
CPU time 833.48 seconds
Started Mar 10 01:39:33 PM PDT 24
Finished Mar 10 01:53:27 PM PDT 24
Peak memory 244080 kb
Host smart-1e27970e-1d46-4da1-aa91-b1dc46ce7112
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144053107 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3144053107
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.2998143062
Short name T119
Test name
Test status
Simulation time 146832772 ps
CPU time 1.06 seconds
Started Mar 10 01:39:32 PM PDT 24
Finished Mar 10 01:39:33 PM PDT 24
Peak memory 198880 kb
Host smart-a38a0dad-93a1-49c0-82bc-38e3dea8ba9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998143062 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.2998143062
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.2960512749
Short name T330
Test name
Test status
Simulation time 33347766803 ps
CPU time 426.11 seconds
Started Mar 10 01:39:40 PM PDT 24
Finished Mar 10 01:46:47 PM PDT 24
Peak memory 200064 kb
Host smart-c24512a4-e06a-4846-9638-997f3634c8a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960512749 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.2960512749
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2647527012
Short name T286
Test name
Test status
Simulation time 15140027998 ps
CPU time 57.46 seconds
Started Mar 10 01:39:39 PM PDT 24
Finished Mar 10 01:40:37 PM PDT 24
Peak memory 200024 kb
Host smart-6149ac87-3dc1-4b2e-88ff-d0718c23e8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647527012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2647527012
Directory /workspace/9.hmac_wipe_secret/latest
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