Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 36536572 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 38779234 1 T1 467438 T2 25695 T3 10796



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 30243269 1 T1 380099 T2 23018 T3 9638
values[0x0] 20992263 1 T1 226013 T2 14756 T3 6166
values[0x1] 24080274 1 T1 264086 T2 18411 T3 7836



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 26796479 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 48519327 1 T1 609241 T2 33923 T3 14237



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 262124 1 T1 3174 T2 231 T3 80
valid_sources[0x01] 272742 1 T1 3657 T2 213 T3 102
valid_sources[0x02] 274228 1 T1 3727 T2 211 T3 88
valid_sources[0x03] 274171 1 T1 3677 T2 231 T3 78
valid_sources[0x04] 268812 1 T1 3139 T2 235 T3 75
valid_sources[0x05] 260896 1 T1 3792 T2 216 T3 65
valid_sources[0x06] 295506 1 T1 3927 T2 205 T3 95
valid_sources[0x07] 266976 1 T1 3371 T2 203 T3 101
valid_sources[0x08] 275814 1 T1 3300 T2 217 T3 86
valid_sources[0x09] 264329 1 T1 3860 T2 206 T3 74
valid_sources[0x0a] 258233 1 T1 2793 T2 211 T3 124
valid_sources[0x0b] 266953 1 T1 3391 T2 188 T3 109
valid_sources[0x0c] 255560 1 T1 3086 T2 230 T3 110
valid_sources[0x0d] 274318 1 T1 3189 T2 187 T3 86
valid_sources[0x0e] 341672 1 T1 4154 T2 211 T3 116
valid_sources[0x0f] 261891 1 T1 3146 T2 229 T3 90
valid_sources[0x10] 690822 1 T1 3286 T2 232 T3 98
valid_sources[0x11] 304885 1 T1 3166 T2 204 T3 106
valid_sources[0x12] 274824 1 T1 3305 T2 240 T3 86
valid_sources[0x13] 270951 1 T1 3728 T2 235 T3 114
valid_sources[0x14] 257566 1 T1 3390 T2 220 T3 95
valid_sources[0x15] 281995 1 T1 3457 T2 206 T3 85
valid_sources[0x16] 280007 1 T1 2935 T2 228 T3 103
valid_sources[0x17] 261117 1 T1 3367 T2 231 T3 86
valid_sources[0x18] 257922 1 T1 3412 T2 219 T3 100
valid_sources[0x19] 271255 1 T1 2865 T2 210 T3 83
valid_sources[0x1a] 275477 1 T1 3695 T2 219 T3 79
valid_sources[0x1b] 263674 1 T1 3492 T2 220 T3 79
valid_sources[0x1c] 264524 1 T1 3066 T2 228 T3 83
valid_sources[0x1d] 258765 1 T1 2805 T2 194 T3 89
valid_sources[0x1e] 263165 1 T1 3674 T2 200 T3 101
valid_sources[0x1f] 260066 1 T1 3575 T2 205 T3 77
valid_sources[0x20] 276230 1 T1 3580 T2 212 T3 82
valid_sources[0x21] 294381 1 T1 3894 T2 241 T3 93
valid_sources[0x22] 311031 1 T1 3253 T2 220 T3 98
valid_sources[0x23] 268138 1 T1 3527 T2 195 T3 91
valid_sources[0x24] 266738 1 T1 3012 T2 211 T3 91
valid_sources[0x25] 266657 1 T1 3638 T2 220 T3 112
valid_sources[0x26] 267276 1 T1 3730 T2 204 T3 90
valid_sources[0x27] 259405 1 T1 3367 T2 214 T3 84
valid_sources[0x28] 274525 1 T1 3089 T2 216 T3 89
valid_sources[0x29] 259190 1 T1 3310 T2 224 T3 87
valid_sources[0x2a] 268254 1 T1 3504 T2 235 T3 82
valid_sources[0x2b] 261029 1 T1 3135 T2 222 T3 81
valid_sources[0x2c] 266726 1 T1 3198 T2 188 T3 66
valid_sources[0x2d] 272314 1 T1 3795 T2 250 T3 82
valid_sources[0x2e] 253362 1 T1 3316 T2 254 T3 66
valid_sources[0x2f] 262451 1 T1 2935 T2 229 T3 103
valid_sources[0x30] 341443 1 T1 3636 T2 205 T3 109
valid_sources[0x31] 268606 1 T1 2814 T2 209 T3 99
valid_sources[0x32] 261000 1 T1 3489 T2 232 T3 70
valid_sources[0x33] 258612 1 T1 3433 T2 238 T3 112
valid_sources[0x34] 281068 1 T1 3927 T2 222 T3 100
valid_sources[0x35] 291119 1 T1 3289 T2 207 T3 85
valid_sources[0x36] 255250 1 T1 4131 T2 210 T3 115
valid_sources[0x37] 344395 1 T1 3319 T2 207 T3 101
valid_sources[0x38] 272240 1 T1 3070 T2 237 T3 95
valid_sources[0x39] 267744 1 T1 3863 T2 222 T3 88
valid_sources[0x3a] 336181 1 T1 3356 T2 199 T3 102
valid_sources[0x3b] 267088 1 T1 3256 T2 218 T3 91
valid_sources[0x3c] 260963 1 T1 3274 T2 187 T3 82
valid_sources[0x3d] 270537 1 T1 3318 T2 230 T3 110
valid_sources[0x3e] 273891 1 T1 3446 T2 245 T3 89
valid_sources[0x3f] 259481 1 T1 3413 T2 248 T3 99
valid_sources[0x40] 296746 1 T1 3469 T2 200 T3 99
valid_sources[0x41] 289421 1 T1 3384 T2 220 T3 93
valid_sources[0x42] 268590 1 T1 2991 T2 218 T3 56
valid_sources[0x43] 267729 1 T1 3472 T2 204 T3 95
valid_sources[0x44] 265443 1 T1 3478 T2 202 T3 85
valid_sources[0x45] 259821 1 T1 3515 T2 231 T3 103
valid_sources[0x46] 267500 1 T1 3032 T2 231 T3 76
valid_sources[0x47] 257325 1 T1 3770 T2 227 T3 101
valid_sources[0x48] 261528 1 T1 3453 T2 218 T3 110
valid_sources[0x49] 512339 1 T1 3016 T2 200 T3 93
valid_sources[0x4a] 265330 1 T1 3362 T2 239 T3 91
valid_sources[0x4b] 289588 1 T1 3536 T2 217 T3 90
valid_sources[0x4c] 275413 1 T1 2911 T2 230 T3 93
valid_sources[0x4d] 257743 1 T1 3176 T2 217 T3 80
valid_sources[0x4e] 331838 1 T1 3215 T2 189 T3 108
valid_sources[0x4f] 263381 1 T1 3833 T2 239 T3 94
valid_sources[0x50] 265438 1 T1 3404 T2 227 T3 88
valid_sources[0x51] 270462 1 T1 3757 T2 235 T3 95
valid_sources[0x52] 327603 1 T1 3122 T2 208 T3 81
valid_sources[0x53] 274557 1 T1 3087 T2 204 T3 69
valid_sources[0x54] 261140 1 T1 3397 T2 226 T3 109
valid_sources[0x55] 275308 1 T1 3621 T2 235 T3 94
valid_sources[0x56] 276282 1 T1 4238 T2 204 T3 72
valid_sources[0x57] 264872 1 T1 3274 T2 235 T3 111
valid_sources[0x58] 268576 1 T1 3479 T2 228 T3 105
valid_sources[0x59] 315993 1 T1 3080 T2 245 T3 86
valid_sources[0x5a] 263448 1 T1 3195 T2 224 T3 102
valid_sources[0x5b] 257748 1 T1 3251 T2 197 T3 91
valid_sources[0x5c] 262087 1 T1 3345 T2 212 T3 88
valid_sources[0x5d] 267991 1 T1 3302 T2 198 T3 103
valid_sources[0x5e] 336502 1 T1 3641 T2 214 T3 98
valid_sources[0x5f] 266799 1 T1 3306 T2 219 T3 98
valid_sources[0x60] 267045 1 T1 3265 T2 229 T3 126
valid_sources[0x61] 288013 1 T1 3353 T2 209 T3 101
valid_sources[0x62] 263024 1 T1 3187 T2 217 T3 84
valid_sources[0x63] 330831 1 T1 2855 T2 231 T3 81
valid_sources[0x64] 280062 1 T1 3810 T2 220 T3 108
valid_sources[0x65] 266553 1 T1 4397 T2 218 T3 85
valid_sources[0x66] 258575 1 T1 3154 T2 232 T3 94
valid_sources[0x67] 264451 1 T1 3622 T2 243 T3 87
valid_sources[0x68] 267946 1 T1 3682 T2 253 T3 100
valid_sources[0x69] 278420 1 T1 3557 T2 253 T3 98
valid_sources[0x6a] 281507 1 T1 3397 T2 216 T3 86
valid_sources[0x6b] 260479 1 T1 3195 T2 205 T3 82
valid_sources[0x6c] 262510 1 T1 3252 T2 244 T3 98
valid_sources[0x6d] 261187 1 T1 2829 T2 243 T3 89
valid_sources[0x6e] 296652 1 T1 3595 T2 219 T3 126
valid_sources[0x6f] 339385 1 T1 3506 T2 251 T3 91
valid_sources[0x70] 264863 1 T1 3792 T2 232 T3 99
valid_sources[0x71] 299251 1 T1 3636 T2 223 T3 93
valid_sources[0x72] 268868 1 T1 3886 T2 229 T3 90
valid_sources[0x73] 287252 1 T1 3277 T2 196 T3 100
valid_sources[0x74] 277706 1 T1 3318 T2 252 T3 92
valid_sources[0x75] 259145 1 T1 3403 T2 231 T3 86
valid_sources[0x76] 259392 1 T1 3189 T2 215 T3 92
valid_sources[0x77] 271999 1 T1 3601 T2 212 T3 97
valid_sources[0x78] 277088 1 T1 3462 T2 195 T3 105
valid_sources[0x79] 269427 1 T1 3364 T2 235 T3 88
valid_sources[0x7a] 261118 1 T1 3608 T2 216 T3 107
valid_sources[0x7b] 258479 1 T1 3431 T2 229 T3 109
valid_sources[0x7c] 695221 1 T1 2824 T2 206 T3 70
valid_sources[0x7d] 257115 1 T1 3080 T2 209 T3 105
valid_sources[0x7e] 311455 1 T1 3102 T2 255 T3 75
valid_sources[0x7f] 255509 1 T1 3999 T2 207 T3 91
valid_sources[0x80] 274146 1 T1 3234 T2 211 T3 113



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 14437372 1 T1 137183 T2 11198 T3 4724
values[0x0] all_enables biggest_size 12802009 1 T1 169080 T2 7609 T3 3207
values[0x1] all_enables biggest_size 11539853 1 T1 161175 T2 6888 T3 2865

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%