Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40842367

1

T1

768034

T2

30490

T3

12844

full_word

39059475

1

T1

491596

T2

25695

T3

10796

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79901392	1			T1	125963		T2	56185		T3	23640
auto[TlIntgErrCmd]	154	1			T54	9		T55	13		T56	9
auto[TlIntgErrData]	155	1			T54	3		T55	7		T56	11
auto[TlIntgErrBoth]	141	1			T54	8		T55	10		T56	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31709734

1

T1

505792

T2

23018

T3

9638

auto[1]

48192108

1

T1

753838

T2

33167

T3

14002

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17160599	1			T1	358865		T2	11820		T3	4914
auto[TlIntgErrNone]	partial	auto[1]	23681356	1			T1	409169		T2	18670		T3	7930
auto[TlIntgErrNone]	full_word	auto[0]	14548944	1			T1	146927		T2	11198		T3	4724
auto[TlIntgErrNone]	full_word	auto[1]	24510493	1			T1	344669		T2	14497		T3	6072
auto[TlIntgErrCmd]	partial	auto[0]	49	1			T54	4		T55	4		T112	3
auto[TlIntgErrCmd]	partial	auto[1]	96	1			T54	5		T55	7		T56	9
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T55	1		T112	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T55	1		T110	1		T113	1
auto[TlIntgErrData]	partial	auto[0]	73	1			T55	5		T56	3		T112	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T54	2		T55	2		T56	5
auto[TlIntgErrData]	full_word	auto[0]	9	1			T56	2		T113	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	11	1			T54	1		T56	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T54	3		T55	5		T56	6
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T54	5		T55	4		T56	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T112	1		T57	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T55	1		T56	1		T116	1