Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	399754699	2422826	0	0
intr_enable_rd_A	399754699	2523	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399754699	2422826	0	0
T1	484170	208373	0	0
T2	121242	0	0	0
T3	76680	0	0	0
T4	0	523633	0	0
T5	0	193899	0	0
T6	0	207629	0	0
T7	0	69499	0	0
T8	0	122331	0	0
T9	0	35404	0	0
T11	552412	0	0	0
T13	105595	0	0	0
T14	54060	0	0	0
T20	227049	0	0	0
T21	392205	0	0	0
T27	768628	0	0	0
T28	12062	0	0	0
T41	0	333432	0	0
T61	0	247804	0	0
T62	0	90166	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399754699	2523	0	0
T5	489890	0	0	0
T56	0	217	0	0
T63	111799	15	0	0
T64	0	94	0	0
T65	0	9	0	0
T66	0	41	0	0
T67	0	28	0	0
T68	0	36	0	0
T69	0	15	0	0
T70	0	23	0	0
T71	0	7	0	0
T72	21807	0	0	0
T73	5704	0	0	0
T74	901	0	0	0
T75	162422	0	0	0
T76	2935	0	0	0
T77	343374	0	0	0
T78	76706	0	0	0
T79	8329	0	0	0