Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

48950357

1

T1

115

T2

23663

T3

44278

full_word

45999119

1

T1

126

T2

20709

T3

43961

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	94949066	1			T1	241		T2	44372		T3	88239
auto[TlIntgErrCmd]	136	1			T59	12		T60	3		T61	7
auto[TlIntgErrData]	140	1			T59	9		T60	5		T61	9
auto[TlIntgErrBoth]	134	1			T59	9		T60	2		T61	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

37295780

1

T1

121

T2

17984

T3

38316

auto[1]

57653696

1

T1

120

T2

26388

T3

49923

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20284995	1			T1	62		T2	8987		T3	19007
auto[TlIntgErrNone]	partial	auto[1]	28664980	1			T1	53		T2	14676		T3	25271
auto[TlIntgErrNone]	full_word	auto[0]	17010600	1			T1	59		T2	8997		T3	19309
auto[TlIntgErrNone]	full_word	auto[1]	28988491	1			T1	67		T2	11712		T3	24652
auto[TlIntgErrCmd]	partial	auto[0]	64	1			T59	6		T60	3		T61	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1			T59	5		T61	3		T121	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T59	1		T119	1		T124	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T120	1		T118	2		T119	1
auto[TlIntgErrData]	partial	auto[0]	53	1			T59	4		T60	1		T61	3
auto[TlIntgErrData]	partial	auto[1]	79	1			T59	4		T60	4		T61	6
auto[TlIntgErrData]	full_word	auto[0]	3	1			T59	1		T120	1		T125	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T120	1		T118	1		T122	1
auto[TlIntgErrBoth]	partial	auto[0]	56	1			T59	2		T61	1		T121	2
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T59	7		T60	2		T61	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T126	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T118	1		T122	2		T127	1