Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	496502976	3769335	0	0
intr_enable_rd_A	496502976	2452	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496502976	3769335	0	0
T9	356955	157345	0	0
T10	0	362392	0	0
T11	0	79612	0	0
T12	0	143653	0	0
T13	0	257943	0	0
T25	1025	0	0	0
T45	0	382780	0	0
T52	324298	0	0	0
T53	32033	0	0	0
T65	0	82360	0	0
T66	0	195672	0	0
T67	0	56523	0	0
T68	0	49416	0	0
T69	849821	0	0	0
T70	3151	0	0	0
T71	332058	0	0	0
T72	381976	0	0	0
T73	369268	0	0	0
T74	264036	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496502976	2452	0	0
T6	194204	54	0	0
T7	49076	0	0	0
T16	126314	0	0	0
T17	0	52	0	0
T21	144280	0	0	0
T23	970	0	0	0
T24	799	0	0	0
T27	0	32	0	0
T46	89013	0	0	0
T58	67803	0	0	0
T75	0	17	0	0
T76	0	77	0	0
T77	0	44	0	0
T78	0	43	0	0
T79	0	30	0	0
T80	0	14	0	0
T81	0	24	0	0
T82	827370	0	0	0
T83	352968	0	0	0