Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42616854

1

T1

14968

T2

184524

T3

35163

full_word

41401661

1

T1

12910

T2

191471

T3

29350

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	84018025	1			T1	27878		T2	375995		T3	64513
auto[TlIntgErrCmd]	156	1			T58	10		T59	9		T60	8
auto[TlIntgErrData]	169	1			T58	9		T59	9		T60	12
auto[TlIntgErrBoth]	165	1			T58	11		T59	12		T60	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33278863

1

T1

11304

T2

146385

T3

26320

auto[1]

50739652

1

T1

16574

T2

229610

T3

38193

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17679310	1			T1	5694		T2	72721		T3	13492
auto[TlIntgErrNone]	partial	auto[1]	24937095	1			T1	9274		T2	111803		T3	21671
auto[TlIntgErrNone]	full_word	auto[0]	15599328	1			T1	5610		T2	73664		T3	12828
auto[TlIntgErrNone]	full_word	auto[1]	25802292	1			T1	7300		T2	117807		T3	16522
auto[TlIntgErrCmd]	partial	auto[0]	60	1			T58	5		T59	3		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	83	1			T58	5		T59	5		T60	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T60	1		T106	1		T107	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T59	1		T108	1		T107	1
auto[TlIntgErrData]	partial	auto[0]	82	1			T58	4		T59	3		T60	9
auto[TlIntgErrData]	partial	auto[1]	75	1			T58	4		T59	6		T60	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T58	1		T108	1		T107	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T60	1		T61	1		T106	1
auto[TlIntgErrBoth]	partial	auto[0]	63	1			T58	6		T59	3		T60	4
auto[TlIntgErrBoth]	partial	auto[1]	86	1			T58	5		T59	8		T60	6
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T59	1		T105	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T61	2		T108	1		T109	1