Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	433262615	2298638	0	0
intr_enable_rd_A	433262615	3497	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433262615	2298638	0	0
T6	216353	64748	0	0
T7	0	282297	0	0
T8	0	66133	0	0
T9	0	297792	0	0
T10	0	228478	0	0
T11	0	278542	0	0
T12	0	161276	0	0
T18	66504	0	0	0
T20	957	0	0	0
T21	1495	0	0	0
T24	196572	0	0	0
T25	126015	0	0	0
T41	3638	0	0	0
T64	0	169684	0	0
T65	0	16967	0	0
T66	0	41725	0	0
T67	47088	0	0	0
T68	334444	0	0	0
T69	48930	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433262615	3497	0	0
T59	0	194	0	0
T65	367920	0	0	0
T70	957750	31	0	0
T71	0	14	0	0
T72	0	47	0	0
T73	0	24	0	0
T74	0	33	0	0
T75	0	61	0	0
T76	0	14	0	0
T77	0	39	0	0
T78	0	16	0	0
T79	146179	0	0	0
T80	295540	0	0	0
T81	69725	0	0	0
T82	845	0	0	0
T83	134369	0	0	0
T84	186586	0	0	0
T85	37911	0	0	0
T86	543274	0	0	0