Unified Coverage Report :: Module :: hmac_core

Module : hmac_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.27	94.52	77.04		100.00	85.53

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_hmac	89.80	94.52	78.01		100.00	86.67

---

Module Instance : tb.dut.u_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.80	94.52	78.01		100.00	86.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.80	94.52	78.01		100.00	86.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
TOTAL		146	138	94.52
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ALWAYS	133	21	21	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
ALWAYS	212	16	15	93.75
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	252	12	7	58.33
ALWAYS	273	6	6	100.00
ALWAYS	283	4	4	100.00
ALWAYS	291	6	6	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	303	3	3	100.00
ALWAYS	308	64	62	96.88
CONT_ASSIGN	443	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
133	1	1
135	1	1
137	1	1
139	1	1
141	1	1
145	1	1
147	1	1
149	1	1
151	1	1
155	1	1
157	1	1
159	1	1
161	1	1
165	1	1
166	1	1
168	1	1
169	1	1
174	1	1
175	1	1
177	1	1
178	1	1
193	1	1
195	1	1
196	1	1
212	1	1
213	1	1
214	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
223	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
			MISSING_ELSE
233	0	1
236	1	1
238	1	1
244	1	1
252	1	1
253	1	1
254	1	1
255	1	1
256	1	1
259	0	1
260	0	1
261	0	1
262	0	1
264	0	1
266	1	1
267	1	1
			MISSING_ELSE
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
			MISSING_ELSE
291	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
			==> MISSING_ELSE
300	1	1
303	2	2
304	1	1
308	1	1
309	1	1
311	1	1
312	1	1
314	1	1
315	1	1
317	1	1
318	1	1
320	1	1
322	1	1
324	1	1
325	1	1
326	1	1
328	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
343	1	1
345	1	1
346	1	1
348	1	1
350	1	1
352	1	1
357	1	1
358	1	1
360	1	1
361	0	1
362	0	1
			MISSING_ELSE
365	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
377	1	1
379	1	1
380	1	1
381	1	1
383	1	1
386	1	1
391	1	1
392	1	1
393	1	1
394	1	1
396	1	1
400	1	1
402	1	1
403	1	1
404	1	1
405	1	1
407	1	1
413	1	1
414	1	1
416	1	1
417	1	1
419	1	1
421	1	1
423	1	1
429	1	1
431	1	1
443	1	1

---

Cond Coverage for Module : hmac_core

	Total	Covered	Percent
Conditions	196	151	77.04
Logical	196	151	77.04
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (hmac_en ? hash_continue : reg_hash_continue)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       125
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       125
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       126
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       193
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       193
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       193
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : (((sel_rdata == SelIPad) && (digest_size == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size == SHA2_256))
                 -----------1----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T16
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))
                 -----------1----------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T36
1	0	Not Covered
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T12,T9,T42
1	0	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T9,T42

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size == SHA2_256))
                 -----------1----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T16
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))
                 -----------1----------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T36
1	0	Not Covered
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T12,T9,T42
1	0	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T9,T42

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       217
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       218
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T1,T3,T4

 LINE       220
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T18,T15
0	1	Covered	T43,T44,T45
1	0	Covered	T46,T47,T48

 LINE       220
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T46,T47,T48

 LINE       220
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T43,T44,T45

 LINE       223
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T1,T3,T4

 LINE       227
 EXPRESSION (digest_size == SHA2_384)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T13,T36,T9

 LINE       229
 EXPRESSION (digest_size == SHA2_512)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T12,T9,T42

 LINE       238
 EXPRESSION 
 Number  Term
      1  (digest_size == SHA2_256) ? (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256) : (((digest_size == SHA2_384) || (digest_size == SHA2_512)) ? (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512) : '0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (((digest_size == SHA2_384) || (digest_size == SHA2_512)) ? (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512) : '0)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       238
 SUB-EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T15,T12,T13
1	Not Covered

 LINE       244
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       259
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       261
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (hmac_hash_done || reg_hash_start || reg_hash_continue)
             -------1------    -------2------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       300
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       300
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       358
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       360
 EXPRESSION ((round_q == Inner) && reg_hash_continue)
             ---------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       360
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       365
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       369
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       380
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       396
 EXPRESSION 
 Number  Term
      1  fifo_wready && 
      2  (((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512)) || ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || 
      2  ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512)) || 
      3  ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256))
                 ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd7)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd15)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd11)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       443
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start || reg_hash_continue) ))
             --------1-------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION ( ! (reg_hash_start || reg_hash_continue) )
                    ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : hmac_core

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	381	Covered	T1,T3,T4
StIPad	331	Covered	T1,T3,T4
StIdle	338	Covered	T1,T2,T3
StMsg	346	Covered	T1,T3,T4
StOPad	400	Covered	T1,T3,T4
StPushToMsgFifo	383	Covered	T1,T3,T4
StWaitResp	367	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	429	Covered	T1,T3,T4
StIPad->StMsg	346	Covered	T1,T3,T4
StIdle->StIPad	331	Covered	T1,T3,T4
StMsg->StWaitResp	367	Covered	T1,T3,T4
StOPad->StMsg	417	Covered	T1,T3,T4
StPushToMsgFifo->StOPad	400	Covered	T1,T3,T4
StWaitResp->StDone	381	Covered	T1,T3,T4
StWaitResp->StPushToMsgFifo	383	Covered	T1,T3,T4

---

Branch Coverage for Module : hmac_core

	Line No.	Total	Covered	Percent
Branches		76	65	85.53
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	125	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	193	2	2	100.00
TERNARY	195	2	2	100.00
TERNARY	196	7	4	57.14
TERNARY	238	3	3	100.00
TERNARY	300	2	2	100.00
CASE	133	6	5	83.33
IF	213	9	8	88.89
IF	252	7	4	57.14
IF	273	4	4	100.00
IF	283	3	3	100.00
IF	291	4	3	75.00
IF	303	2	2	100.00
CASE	328	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	123	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	195	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	196	((!hmac_en)) ? 
-2-:	196	(((sel_rdata == SelIPad) && (digest_size == SHA2_256))) ? 
-3-:	196	(((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))) ? 
-4-:	196	(((sel_rdata == SelOPad) && (digest_size == SHA2_256))) ? 
-5-:	196	(((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))) ? 
-6-:	196	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T3,T4
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	238	((digest_size == SHA2_256)) ? 
-2-:	238	(((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	133	case (key_length)

Branches:

-1-	Status	Tests
Key_128	Covered	T5,T12,T9
Key_256	Covered	T1,T2,T3
Key_384	Covered	T12,T13,T14
Key_512	Covered	T5,T6,T12
Key_1024	Covered	T18,T12,T26
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!hmac_en))
-2-:	217	if ((sel_msglen == SelIPadMsg))
-3-:	218	if ((digest_size == SHA2_256))
-4-:	220	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-5-:	223	if ((sel_msglen == SelOPadMsg))
-6-:	225	if ((digest_size == SHA2_256))
-7-:	227	if ((digest_size == SHA2_384))
-8-:	229	if ((digest_size == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T3,T4
0	1	0	1	-	-	-	-	Covered	T43,T44,T46
0	1	0	0	-	-	-	-	Covered	T5,T18,T15
0	0	-	-	1	1	-	-	Covered	T1,T3,T4
0	0	-	-	1	0	1	-	Covered	T13,T36,T9
0	0	-	-	1	0	0	1	Covered	T12,T9,T42
0	0	-	-	1	0	0	0	Covered	T16,T15,T12
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	252	if ((!rst_ni))
-2-:	254	if (clr_txcount)
-3-:	256	if (load_txcount)
-4-:	259	if ((digest_size == SHA2_256))
-5-:	261	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-6-:	266	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T4
0	0	1	1	-	-	Not Covered
0	0	1	0	1	-	Not Covered
0	0	1	0	0	-	Not Covered
0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (reg_hash_process)
-3-:	277	if (((hmac_hash_done || reg_hash_start) || reg_hash_continue))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if ((!rst_ni))
-2-:	285	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	if ((!rst_ni))
-2-:	293	if (clr_fifo_wdata_sel)
-3-:	295	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Not Covered

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	case (st_q)
-2-:	330	if ((hmac_en && reg_hash_start))
-3-:	345	if (txcnt_eq_blksz)
-4-:	360	if (((round_q == Inner) && reg_hash_continue))
-5-:	365	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-6-:	379	if (sha_hash_done)
-7-:	380	if ((round_q == Outer))
-8-:	396	if ((fifo_wready && ((((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512))) || ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384)))))
-9-:	416	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T1,T3,T4
StIPad	-	0	-	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	1	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	0	-	-	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	0	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	0	-	-	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
StDone	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
TOTAL		146	138	94.52
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
ALWAYS	133	21	21	100.00
CONT_ASSIGN	193	1	1	100.00
CONT_ASSIGN	195	1	1	100.00
CONT_ASSIGN	196	1	1	100.00
ALWAYS	212	16	15	93.75
CONT_ASSIGN	236	1	1	100.00
CONT_ASSIGN	238	1	1	100.00
CONT_ASSIGN	244	1	1	100.00
ALWAYS	252	12	7	58.33
ALWAYS	273	6	6	100.00
ALWAYS	283	4	4	100.00
ALWAYS	291	6	6	100.00
CONT_ASSIGN	300	1	1	100.00
ALWAYS	303	3	3	100.00
ALWAYS	308	64	62	96.88
CONT_ASSIGN	443	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
124	1	1
125	1	1
126	1	1
128	1	1
129	1	1
133	1	1
135	1	1
137	1	1
139	1	1
141	1	1
145	1	1
147	1	1
149	1	1
151	1	1
155	1	1
157	1	1
159	1	1
161	1	1
165	1	1
166	1	1
168	1	1
169	1	1
174	1	1
175	1	1
177	1	1
178	1	1
193	1	1
195	1	1
196	1	1
212	1	1
213	1	1
214	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
			MISSING_ELSE
223	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
			MISSING_ELSE
233	0	1
236	1	1
238	1	1
244	1	1
252	1	1
253	1	1
254	1	1
255	1	1
256	1	1
259	0	1
260	0	1
261	0	1
262	0	1
264	0	1
266	1	1
267	1	1
			MISSING_ELSE
273	1	1
274	1	1
275	1	1
276	1	1
277	1	1
278	1	1
			MISSING_ELSE
283	1	1
284	1	1
285	1	1
286	1	1
			MISSING_ELSE
291	1	1
292	1	1
293	1	1
294	1	1
295	1	1
296	1	1
			==> MISSING_ELSE
300	1	1
303	2	2
304	1	1
308	1	1
309	1	1
311	1	1
312	1	1
314	1	1
315	1	1
317	1	1
318	1	1
320	1	1
322	1	1
324	1	1
325	1	1
326	1	1
328	1	1
330	1	1
331	1	1
333	1	1
334	1	1
335	1	1
336	1	1
338	1	1
343	1	1
345	1	1
346	1	1
348	1	1
350	1	1
352	1	1
357	1	1
358	1	1
360	1	1
361	0	1
362	0	1
			MISSING_ELSE
365	1	1
367	1	1
368	1	1
369	1	1
371	1	1
372	1	1
377	1	1
379	1	1
380	1	1
381	1	1
383	1	1
386	1	1
391	1	1
392	1	1
393	1	1
394	1	1
396	1	1
400	1	1
402	1	1
403	1	1
404	1	1
405	1	1
407	1	1
413	1	1
414	1	1
416	1	1
417	1	1
419	1	1
421	1	1
423	1	1
429	1	1
431	1	1
			Exclude Annotation: VC_COV_UNR
443	1	1

---

Cond Coverage for Instance : tb.dut.u_hmac

	Total	Covered	Percent
Conditions	191	149	78.01
Logical	191	149	78.01
Non-Logical	0	0
Event	0	0

 LINE       123
 EXPRESSION (hmac_en ? hash_start : reg_hash_start)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       124
 EXPRESSION (hmac_en ? hash_continue : reg_hash_continue)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       125
 EXPRESSION (hmac_en ? (reg_hash_process | hash_process) : reg_hash_process)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       125
 SUB-EXPRESSION (reg_hash_process | hash_process)
                 --------1-------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       126
 EXPRESSION (hmac_en ? hmac_hash_done : sha_hash_done)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       193
 EXPRESSION (hmac_en ? ((st_q == StMsg) & sha_rready) : sha_rready)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T4

 LINE       193
 SUB-EXPRESSION ((st_q == StMsg) & sha_rready)
                 -------1-------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       193
 SUB-EXPRESSION (st_q == StMsg)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       195
 EXPRESSION (((!hmac_en)) ? fifo_rvalid : hmac_sha_rvalid)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       196
 EXPRESSION 
 Number  Term
      1  ((!hmac_en)) ? fifo_rdata : (((sel_rdata == SelIPad) && (digest_size == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && (digest_size == SHA2_256)) ? ('{data:i_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelIPad) && (digest_size == SHA2_256))
                 -----------1----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T16
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:i_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : (((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))
                 -----------1----------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T36
1	0	Not Covered
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelIPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T12,T9,T42
1	0	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T9,T42

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && (digest_size == SHA2_256)) ? ('{data:o_pad_256[((BlockSizeSHA256 - 1) - (32 * pad_index_256))-:32], mask:'1}) : (((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelOPad) && (digest_size == SHA2_256))
                 -----------1----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T16
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION 
 Number  Term
      1  ((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? ('{data:o_pad_512[((BlockSizeSHA512 - 1) - (32 * pad_index_512))-:32], mask:'1}) : ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0})))

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))
                 -----------1----------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T12,T13,T36
1	0	Not Covered
1	1	Not Covered

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelOPad)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       196
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T12,T9,T42
1	0	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T13,T36,T9

 LINE       196
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T12,T9,T42

 LINE       196
 SUB-EXPRESSION ((sel_rdata == SelFifo) ? fifo_rdata : ('{(*adjust*)default:'0, (*adjust*)default:'0}))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       196
 SUB-EXPRESSION (sel_rdata == SelFifo)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       217
 EXPRESSION (sel_msglen == SelIPadMsg)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       218
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T1,T3,T4

 LINE       220
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T18,T15
0	1	Covered	T43,T44,T45
1	0	Covered	T46,T47,T48

 LINE       220
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T46,T47,T48

 LINE       220
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T5,T18,T15
1	Covered	T43,T44,T45

 LINE       223
 EXPRESSION (sel_msglen == SelOPadMsg)
            -------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       225
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T1,T3,T4

 LINE       227
 EXPRESSION (digest_size == SHA2_384)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T13,T36,T9

 LINE       229
 EXPRESSION (digest_size == SHA2_512)
            ------------1------------

-1-	Status	Tests
0	Covered	T16,T15,T12
1	Covered	T12,T9,T42

 LINE       238
 EXPRESSION 
 Number  Term
      1  (digest_size == SHA2_256) ? (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256) : (((digest_size == SHA2_384) || (digest_size == SHA2_512)) ? (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512) : '0))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (txcount[BlockSizeBitsSHA256:0] == BlockSizeBSBSHA256)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       238
 SUB-EXPRESSION (((digest_size == SHA2_384) || (digest_size == SHA2_512)) ? (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512) : '0)
                 ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T13,T14
1	0	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T15,T12,T13

 LINE       238
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T13,T14

 LINE       238
 SUB-EXPRESSION (txcount[BlockSizeBitsSHA512:0] == BlockSizeBSBSHA512)
                ---------------------------1--------------------------

-1-	Status	Tests
0	Covered	T15,T12,T13
1	Not Covered

 LINE       244
 EXPRESSION (sha_rready && sha_rvalid)
             -----1----    -----2----
 Exclude Annotation: [UNR] sha_rready=1 requires sha_rvalid=1.

-1-	-2-	Status	Tests
0	1	Excluded	T1,T2,T3
1	0	Excluded
1	1	Excluded	T1,T2,T3

 LINE       259
 EXPRESSION (digest_size == SHA2_256)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 EXPRESSION ((digest_size == SHA2_384) || (digest_size == SHA2_512))
             ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       261
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       261
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       277
 EXPRESSION (hmac_hash_done || reg_hash_start || reg_hash_continue)
             -------1------    -------2------    --------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T1,T2,T3
1	0	0	Covered	T1,T3,T4

 LINE       295
 EXPRESSION (fifo_wsel && fifo_wvalid)
             ----1----    -----2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T3,T4

 LINE       300
 EXPRESSION ((round_q == Inner) ? SelIPadMsg : SelOPadMsg)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T2,T3

 LINE       300
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       330
 EXPRESSION (hmac_en && reg_hash_start)
             ---1---    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       358
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       360
 EXPRESSION ((round_q == Inner) && reg_hash_continue)
             ---------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Not Covered

 LINE       360
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       365
 EXPRESSION ((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length))
             ----------------------------------1----------------------------------    ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer))
                 ----------------------1----------------------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION ((round_q == Inner) && reg_hash_process_flag)
                 ---------1--------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (round_q == Inner)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       365
 SUB-EXPRESSION (round_q == Outer)
                ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       369
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       380
 EXPRESSION (round_q == Outer)
            ---------1--------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       396
 EXPRESSION 
 Number  Term
      1  fifo_wready && 
      2  (((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512)) || ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384))))

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION 
 Number  Term
      1  ((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || 
      2  ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512)) || 
      3  ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384)))

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T3,T4
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256))
                 ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Not Covered
1	1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd7)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_256)
                ------------1------------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T3,T4

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd15)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_512)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384))
                 ------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       396
 SUB-EXPRESSION (fifo_wdata_sel == 4'd11)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       396
 SUB-EXPRESSION (digest_size == SHA2_384)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Not Covered

 LINE       443
 EXPRESSION ((st_q == StIdle) && ( ! (reg_hash_start || reg_hash_continue) ))
             --------1-------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION (st_q == StIdle)
                --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION ( ! (reg_hash_start || reg_hash_continue) )
                    ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       443
 SUB-EXPRESSION (reg_hash_start || reg_hash_continue)
                 -------1------    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_hmac

Summary for FSM :: st_q

	Total	Covered	Percent
States	7	7	100.00	(Not included in score)
Transitions	8	8	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st_q

---

states	Line No.	Covered	Tests
StDone	381	Covered	T1,T3,T4
StIPad	331	Covered	T1,T3,T4
StIdle	338	Covered	T1,T2,T3
StMsg	346	Covered	T1,T3,T4
StOPad	400	Covered	T1,T3,T4
StPushToMsgFifo	383	Covered	T1,T3,T4
StWaitResp	367	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
StDone->StIdle	429	Covered	T1,T3,T4
StIPad->StMsg	346	Covered	T1,T3,T4
StIdle->StIPad	331	Covered	T1,T3,T4
StMsg->StWaitResp	367	Covered	T1,T3,T4
StOPad->StMsg	417	Covered	T1,T3,T4
StPushToMsgFifo->StOPad	400	Covered	T1,T3,T4
StWaitResp->StDone	381	Covered	T1,T3,T4
StWaitResp->StPushToMsgFifo	383	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_hmac

	Line No.	Total	Covered	Percent
Branches		75	65	86.67
TERNARY	123	2	2	100.00
TERNARY	124	2	2	100.00
TERNARY	125	2	2	100.00
TERNARY	126	2	2	100.00
TERNARY	193	2	2	100.00
TERNARY	195	2	2	100.00
TERNARY	196	7	4	57.14
TERNARY	238	3	3	100.00
TERNARY	300	2	2	100.00
CASE	133	6	5	83.33
IF	213	9	8	88.89
IF	252	7	4	57.14
IF	273	4	4	100.00
IF	283	3	3	100.00
IF	291	3	3	100.00
IF	303	2	2	100.00
CASE	328	17	15	88.24

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv' or '../src/lowrisc_ip_hmac_0.1/rtl/hmac_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	123	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	124	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	125	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	193	(hmac_en) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	195	((!hmac_en)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	196	((!hmac_en)) ? 
-2-:	196	(((sel_rdata == SelIPad) && (digest_size == SHA2_256))) ? 
-3-:	196	(((sel_rdata == SelIPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))) ? 
-4-:	196	(((sel_rdata == SelOPad) && (digest_size == SHA2_256))) ? 
-5-:	196	(((sel_rdata == SelOPad) && ((digest_size == SHA2_384) || (digest_size == SHA2_512)))) ? 
-6-:	196	((sel_rdata == SelFifo)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T4
0	0	1	-	-	-	Not Covered
0	0	0	1	-	-	Covered	T1,T3,T4
0	0	0	0	1	-	Not Covered
0	0	0	0	0	1	Covered	T1,T3,T4
0	0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	238	((digest_size == SHA2_256)) ? 
-2-:	238	(((digest_size == SHA2_384) || (digest_size == SHA2_512))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T15,T12,T13
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	((round_q == Inner)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	133	case (key_length)

Branches:

-1-	Status	Tests
Key_128	Covered	T5,T12,T9
Key_256	Covered	T1,T2,T3
Key_384	Covered	T12,T13,T14
Key_512	Covered	T5,T6,T12
Key_1024	Covered	T18,T12,T26
default	Not Covered

	LineNo.	Expression
-1-:	213	if ((!hmac_en))
-2-:	217	if ((sel_msglen == SelIPadMsg))
-3-:	218	if ((digest_size == SHA2_256))
-4-:	220	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-5-:	223	if ((sel_msglen == SelOPadMsg))
-6-:	225	if ((digest_size == SHA2_256))
-7-:	227	if ((digest_size == SHA2_384))
-8-:	229	if ((digest_size == SHA2_512))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
1	-	-	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	-	-	Covered	T1,T3,T4
0	1	0	1	-	-	-	-	Covered	T43,T44,T46
0	1	0	0	-	-	-	-	Covered	T5,T18,T15
0	0	-	-	1	1	-	-	Covered	T1,T3,T4
0	0	-	-	1	0	1	-	Covered	T13,T36,T9
0	0	-	-	1	0	0	1	Covered	T12,T9,T42
0	0	-	-	1	0	0	0	Covered	T16,T15,T12
0	0	-	-	0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	252	if ((!rst_ni))
-2-:	254	if (clr_txcount)
-3-:	256	if (load_txcount)
-4-:	259	if ((digest_size == SHA2_256))
-5-:	261	if (((digest_size == SHA2_384) || (digest_size == SHA2_512)))
-6-:	266	if (inc_txcount)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	-	Covered	T1,T3,T4
0	0	1	1	-	-	Not Covered
0	0	1	0	1	-	Not Covered
0	0	1	0	0	-	Not Covered
0	0	0	-	-	1	Covered	T1,T2,T3
0	0	0	-	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	273	if ((!rst_ni))
-2-:	275	if (reg_hash_process)
-3-:	277	if (((hmac_hash_done || reg_hash_start) || reg_hash_continue))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	283	if ((!rst_ni))
-2-:	285	if (update_round)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	291	if ((!rst_ni))
-2-:	293	if (clr_fifo_wdata_sel)
-3-:	295	if ((fifo_wsel && fifo_wvalid))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T3,T4
0	0	0	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	303	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	328	case (st_q)
-2-:	330	if ((hmac_en && reg_hash_start))
-3-:	345	if (txcnt_eq_blksz)
-4-:	360	if (((round_q == Inner) && reg_hash_continue))
-5-:	365	if (((((round_q == Inner) && reg_hash_process_flag) || (round_q == Outer)) && (txcount >= sha_message_length)))
-6-:	379	if (sha_hash_done)
-7-:	380	if ((round_q == Outer))
-8-:	396	if ((fifo_wready && ((((fifo_wdata_sel == 4'd7) && (digest_size == SHA2_256)) || ((fifo_wdata_sel == 4'd15) && (digest_size == SHA2_512))) || ((fifo_wdata_sel == 4'd11) && (digest_size == SHA2_384)))))
-9-:	416	if (txcnt_eq_blksz)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
StIdle	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIPad	-	1	-	-	-	-	-	-	Covered	T1,T3,T4
StIPad	-	0	-	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	1	-	-	-	-	-	Not Covered
StMsg	-	-	0	-	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	1	-	-	-	-	Covered	T1,T3,T4
StMsg	-	-	-	0	-	-	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	1	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	1	0	-	-	Covered	T1,T3,T4
StWaitResp	-	-	-	-	0	-	-	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	1	-	Covered	T1,T3,T4
StPushToMsgFifo	-	-	-	-	-	-	0	-	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	1	Covered	T1,T3,T4
StOPad	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
StDone	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	-	Not Covered