Unified Coverage Report :: Module :: tlul_socket_1n

Module : tlul_socket_1n

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.67	98.21	97.73			94.74	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_socket	99.55	98.21	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_socket

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	98.21	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	98.75	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.38	100.00	97.53			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
fifo_h	100.00	100.00	100.00			100.00	100.00
gen_dfifo[0].fifo_d	100.00	100.00	100.00			100.00	100.00
gen_dfifo[1].fifo_d	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : tlul_socket_1n

	Line No.	Total	Covered	Percent
TOTAL		56	55	98.21
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	180	6	6	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	192	4	4	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	252	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
121	1	1
			==> MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
132	1	1
145	1	1
155	2	2
157	2	2
158	2	2
159	2	2
160	2	2
161	2	2
162	2	2
163	2	2
164	2	2
167	2	2
171	2	2
180	1	1
181	1	1
183	2	2
			MISSING_ELSE
185	2	2
			MISSING_ELSE
189	1	1
192	1	1
193	1	1
194	2	2
			MISSING_ELSE
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
252	0	1

---

Cond Coverage for Module : tlul_socket_1n

	Total	Covered	Percent
Conditions	44	43	97.73
Logical	44	43	97.73
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(0))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(1))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 1'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 1'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : tlul_socket_1n

	Line No.	Total	Covered	Percent
Branches		19	18	94.74
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
IF	116	5	4	80.00
IF	183	2	2	100.00
IF	185	2	2	100.00
IF	194	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	164	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	119	if (accept_t_req)
-3-:	120	if ((!accept_t_rsp))
-4-:	124	if (accept_t_rsp)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Not Covered
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if ((dev_select_t == 1'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	if (hold_all_requests)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((dev_select_outstanding == 1'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_socket_1n

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NotOverflowed_A	433262615	433144270	0	0
maxN	734	734	0	0

NotOverflowed_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433262615	433144270	0	0
T1	197121	197029	0	0
T2	770129	770031	0	0
T3	140747	140677	0	0
T4	129822	129741	0	0
T5	803124	802926	0	0
T6	216353	216341	0	0
T19	1240	1179	0	0
T22	30406	30355	0	0
T24	196572	196522	0	0
T27	13879	13818	0	0

maxN

Name	Attempts	Real Successes	Failures	Incomplete
Total	734	734	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket

	Line No.	Total	Covered	Percent
TOTAL		56	55	98.21
CONT_ASSIGN	112	1	1	100.00
CONT_ASSIGN	113	1	1	100.00
ALWAYS	116	9	9	100.00
CONT_ASSIGN	132	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	157	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	158	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	159	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	161	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	162	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	164	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
ALWAYS	180	6	6	100.00
CONT_ASSIGN	189	1	1	100.00
ALWAYS	192	4	4	100.00
CONT_ASSIGN	197	1	1	100.00
CONT_ASSIGN	198	1	1	100.00
CONT_ASSIGN	199	1	1	100.00
CONT_ASSIGN	200	1	1	100.00
CONT_ASSIGN	201	1	1	100.00
CONT_ASSIGN	202	1	1	100.00
CONT_ASSIGN	203	1	1	100.00
CONT_ASSIGN	204	1	1	100.00
CONT_ASSIGN	205	1	1	100.00
CONT_ASSIGN	252	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
119	1	1
120	1	1
121	1	1
			==> MISSING_ELSE
123	1	1
124	1	1
125	1	1
			MISSING_ELSE
132	1	1
145	1	1
155	2	2
157	2	2
158	2	2
159	2	2
160	2	2
161	2	2
162	2	2
163	2	2
164	2	2
167	2	2
171	2	2
180	1	1
181	1	1
183	2	2
			MISSING_ELSE
185	2	2
			MISSING_ELSE
189	1	1
192	1	1
193	1	1
194	2	2
			MISSING_ELSE
197	1	1
198	1	1
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
204	1	1
205	1	1
252	0	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_socket

	Total	Covered	Percent
Conditions	43	43	100.00
Logical	43	43	100.00
Non-Logical	0	0
Event	0	0

 LINE       112
 EXPRESSION (tl_t_o.a_valid & tl_t_i.a_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       113
 EXPRESSION (tl_t_i.d_valid & tl_t_o.d_ready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T19
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION ((num_req_outstanding != '0) & (dev_select_t != dev_select_outstanding))
             -------------1-------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T5

 LINE       132
 SUB-EXPRESSION (num_req_outstanding != '0)
                -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       132
 SUB-EXPRESSION (dev_select_t != dev_select_outstanding)
                --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(0)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(0))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       155
 EXPRESSION ((dev_select_t == 1'(1)) & ((~hold_all_requests)))
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       155
 SUB-EXPRESSION (dev_select_t == 1'(1))
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[0].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (tl_t_o.a_valid & gen_u_o[1].dev_select)
             -------1------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       164
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_data : tlul_pkg::BlankedAData)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[0].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       167
 EXPRESSION (gen_u_o[1].dev_select ? tl_t_o.a_user : blanked_auser)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 EXPRESSION (dev_select_t == 1'(idx))
            ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       189
 EXPRESSION (tl_t_o.a_valid & hfifo_reqready)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (dev_select_outstanding == 1'(idx))
            -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_socket

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
TERNARY	164	2	2	100.00
TERNARY	167	2	2	100.00
IF	116	4	4	100.00
IF	183	2	2	100.00
IF	185	2	2	100.00
IF	194	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_socket_1n.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	164	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(gen_u_o[0].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	167	(gen_u_o[1].dev_select) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	116	if ((!rst_ni))
-2-:	119	if (accept_t_req)
-3-:	120	if ((!accept_t_rsp))
-4-:	124	if (accept_t_rsp)

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T1,T2,T3
0	1	1	-	Covered	T1,T2,T3
0	1	0	-	Excluded		VC_COV_UNR
0	0	-	1	Covered	T1,T2,T3
0	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	183	if ((dev_select_t == 1'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	185	if (hold_all_requests)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	194	if ((dev_select_outstanding == 1'(idx)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

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Assert Coverage for Instance : tb.dut.u_reg.u_socket

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NotOverflowed_A	433262615	433144270	0	0
maxN	734	734	0	0

NotOverflowed_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	433262615	433144270	0	0
T1	197121	197029	0	0
T2	770129	770031	0	0
T3	140747	140677	0	0
T4	129822	129741	0	0
T5	803124	802926	0	0
T6	216353	216341	0	0
T19	1240	1179	0	0
T22	30406	30355	0	0
T24	196572	196522	0	0
T27	13879	13818	0	0

maxN

Name	Attempts	Real Successes	Failures	Incomplete
Total	734	734	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T22	1	1	0	0
T24	1	1	0	0
T27	1	1	0	0