Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	37862033	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

40339975

1

T1

221

T2

137

T3

184236

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	31284788	1			T1	209		T2	143		T3	143065
values[0x0]	21871678	1			T1	95		T2	54		T3	104709
values[0x1]	25045542	1			T1	116		T2	80		T3	117037

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27833502	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

50368506

1

T1

269

T2

170

T3

228884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	256612	1			T1	2		T5	429		T19	3
valid_sources[0x01]	252458	1			T1	1		T5	420		T6	42
valid_sources[0x02]	258168	1			T5	455		T19	1		T6	190
valid_sources[0x03]	249185	1			T5	373		T6	53		T7	12
valid_sources[0x04]	266126	1			T1	2		T5	503		T6	64
valid_sources[0x05]	248880	1			T1	3		T4	367		T5	380
valid_sources[0x06]	263061	1			T1	1		T24	1		T5	452
valid_sources[0x07]	252673	1			T4	2		T5	383		T6	72
valid_sources[0x08]	251820	1			T5	404		T6	226		T7	15
valid_sources[0x09]	666856	1			T1	2		T5	366		T6	41
valid_sources[0x0a]	615747	1			T1	1		T5	578		T19	14
valid_sources[0x0b]	269352	1			T1	1		T5	607		T6	51
valid_sources[0x0c]	259263	1			T1	8		T24	1		T4	25
valid_sources[0x0d]	245824	1			T1	2		T5	552		T19	12
valid_sources[0x0e]	682055	1			T5	473		T6	49		T7	13
valid_sources[0x0f]	273220	1			T1	1		T24	1		T5	542
valid_sources[0x10]	261235	1			T1	5		T5	309		T6	42
valid_sources[0x11]	275274	1			T4	2		T5	408		T19	6
valid_sources[0x12]	250291	1			T1	1		T5	463		T19	3
valid_sources[0x13]	257934	1			T1	2		T5	422		T6	41
valid_sources[0x14]	260481	1			T5	386		T19	5		T6	92
valid_sources[0x15]	610797	1			T1	1		T4	187		T5	439
valid_sources[0x16]	256881	1			T1	3		T5	466		T6	96
valid_sources[0x17]	267345	1			T1	1		T5	380		T6	55
valid_sources[0x18]	250877	1			T1	1		T4	37		T5	340
valid_sources[0x19]	740522	1			T1	1		T5	538		T6	58
valid_sources[0x1a]	271109	1			T5	326		T19	1		T6	54
valid_sources[0x1b]	250037	1			T1	3		T5	458		T6	55
valid_sources[0x1c]	251722	1			T1	2		T5	433		T19	3
valid_sources[0x1d]	265094	1			T5	415		T19	3		T6	136
valid_sources[0x1e]	252928	1			T1	1		T5	545		T6	74
valid_sources[0x1f]	716232	1			T1	2		T5	448		T6	84
valid_sources[0x20]	253940	1			T1	1		T4	5		T5	563
valid_sources[0x21]	287040	1			T5	443		T6	185		T7	18
valid_sources[0x22]	299894	1			T5	422		T19	5		T6	43
valid_sources[0x23]	252895	1			T5	444		T19	24		T6	56
valid_sources[0x24]	248400	1			T5	650		T6	60		T7	20
valid_sources[0x25]	257466	1			T5	416		T6	55		T7	10
valid_sources[0x26]	259534	1			T1	3		T5	496		T19	1
valid_sources[0x27]	253961	1			T1	3		T5	509		T6	81
valid_sources[0x28]	262376	1			T1	3		T5	480		T19	3
valid_sources[0x29]	259158	1			T1	2		T5	376		T6	81
valid_sources[0x2a]	1061407	1			T4	307		T5	436		T6	141
valid_sources[0x2b]	244820	1			T5	279		T6	64		T7	17
valid_sources[0x2c]	249901	1			T1	1		T5	370		T19	4
valid_sources[0x2d]	258252	1			T1	3		T5	358		T6	107
valid_sources[0x2e]	259044	1			T1	5		T4	81		T5	440
valid_sources[0x2f]	248921	1			T5	501		T6	42		T7	11
valid_sources[0x30]	254175	1			T1	2		T5	459		T6	49
valid_sources[0x31]	254454	1			T5	485		T6	58		T7	12
valid_sources[0x32]	264747	1			T1	3		T5	385		T6	276
valid_sources[0x33]	652827	1			T5	383		T6	43		T7	16
valid_sources[0x34]	249742	1			T1	2		T5	418		T19	2
valid_sources[0x35]	249476	1			T1	3		T5	399		T19	2
valid_sources[0x36]	287800	1			T1	1		T5	513		T19	6
valid_sources[0x37]	262126	1			T5	400		T19	2		T6	59
valid_sources[0x38]	254485	1			T1	3		T5	543		T19	3
valid_sources[0x39]	264932	1			T5	418		T19	2		T6	35
valid_sources[0x3a]	254831	1			T1	1		T24	1		T4	7
valid_sources[0x3b]	255912	1			T1	1		T5	435		T19	2
valid_sources[0x3c]	274399	1			T1	1		T5	436		T6	79
valid_sources[0x3d]	301913	1			T5	465		T19	12		T6	27
valid_sources[0x3e]	611329	1			T1	3		T5	469		T6	46
valid_sources[0x3f]	251467	1			T1	3		T4	13		T5	579
valid_sources[0x40]	245349	1			T1	2		T5	580		T19	11
valid_sources[0x41]	251393	1			T1	2		T5	344		T6	58
valid_sources[0x42]	253939	1			T5	437		T6	75		T7	15
valid_sources[0x43]	263013	1			T1	1		T5	364		T19	1
valid_sources[0x44]	260934	1			T5	311		T6	73		T7	22
valid_sources[0x45]	265261	1			T1	1		T5	439		T19	5
valid_sources[0x46]	250595	1			T24	1		T5	530		T19	1
valid_sources[0x47]	257527	1			T1	1		T5	445		T19	14
valid_sources[0x48]	247562	1			T1	1		T5	371		T6	51
valid_sources[0x49]	253618	1			T1	1		T5	475		T19	5
valid_sources[0x4a]	253127	1			T1	1		T5	436		T6	28
valid_sources[0x4b]	275915	1			T1	5		T5	425		T6	48
valid_sources[0x4c]	249004	1			T1	2		T5	444		T6	67
valid_sources[0x4d]	316469	1			T1	4		T5	447		T19	2
valid_sources[0x4e]	259839	1			T1	1		T5	452		T19	8
valid_sources[0x4f]	301031	1			T1	4		T5	598		T19	2
valid_sources[0x50]	259253	1			T1	3		T5	425		T6	25
valid_sources[0x51]	263203	1			T1	5		T5	461		T6	35
valid_sources[0x52]	615204	1			T1	1		T5	353		T6	76
valid_sources[0x53]	679922	1			T5	299		T19	15		T6	63
valid_sources[0x54]	254226	1			T1	3		T5	401		T19	2
valid_sources[0x55]	696399	1			T1	2		T5	376		T6	70
valid_sources[0x56]	257179	1			T1	1		T24	1		T5	403
valid_sources[0x57]	258312	1			T1	1		T4	18		T5	424
valid_sources[0x58]	280365	1			T1	2		T5	250		T6	114
valid_sources[0x59]	265772	1			T1	2		T5	424		T19	10
valid_sources[0x5a]	265928	1			T4	5		T5	461		T6	81
valid_sources[0x5b]	254977	1			T1	2		T5	403		T19	10
valid_sources[0x5c]	276246	1			T1	2		T5	515		T19	7
valid_sources[0x5d]	605072	1			T1	3		T4	22		T5	436
valid_sources[0x5e]	257965	1			T1	1		T4	84		T5	462
valid_sources[0x5f]	298370	1			T1	1		T5	540		T6	59
valid_sources[0x60]	262471	1			T1	1		T5	429		T6	60
valid_sources[0x61]	266287	1			T1	5		T5	500		T6	39
valid_sources[0x62]	270369	1			T1	1		T5	539		T6	51
valid_sources[0x63]	244852	1			T1	1		T5	400		T6	71
valid_sources[0x64]	256343	1			T4	9		T5	486		T6	66
valid_sources[0x65]	254677	1			T5	426		T6	37		T7	11
valid_sources[0x66]	276878	1			T1	1		T5	324		T6	41
valid_sources[0x67]	252272	1			T1	2		T5	458		T6	67
valid_sources[0x68]	261552	1			T2	277		T5	502		T6	73
valid_sources[0x69]	270821	1			T1	2		T5	483		T19	3
valid_sources[0x6a]	295655	1			T5	327		T6	18		T7	20
valid_sources[0x6b]	257117	1			T1	3		T5	424		T6	51
valid_sources[0x6c]	1067591	1			T1	1		T5	569		T6	68
valid_sources[0x6d]	630084	1			T1	4		T5	556		T19	16
valid_sources[0x6e]	254267	1			T1	1		T5	638		T6	61
valid_sources[0x6f]	257641	1			T1	4		T5	571		T6	97
valid_sources[0x70]	271059	1			T1	3		T4	86		T5	390
valid_sources[0x71]	256348	1			T1	4		T5	475		T19	5
valid_sources[0x72]	247786	1			T1	3		T5	506		T19	7
valid_sources[0x73]	254718	1			T5	422		T6	80		T7	19
valid_sources[0x74]	295128	1			T1	1		T5	471		T19	1
valid_sources[0x75]	281041	1			T1	4		T5	428		T6	47
valid_sources[0x76]	263946	1			T1	2		T5	413		T19	4
valid_sources[0x77]	271915	1			T1	1		T5	359		T6	83
valid_sources[0x78]	247858	1			T1	3		T5	492		T6	85
valid_sources[0x79]	257532	1			T1	2		T5	343		T6	50
valid_sources[0x7a]	266226	1			T5	296		T6	301		T7	12
valid_sources[0x7b]	258870	1			T1	1		T5	533		T19	4
valid_sources[0x7c]	257381	1			T1	1		T5	495		T19	16
valid_sources[0x7d]	284612	1			T1	1		T5	452		T6	26
valid_sources[0x7e]	258022	1			T1	3		T5	468		T19	2
valid_sources[0x7f]	270634	1			T1	1		T5	398		T6	115
valid_sources[0x80]	301584	1			T1	1		T5	503		T19	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

15077420

1

T1

97

T2

70

T3

71381

values[0x0]

all_enables

biggest_size

13298006

1

T1

60

T2

31

T3

60618

values[0x1]

all_enables

biggest_size

11964549

1

T1

64

T2

36

T3

52237