Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

42172547

1

T1

199

T2

140

T3

180575

full_word

40621404

1

T1

221

T2

137

T3

184236

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	82793561	1			T1	420		T2	277		T3	364811
auto[TlIntgErrCmd]	136	1			T64	11		T65	9		T66	12
auto[TlIntgErrData]	138	1			T64	12		T65	5		T66	9
auto[TlIntgErrBoth]	116	1			T64	7		T65	6		T66	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32754865

1

T1

209

T2

143

T3

143065

auto[1]

50039086

1

T1

211

T2

134

T3

221746

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	17565425	1			T1	112		T2	73		T3	71684
auto[TlIntgErrNone]	partial	auto[1]	24606770	1			T1	87		T2	67		T3	108891
auto[TlIntgErrNone]	full_word	auto[0]	15189265	1			T1	97		T2	70		T3	71381
auto[TlIntgErrNone]	full_word	auto[1]	25432101	1			T1	124		T2	67		T3	112855
auto[TlIntgErrCmd]	partial	auto[0]	46	1			T64	5		T65	2		T66	4
auto[TlIntgErrCmd]	partial	auto[1]	76	1			T64	5		T65	5		T66	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T64	1		T65	1		T66	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T65	1		T66	2		T118	1
auto[TlIntgErrData]	partial	auto[0]	62	1			T64	8		T65	2		T66	4
auto[TlIntgErrData]	partial	auto[1]	63	1			T64	4		T65	2		T66	3
auto[TlIntgErrData]	full_word	auto[0]	7	1			T65	1		T118	1		T117	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T66	2		T115	1		T119	1
auto[TlIntgErrBoth]	partial	auto[0]	47	1			T64	1		T65	1		T66	5
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T64	5		T65	4		T66	4
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T65	1		T115	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T64	1		T116	1		T120	1