Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	426297775	2444648	0	0
intr_enable_rd_A	426297775	2953	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426297775	2444648	0	0
T9	335796	144833	0	0
T10	0	12634	0	0
T11	0	206786	0	0
T12	0	345179	0	0
T28	0	212224	0	0
T35	4364	0	0	0
T72	0	58614	0	0
T73	0	115479	0	0
T74	0	404902	0	0
T75	0	17195	0	0
T76	0	222836	0	0
T77	121491	0	0	0
T78	57773	0	0	0
T79	321243	0	0	0
T80	794719	0	0	0
T81	766743	0	0	0
T82	141395	0	0	0
T83	96604	0	0	0
T84	1395	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	426297775	2953	0	0
T15	114928	35	0	0
T21	113988	0	0	0
T26	1114	0	0	0
T60	180857	0	0	0
T61	5246	0	0	0
T62	25468	0	0	0
T63	204539	0	0	0
T69	0	58	0	0
T85	0	61	0	0
T86	0	20	0	0
T87	0	22	0	0
T88	0	15	0	0
T89	0	37	0	0
T90	0	42	0	0
T91	0	36	0	0
T92	0	24	0	0
T93	127770	0	0	0
T94	5819	0	0	0
T95	3106	0	0	0