Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

40515357

1

T1

107748

T2

124

T3

23335

full_word

38985422

1

T1

145203

T2

132

T3

20268

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	79500349	1			T1	252951		T2	256		T3	43603
auto[TlIntgErrCmd]	146	1			T58	8		T59	9		T60	3
auto[TlIntgErrData]	142	1			T58	12		T59	13		T60	7
auto[TlIntgErrBoth]	142	1			T58	10		T59	8		T105	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31287948

1

T1

95189

T2

127

T3

17802

auto[1]

48212831

1

T1

157762

T2

129

T3

25801

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	16997025	1			T1	48875		T2	67		T3	8913
auto[TlIntgErrNone]	partial	auto[1]	23517937	1			T1	58873		T2	57		T3	14422
auto[TlIntgErrNone]	full_word	auto[0]	14290731	1			T1	46314		T2	60		T3	8889
auto[TlIntgErrNone]	full_word	auto[1]	24694656	1			T1	98889		T2	72		T3	11379
auto[TlIntgErrCmd]	partial	auto[0]	48	1			T58	3		T59	3		T112	5
auto[TlIntgErrCmd]	partial	auto[1]	89	1			T58	5		T59	6		T60	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T109	1		T113	1		T107	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T114	1		T108	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T58	5		T59	3		T60	4
auto[TlIntgErrData]	partial	auto[1]	62	1			T58	7		T59	9		T60	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T59	1		T60	1		T109	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T110	1		T107	1		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T58	4		T59	3		T112	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T58	6		T59	4		T105	1
auto[TlIntgErrBoth]	full_word	auto[0]	9	1			T59	1		T113	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T110	1		T117	1		T118	1