Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.26	93.44	77.86	100.00	40.00	88.24	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	416836388	2669506	0	0
intr_enable_rd_A	416836388	3361	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416836388	2669506	0	0
T5	0	115238	0	0
T6	0	231298	0	0
T7	0	223446	0	0
T8	0	213507	0	0
T9	0	116638	0	0
T10	0	221401	0	0
T12	101300	44371	0	0
T13	350342	157077	0	0
T46	3169	0	0	0
T47	169133	0	0	0
T63	0	219186	0	0
T64	0	61331	0	0
T65	18204	0	0	0
T66	302891	0	0	0
T67	1453	0	0	0
T68	560592	0	0	0
T69	184824	0	0	0
T70	21025	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416836388	3361	0	0
T42	714915	42	0	0
T43	0	59	0	0
T48	123143	0	0	0
T58	0	228	0	0
T71	0	20	0	0
T72	0	71	0	0
T73	0	22	0	0
T74	0	23	0	0
T75	0	39	0	0
T76	0	21	0	0
T77	0	5	0	0
T78	17541	0	0	0
T79	801341	0	0	0
T80	189619	0	0	0
T81	3118	0	0	0
T82	45787	0	0	0
T83	954	0	0	0
T84	291737	0	0	0
T85	119319	0	0	0