Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

37259142

1

T1

2

T2

12756

T3

98463

full_word

36331021

1

T1

1

T2

11046

T3

90090

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	73589783	1			T1	3		T2	23802		T3	188553
auto[TlIntgErrCmd]	122	1			T57	5		T58	2		T59	6
auto[TlIntgErrData]	126	1			T57	2		T58	3		T59	3
auto[TlIntgErrBoth]	132	1			T57	3		T58	5		T59	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29065129

1

T1

1

T2

14182

T3

79883

auto[1]

44525034

1

T1

2

T2

9620

T3

108670

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	15497852	1			T1	1		T2	12507		T3	39832
auto[TlIntgErrNone]	partial	auto[1]	21760947	1			T1	1		T2	249		T3	58631
auto[TlIntgErrNone]	full_word	auto[0]	13567116	1			T2	1675		T3	40051		T4	334
auto[TlIntgErrNone]	full_word	auto[1]	22763868	1			T1	1		T2	9371		T3	50039
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T57	2		T59	4		T111	1
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T57	3		T58	2		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T111	1		T110	2		T112	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T114	1		T116	1		T115	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T58	3		T59	2		T114	5
auto[TlIntgErrData]	partial	auto[1]	62	1			T57	1		T59	1		T111	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T57	1		T110	1		T114	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T110	1		T115	1		T117	1
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T57	2		T58	2		T111	2
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T57	1		T58	2		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T110	1		T116	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T58	1		T111	1		T114	1